Computer System A rc h i tec ture( 5 ) Computer System A rc h i tec ture( 5 )
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Computer SystemA rc h i tec ture( 5 ����)Computer SystemA rc h i tec ture( 5 ����)
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• � � � �� � � �� � � �� � � � � � � � ! " ! " ! " ! " # $# $# $# $
• # %# %# %# % � � �� � �� � �� � � & '& '& '& '
• ( ) #( ) #( ) #( ) # * � +* � +* � +* � + & '& '& '& '
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INTRODUCTIONINTRODUCTION
� �� � � � �� � � � � � � � � � �.( d i f f e r e n t r e g i s t e r s , b u s e s , m i c r o o p e r a t i o n s , m a c h i n e i n s t r u c t i o n s , e t c )� � �� � �� � � � � � � � � � ��.
- � ! " -��� � � � � .� � � � � � � � � �� � � � � � � � � � � .� � � � � � � � � � ! " � � # P i p e l i n e $� � %& � .� E t c .
� � �� � � # $ % & ' ( ) * � �+ �,� - . / 0 1 � �� 23 4 � 5 & 6 7 ��.
� 2 5 8 9 : ; < = � �� � > � ? @ � �.� M . M o r r i s M a n o � . A � � �� 2 3 4 ( " B � C B a s i c C o m p u t e rD E F �.
� P r o c e s s o r � � G R T L M o d e lH h i g h e r l e v e l c o m p u t e r � � I �, " B � J �.
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TH E B A S IC COM P UTE RTH E B A S IC COM P UTE R
� B a s i c C o m p u t e r � p r o c e s s o r K m e m o r r y L B � C o m p o n e n t s � � ��.
� M e m o r y � 4 0 9 6 w o r d � � � �.� 4 0 9 6 = 2 12, ' ( ) * + , - ) 1 2 b i t s - . � w o r d % / 0 1 � .
� M M � w o r d � 1 6 b i t s � N # O �.
CPU RAM0
4095
015
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INS TRUCTIONSInstruction codes
������ A s e q u e n c e o f ( m a c h i n e ) i n s t r u c t i o n s - E P # Q �
� (Machine) Instruction� R S ; I � T U N � S p e c i f i c o p e r a t i o n ( V � � b i t �W X .
������ � � � � � � � � � m em ory� � � � � .
� C P U � m em ory �� � � � � � � � � � � � .� Instruction Register (IR )� � � � � .� C ontrol unit� C ontrol circuitry � m icroop eration�seq uence � � � � � ! " �� � # $ � .
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������������ � �� �� �� �Instruction codes
� % & � � � � � ' ' ( � ) * � + , � .� O p e r a t i o n C o d e ( o p c o d e )� Y Z I �� [ ���.� Y Z � \ ] , @ ^ N � _ Y Z ( a n d / o r )� ` � 1 a 3 *b � c " .
� 4 0 9 6 (= 2 12) - . � / 0 1 2 � 3 � 4 5 1 2 67 � 8 9 / " � .
� 1 : % & � �5 � , 1 5 ; < b it � � � 8 9 = >�(a d d r e s s i n g m o d e ) ��� � � � � .
(0: �� � � � � , 1 : � � � � � � )� ? @ A - . B C � � � 1 6 b it D � 3 b its � � �� + E F � op cod e � .
Opcode Address
Instruction Format
15 14 12 0I
11
Addressibgmode
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A DDRE S S ING M ODE SInstruction codes
� � �� � � � � � � � � .� 2 3 4 : * + , 4 - 5 $� � - 6 7 � # 8 7 $ 9 � � � . � : 3 4 : * + , 4 - 5 $� � - 6 7 � # 8 7 $ 9 � � #
4 % 9 � � �
; < 4 - Effective Address (EA)� = > � � � . 2 3 � ? @ � A . 4 .� B � , C D > � � � -) E F 1 G � 4 .
0 ADD 45722
Operand457
1 ADD 30035
1350300
Operand1350
+AC
+AC
Direct addressing Indirect addressing
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PROCESSOR REGISTERSInstruction codes
� ����� � � � � � � � � � � � � � � .(a d d r e s s e s , d a t a , e t c )
� ����� � � � � � �� � � � � � Program Counter (P C ) � � � �� � � � � � .� 4096� � � � � �� � � � � P C 1 2 b i t s � � � � � .
� � �� ! " # $ % & �� , ����� ' ( ) * ! + , - � � � �� � . & " # / 0 � . : A d d res s R egi s ter (A R )� � � � � � A R � 1 2 b i t � � � � � � � � � .
� � � � � 1 �� 2 � �� � 3 4 5 6 # �7 8 9 : ; D ata R egi s ter (D R )� 3 4 5 6 � . � � � ! < = > ? 8 + , - � � � .
� $ @ A B � � C D E F G E � # 2 � � � � � � H I � .– t h e Accumulator (A C )
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PROCESSOR REGISTERSInstruction codes
� def g f h + 2 ; � i ! � E P # K j k � O �.� H � I �J * + , K L M N - O P Q R AC % � S 1 � .
; AC - * + , K L - M N $ � T � � K L 1 � .� l l ) * \ � m 5 i . n H � �̀ � o d5 fp q � r � `� , s ( T � O �.
; \ t R S ; I � � Temporary Register (T R )D � �.� \ t R S ; � � � . A � i n p u t / o u t p u t (I / O ) Y Z ( � �.
� U V L W # ch a ra cter da ta X , Y � Q Z 8 [ \ Y ] ^ 9 ? � . � X , D # _ V L W - 8 [ \ 5 $ � Y ` a � � � .
� I n pu t Register (I N P R ) I � � u � � � : ; 8 b i t c h a r a c t e r � v��.
� O u tpu t Register (O U T R ) I � � w u � � � 8 b i t c h a r a c t e r � x y�.
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B A SIC COM PU TER REGISTERS
List of BC Registers
DR 16 Data Register Holds memory operandAR 12 Address Register Holds address for memoryAC 16 Accumulator Processor registerIR 16 Instruction Register Holds instruction codePC 12 Program Counter Holds address of instructionTR 16 Temporary Register Holds temporary dataINPR 8 Input Register Holds input characterOUTR 8 Output Register Holds output character
Registers
Registers in the Basic Computer
11 0PC
15 0IR
15 0TR
7 0OUTR
15 0DR
15 0AC
11 0AR
INPR0 7
Memory
4096 x 16
CPU
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COM M ON B U S SY STEMRegisters
� \ t R S ; I � � h + 2 ; > � z2 I Y n N # @ ^ 1 �.
� h + 2 ; > { * Y n 1 | � " } ~ I � �̀ 1 �.
12������������������ ������������ �� � � � ��
COM M ON B U S SY STEMRegisters
S2S1S0 Bus
Memory unit4096 x 16
LD INR CLR
AddressReadWrite
AR
LD INR CLR
PC
LD INR CLR
DR
LD INR CLR
ACALUE
INPRIR
LD
LD INR CLR
TR
OUTRLD
Clock
16-bit common bus
7
1
2
3
4
5
6
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COM M ON B U S SY STEMRegisters
AR
PC
DR
L I C
L I C
L I C
AC
L I C
ALUE
IR
L
TR
L I C
OUTR LD
INPRMemory
4096 x 16Address
Read
Write
16-bit Common Bus7 1 2 3 4 5 6
S0 S1 S2
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COM M ON B U S SY STEMRegisters
� � B � = # Dp S2 , S 1 , S0� z2 � u �� � = # � �.
� �� � � h + 2 ; � � � �� � T U � o a 3 * I ��� � � # � �. � b � - c � d 5 $ � Y � J � .
� 12 � � h + 2 ; A R , P C � 0( � � � � ( � z2 ]I �] 4 � � � # � �.
� 8 � � h + 2 ; O U T R �z2 � : ; � � � � q � ; � z2 � � ] 8 � � � � # � � �.
0 0 0 x0 0 1 AR0 1 0 PC0 1 1 DR1 0 0 AC1 0 1 IR1 1 0 TR1 1 1 Memory
S2 S1 S0 Register
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B A SIC COM PU TER IN STRU CTION SInstructions
•�������� � � �� � �� � �� � � � � �� � �� � �� � �
15 14 12 11 0I Opcode Address
Memory-Reference Instructions (OP-code = 000 ~ 110)
Register-Reference Instructions (OP-code = 111, I = 0)
Input-Output Instructions (OP-code =111, I = 1)
15 12 11 0Register operation0 1 1 1
15 12 11 0I/O operation1 1 1 1
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B A SIC COM PU TER IN STRU CTION SInstructions
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IN STRU CTION SET COM PL ETEN ESS
� � � �� � �� � �� � � � �� �� �� �
� � � � � � � � � � � � � � � � �� � � �� � � �� � � � � � � � �� � � � �� � � � �� � � � � �� � ��� � ��� � ��� � � ���� � � � � �� � � � �� � � � �� � � � � � �� �� �� � ����
! " ! " ! " ! " # $ % & ' ( ) & # * $ + % , &# $ % & ' ( ) & # * $ + % , &# $ % & ' ( ) & # * $ + % , &# $ % & ' ( ) & # * $ + % , & ���� � - .� - .� - .� - . / / / / 0000
�������� � � �� � �� � �� � �
- Arithmetic, logic, and shift instructions- ADD, CMA, INC, CIR, CIL, AND, CLA
� �� �� �� � � � �� � �� � �� � �
- Data transfers between the main memory and the processor registers
- LDA, STA� �� �� �� � � � �� � �� � �� � �
- Program sequencing and control- BUN, BSA, ISZ
� � � � � � �� � �� � �� � �
- Input and output- INP, OUT
Instructions
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CON TROL U N ITInstruction codes
� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ( ], �� � � � � � � � � � � � ( � � � �� � ¡ �¢�
� � � � � � � � � � � � � � L �+ £ ¤ ¥ � � � � 1 �¢
¦ § � � ¨ © � � � ¨ � � � � � � �
� e f # g � h i Y j � Q D � � ) k l m n l o p q r s t u q v u n q p k wu x y z q o r p q x o r s t u q v u n q p k � � O 9 � & � { t
¦ ª � � � � � � � « � � � � � ¨ � � � � � � �
� | � } ) . u x o p v x s t y l y x v ~ # � � � J g � h i Y � � � T� # y q u v x � v x � v r y 9 � � � J � { t
� � * � \ t R S ; � � � � � � � � � � � � � � ¬ � � ¨ © � � � ¨ fp � � I� � � ® ¯ 7 � �¢�
19������������������ ������������ �� � � � ��
TIM IN G A N D CON TROL
Control unit of Basic Computer
Timing and control
Instruction register (IR)15 14 13 12 11 - 0
3 x 8decoder
7 6 5 4 3 2 1 0
ID0
15 14 . . . . 2 1 04 x 16
decoder
4-bitsequence
counter(SC)
Increment (INR)Clear (CLR)Clock
Other inputs
Controlsignals
D
T
T
7
15
0
CombinationalControl
logic
20������������������ ������������ �� � � � ��
TIM IN G SIGN A L S
ClockT0 T1 T2 T3 T4 T0
T0
T1
T2
T3
T4
D3
CLR SC
- 4-bit � � � � � � �� � �� � �� � � ���� 4×16 decoder���� � � �� � �� � �� � �
- SC���� � �� �� �� � � �� �� �� � .
- Example: T0, T1, T2, T3, T4, T0, T1, . . .Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC ← 0
Timing and control
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IN STRU CTION CY CL EIN STRU CTION CY CL E
� \ t R S ; � \ � E P # � �° � @ � ± � ² T U 1 �.1 . F etch a n in stru ctio n fro m m em o ry2 . D eco de th e in stru ctio n3 . R ea d th e effective a ddress fro m m em o ry if th e in stru ctio n h a s a n
in direct a ddress4. Ex ecu te th e in stru ctio n
� E P # @ � ± � 12 ³ ´ T U 1 �.
� c � : � � � � µ � �� E P # @ � ± ( �+ - O �.
22������������������ ������������ �� � � � ��
F ETCH a n d D ECOD E
• Fetch and Decode T0: AR ← PC (S0S1S2=010, T0=1)T1: IR ← M [AR], PC ← PC + 1 (S0S1S2=111, T1=1)T2: D0, . . . , D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)
S2
S1
S0
Bus
7Memoryunit
AddressRead
AR
LD
PC
INR
IR
LD Clock
1
2
5
Common bus
T1
T0
Instruction Cycle
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D ETERM IN E TH E TY PE OF IN STRU CTION
D'7IT3: AR ← M[AR]D'7I'T3: NothingD7I'T3: Execute a register-reference instr.D7IT3: Execute an input-output instr.
Instrction Cycle
= 0 (direct)
StartSC ← 0
AR ← PC T0
IR ← M[AR], PC ← PC + 1T1
AR ← IR(0-11), I ← IR(15)Decode Opcode in IR(12-14),
T2
D7= 0 (Memory-reference)(Register or I/O) = 1
II
Executeregister-reference
instructionSC ← 0
Executeinput-outputinstruction
SC ← 0
M[AR]←AR Nothing
= 0 (register)(I/O) = 1 (indirect) = 1
T3 T3 T3 T3
Executememory-reference
instructionSC ← 0
T4
24������������������ ������������ �� � � � ��
REGISTER REF EREN CE IN STRU CTION S
r = D7 I’ T3 => Register Reference InstructionBi = IR(i) , i=0,1,2,...,11
- D7 = 1, I = 0- IR���� b0 ~ b11���� � �� �� �� � � � �� � �� � �� � � � � � �� � � �� � � �� � � � .- T3 � � � � ! "! "! "! " � � � �� � � �� � � �� � � � # $ � �# $ � �# $ � �# $ � � ...
Instruction Cycle
� % ! "� % ! "� % ! "� % ! " & ' ( �& ' ( �& ' ( �& ' ( � � � � )� � � )� � � )� � � ) * + , #* + , #* + , #* + , # - �- �- �- �
r: SC ← 0CLA rB11: AC ← 0CLE rB10: E ← 0CMA rB9: AC ← AC’CME rB8: E ← E’CIR rB7: AC ← shr AC, AC(15) ← E, E ← AC(0)CIL rB6: AC ← shl AC, AC(0) ← E, E ← AC(15)INC rB5: AC ← AC + 1SPA rB4: if (AC(15) = 0) then (PC ← PC+1)SNA rB3: if (AC(15) = 1) then (PC ← PC+1)SZA rB2: if (AC = 0) then (PC ← PC+1)SZE rB1: if (E = 0) then (PC ← PC+1)HLT rB0: S ← 0 (S is a start-stop flip-flop)
25������������������ ������������ �� � � � ��
M EM ORY REF EREN CE IN STRU CTION S
AND to ACD0T4: DR ← M[AR] Read operandD0T5: AC ← AC ∧ DR, SC ← 0 AND with AC
ADD to ACD1T4: DR ← M[AR] Read operandD1T5: AC ← AC + DR, E ← Cout, SC ← 0 Add to AC and store carry in E
- Instruction����./012./012./012./012 AR )))) 3 4 53 4 53 4 53 4 5 6 7 ��6 7 ��6 7 ��6 7 �� .8 9 � �8 9 � �8 9 � �8 9 � � T2 : ;: ;: ;: ; I = 0, 8 9 � �8 9 � �8 9 � �8 9 � � T3 : ;: ;: ;: ; I = 1
- CPU < 6 =< 6 =< 6 =< 6 = > ! "> ! "> ! "> ! " ? @ A? @ A? @ A? @ A < 6 = B< 6 = B< 6 = B< 6 = B C D 4 EC D 4 EC D 4 EC D 4 E F A ��F A ��F A ��F A �� ..- MR Instruction ���� G H BG H BG H BG H B T���� I 6I 6I 6I 6 J $ ��J $ ��J $ ��J $ �� .4
MR Instructions
Symbol OperationDecoder Symbolic Description
AND D0 AC ← AC ∧ M[AR]ADD D1 AC ← AC + M[AR], E ← CoutLDA D2 AC ← M[AR]STA D3 M[AR] ← ACBUN D4 PC ← ARBSA D5 M[AR] ← PC, PC ← AR + 1ISZ D6 M[AR] ← M[AR] + 1, if M[AR] + 1 = 0 then PC ← PC+1
26������������������ ������������ �� � � � ��
MEMORY REFERENCE INSTRUCTIONS
Memory, PC after execution
21
0 BSA 135Next instruction
Subroutine
20PC = 21
AR = 135136
1 BUN 135
Memory, PC, AR at time T4
0 BSA 135Next instruction
Subroutine
2021
135PC = 136
1 BUN 135Memory Memory
LDA: Load to ACD2T4: DR ← M[AR]D2T5: AC ← DR, SC ← 0
STA: Store ACD3T4: M[AR] ← AC, SC ← 0
BUN: Branch UnconditionallyD4T4: PC ← AR, SC ← 0
BSA: Branch and Save Return AddressM[AR] ← PC, PC ← AR + 1
27������������������ ������������ �� � � � ��
MEMORY REFERENCE INSTRUCTIONSMR Instructions
BSA: D5T4: M[AR] ← PC, AR ← AR + 1D5T5: PC ← AR, SC ← 0
ISZ: Increment and Skip-if-ZeroD6T4: DR ← M[AR]D6T5: DR ← DR + 1D6T4: M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0
28������������������ ������������ �� � � � ��
FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONSMR Instructions
Memory-reference instruction
DR ← M[AR] DR ← M[AR] DR ← M[AR] M[AR] ← ACSC ← 0
AND ADD LDA STA
AC ← AC DRSC ← 0
AC ← AC + DRE ← CoutSC ← 0
AC ← DRSC ← 0
D T0 4 D T1 4 D T2 4 D T3 4
D T0 5 D T1 5 D T2 5
PC ← ARSC ← 0
M[AR] ← PCAR ← AR + 1
DR ← M[AR]
BUN BSA ISZ
D T4 4 D T5 4 D T6 4
DR ← DR + 1D T5 5 D T6 5
PC ← ARSC ← 0
M[AR] ← DRIf (DR = 0)then (PC ← PC + 1)SC ← 0
D T6 6
∧
29������������������ ������������ �� � � � ��
INP UT-OUTP UT A ND INTERRUP T
• Input-Output Configuration
INPR Input register - 8 bitsOUTR Output register - 8 bitsFGI Input flag - 1 bitFGO Output flag - 1 bitIEN Interrupt enable - 1 bit
- D KD KD KD K L M 2L M 2L M 2L M 2 � � � � N O )N O )N O )N O ) 0P0P0P0P Q 2�Q 2�Q 2�Q 2� . - The serial info. INPRR S TR S TR S TR S T U O V TU O V TU O V TU O V T W � �W � �W � �W � � G X Y �G X Y �G X Y �G X Y � N ON ON ON O .- The serial info. OUTRR S TR S TR S TR S T X Z � TX Z � TX Z � TX Z � T W �W �W �W � [ L �[ L �[ L �[ L � N ON ON ON O .- INPR ���� OUTR 2222 \ ] T\ ] T\ ] T\ ] T ����AC N O �N O �N O �N O � D K � �D K � �D K � �D K � � ^ ]^ ]^ ]^ ] ( � � � � ) � )� )� )� ) 3 � � �3 � � �3 � � �3 � � � .- Flags2222 " T � _" T � _" T � _" T � _ I/O L M �L M �L M �L M � ` a �` a �` a �` a � b �b �b �b � � )� )� )� ) c d Tc d Tc d Tc d T � �� �� �� � .
A Terminal with a keyboard and a Printer
I/O and Interrupt
Input-outputterminal
Serialcommunication
interface Computerregisters and
flip-flops
Printer
Keyboard
Receiverinterface
Transmitterinterface
FGOOUTR
AC
INPR FGI
Serial Communications PathParallel Communications Path
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P ROG RA M CONTROL L ED D A TA TRA NSFERI/O and Interrupt
loop: If FGI = 1 goto loop
INPR ← new data, FGI ← 1
loop: If FGO = 1 goto loop
consume OUTR, FGO ← 1
-- CPU -- -- I/O Device --/* Input */ /* Initially FGI = 0 */
loop: If FGI = 0 goto loopAC ← INPR, FGI ← 0
/* Output */ /* Initially FGO = 1 */loop: If FGO = 0 goto loop
OUTR ← AC, FGO ← 0
Start Input
FGI ← 0
FGI=0
AC ← INPR
MoreCharacter
END
Start Output
FGO ← 0
FGO=0
MoreCharacter
END
OUTR ← AC
AC ← Datayes
no
yes
no
FGI=0 FGO=1
yes
yesno
no
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INP UT-OUTP UT INSTRUCTIONS
D7IT3 = pIR(i) = Bi, i = 6, …, 11
INP pB11: AC(0-7) ← INPR, FGI ← 0 Input char. to ACOUT pB10: OUTR ← AC(0-7), FGO ← 0 Output char. from ACSKI pB9: if(FGI = 1) then (PC ← PC + 1) Skip on input flagSKO pB8: if(FGO = 1) then (PC ← PC + 1) Skip on output flagION pB7: IEN ← 1 Interrupt enable onIOF pB6: IEN ← 0 Interrupt enable off
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P ROG RA M-CONTROL L ED INP UT/ OUTP UT
• Program-controlled I/O- Continuous CPU involvement
I/O takes valuable CPU time- CPU slowed down to I/O speed- Simple- Least hardware
I/O and Interrupt
Input
LOOP, SKI DEVBUN LOOPINP DEV
Output
LOOP, LD DATALOP, SKO DEV
BUN LOPOUT DEV
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INTERRUP T INITIA TED INP UT/ OUTP UT
- 3 � 63 � 63 � 63 � 6 e fe fe fe f - � ; g- � ; g- � ; g- � ; g , h 6 �h 6 �h 6 �h 6 � � 6 � 6 � 6 � 6 i 7 ��i 7 ��i 7 ��i 7 �� . --> interrupt.
- I/O+ � j 6 ( �+ � j 6 ( �+ � j 6 ( �+ � j 6 ( � k l mk l mk l mk l m CPU n "n "n "n " I/O device)))) @ l � o � �@ l � o � �@ l � o � �@ l � o � � .
- + � j 6 ( )+ � j 6 ( )+ � j 6 ( )+ � j 6 ( ) p � ;p � ;p � ;p � ; I/O L M 2L M 2L M 2L M 2 h 6 �h 6 �h 6 �h 6 � � � �� � �� � �� � � q �q �q �q � r s Tr s Tr s Tr s T CPU ! E! E! E! Einterrupt d td td td t 6 - � u6 - � u6 - � u6 - � u � �� �� �� � .
- + � v Y+ � v Y+ � v Y+ � v Y � )� )� )� ) w x Gw x Gw x Gw x G CPU2222 4 y : �4 y : �4 y : �4 y : � z { Pz { Pz { Pz { P , service routine S TS TS TS T h 6 �h 6 �h 6 �h 6 �
� � �� � �� � �� � � q |q |q |q | } � 4 P} � 4 P} � 4 P} � 4 P , # $ 4 y : �# $ 4 y : �# $ 4 y : �# $ 4 y : � A ~ � �A ~ � �A ~ � �A ~ � � .
* IEN (Interrupt-enable flip-flop)
- can be set and cleared by instructions- when cleared, the computer cannot be interrupted
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FL OW CH A RT FOR INTERRUP T CYCL E
- The interrupt cycle is a HW implementation of a branchand save return address operation.
- At the beginning of the next instruction cycle, the instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine
- The instruction that returns the control to the original program is "indirect BUN 0"
I/O and Interrupt
R = Interrupt f/f
Store return address
R =1=0
in location 0M[0] ← PC
Branch to location 1PC ← 1
IEN ← 0R ← 0
Interrupt cycleInstruction cycle
Fetch and decodeinstructions
IEN
FGI
FGO
Executeinstructions
R ← 1
=1=1
=1
=0
=0
=0
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REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE
Register Transfer Statements for Interrupt Cycle- R F/F ← 1 if IEN (FGI + FGO)T0’T1’T2’
⇔ T0’T1’T2’ (IEN)(FGI + FGO): R ← 1
- The fetch and decode phases of the instruction cyclemust be modified:Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :RT0: AR ← 0, TR ← PCRT1: M[AR] ← TR, PC ← 0RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
After interrupt cycle
0 BUN 112001
PC = 256255
1 BUN 0
Before interrupt
MainProgram
1120I/O
Program
0 BUN 11200
PC = 1
256255
1 BUN 0
Memory
MainProgram
1120I/O
Program
256
I/O and Interrupt
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FURTH ER Q UESTIONS ON INTERRUP T
Questions on Interrupt
How can the CPU recognize the device requesting an interrupt ?
Since different devices are likely to require different interrupt service routines, how can the CPU obtain the starting address of the appropriate routine in each case ?
Should any device be allowed to interrupt the CPU while another interrupt is being serviced ?
How can the situation be handled when two or more interrupt requests occur simultaneously ?
I/O and Interrupt
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COMP L ETE COMP UTER D ESCRIP TIONFl o w c h a r t o f Op e r a t i o n sDescription
=1 (I/O) =0 (Register) =1(Indir) =0(Dir)
startSC ← 0, IEN ← 0, R ← 0
R
AR ← PCR’T0
IR ←M[AR], PC ← PC + 1R’T1
AR ← IR(0~11), I ← IR(15)D0...D7 ← Decode IR(12 ~ 14)
R’T2
AR ← 0, TR ← PCRT0
M[AR] ← TR, PC ← 0RT1
PC ← PC + 1, IEN ← 0R ← 0, SC ← 0
RT2
D7
I I
ExecuteI/O
Instruction
ExecuteRR
Instruction
AR <- M[AR] IdleD7IT3 D7I’T3 D7’IT3 D7’I’T3
Execute MRInstruction
=0(Instruction =1(Interrupt Cycle) Cycle)
=1(Register or I/O) =0(Memory Ref)
D7’T4
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COMP L ETE COMP UTER D ESCRIP TION M i c r o o p e r a t i o n sDescription
Fetch
Decode
IndirectInterrupt
Memory-ReferenceAND
ADD
LDA
STABUNBSA
ISZ
R’T0: R’T1:R’T2:
D7’IT3:
RT0:RT1:RT2:
D0T4:D0T5:D1T4:D1T5:D2T4:D2T5:D3T4:D4T4:D5T4:D5T5:D6T4:D6T5:D6T6:
AR ← PCIR ← M[AR], PC ← PC + 1D0, ..., D7 ← Decode IR(12 ~ 14), AR ← IR(0 ~ 11), I ← IR(15)AR ← M[AR]
R ← 1AR ← 0, TR ← PCM[AR] ← TR, PC ← 0PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
DR ← M[AR]AC ← AC ∧ DR, SC ← 0DR ← M[AR]AC ← AC + DR, E ← Cout, SC ← 0DR ← M[AR]AC ← DR, SC ← 0M[AR] ← AC, SC ← 0PC ← AR, SC ← 0M[AR] ← PC, AR ← AR + 1PC ← AR, SC ← 0DR ← M[AR]DR ← DR + 1M[AR] ← DR, if(DR=0) then (PC ← PC + 1), SC ← 0
T0’T1’T2’(IEN)(FGI + FGO):
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Register-Reference
CLACLECMACMECIRCILINCSPASNASZASZEHLT
Input-Output
INPOUTSKISKOIONIOF
D7I’T3 = rIR(i) = Bi
r:rB11:rB10:rB9:rB8:rB7:rB6:rB5:rB4:rB3:rB2:rB1:rB0:
D7IT3 = p IR(i) = Bi
p:pB11:pB10:pB9:pB8:pB7:pB6:
(Common to all register-reference instr)(i = 0,1,2, ..., 11)SC ← 0AC ← 0E ← 0AC ← AC’E ← E’AC ← shr AC, AC(15) ← E, E ← AC(0)AC ← shl AC, AC(0) ← E, E ← AC(15)AC ← AC + 1If(AC(15) =0) then (PC ← PC + 1)If(AC(15) =1) then (PC ← PC + 1)If(AC = 0) then (PC ← PC + 1)If(E=0) then (PC ← PC + 1)S ← 0
(Common to all input-output instructions)(i = 6,7,8,9,10,11)SC ← 0AC(0-7) ← INPR, FGI ← 0OUTR ← AC(0-7), FGO ← 0If(FGI=1) then (PC ← PC + 1)If(FGO=1) then (PC ← PC + 1)IEN ← 1IEN ← 0
DescriptionCOMP L ETE COMP UTER D ESCRIP TION M i c r o o p e r a t i o n s
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D ESIG N OF B A SIC COMP UTER( B C)
Hardware Components of BC A memory unit: 4096 x 16.Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SCFlip-Flops(Status):
I, S, E, R, IEN, FGI, and FGODecoders: a 3x8 Opcode decoder
a 4x16 timing decoderCommon bus: 16 bitsControl logic gates:Adder and Logic circuit: Connected to AC
Control Logic Gates
- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit
Design of Basic Computer
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CONTROL OF REG ISTERS A ND MEMORY
Scan all of the register transfer statements that change the content of AR:
Address Register; AR
LD(AR) = R'T0 + R'T2 + D'7IT3CLR(AR) = RT0INR(AR) = D5T4
R’T0: AR ← PC LD(AR)R’T2: AR ← IR(0-11) LD(AR)D’7IT3: AR ← M[AR] LD(AR)RT0: AR ← 0 CLR(AR)D5T4: AR ← AR + 1 INR(AR)
Design of Basic Computer
AR
LDINR
CLR
Clock
To bus12From bus 12
D'I
TT
RTDT
7
32
0
4
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CONTROL OF FL A G S
pB7: IEN ← 1 (I/O Instruction)pB6: IEN ← 0 (I/O Instruction)RT2: IEN ← 0 (Interrupt)
p = D7IT3 (Input/Output Instruction)
IEN: Interrupt Enable Flag
D
I
T3
7
J
K
Q IENp
B7
B6
T2R
Design of Basic Computer
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CONTROL OF COMMON B US
For AR D4T4: PC ← ARD5T5: PC ← AR
x1 = D4T4 + D5T5
Design of Basic Computer
x1x2x3x4x5x6x7
Encoder
S 2
S 1
S 0
Multiplexer
bus select
inputs
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0selectedregister
0 0 0 0 0 0 0 0 0 0 none1 0 0 0 0 0 0 0 0 1 AR0 1 0 0 0 0 0 0 1 0 PC0 0 1 0 0 0 0 0 1 1 DR0 0 0 1 0 0 0 1 0 0 AC0 0 0 0 1 0 0 1 0 1 IR0 0 0 0 0 1 0 1 1 0 TR0 0 0 0 0 0 1 1 1 1 Memory
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D ESIG N OF A CCUMUL A TOR L OG IC
Circuits associated with AC
All the statements that change the content of AC
Design of AC Logic
16
16
8
Adder andlogic circuit
16 ACFrom DR
From INPR
Controlgates
LD INR CLR
16
To bus
Clock
D0T5: AC ← AC ∧ DR AND with DRD1T5: AC ← AC + DR Add with DRD2T5: AC ← DR Transfer from DRpB11: AC(0-7) ← INPR Transfer from INPRrB9: AC ← AC’ ComplementrB7 : AC ← shr AC, AC(15) ← E Shift rightrB6 : AC ← shl AC, AC(0) ← E Shift leftrB11 : AC ← 0 ClearrB5 : AC ← AC + 1 Increment
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CONTROL OF A C REG ISTER
Gate structures for controlling the LD, INR, and CLR of AC
AC
LDINR
CLR
Clock
To bus16From Adderand Logic
16
AND
ADD
DR
INPR
COM
SHR
SHL
INC
CLR
D0
D1
D2
B11
B9
B7
B6
B5
B11
r
p
T5
T5
Design of AC Logic
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A L U ( A D D ER A ND L OG IC CIRCUIT)
One stage of Adder and Logic circuit
Design of AC Logic
AND
ADD
DR
INPR
COM
SHR
SHL
J
K
QAC(i)
LD
FA
C
C
FromINPRbit(i)
DR(i) AC(i)
AC(i+1)
AC(i-1)
i
i
i+1
I