ARM introduction with reference to arm 11

7/28/2019 ARM introduction with reference to arm 11

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By : SUMEET SAURAV

ARM :ANINTRODUCTION


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ar ous arm arc ec ure an e r family


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Features of ARM11

Powerful ARMv6 instruction set architecture.ARM Thumb instruction set reduces memory

bandwidth and size requirements by up to 35%.ARM Jazelle technology for efficient embedded Javaexecution.

ARM DSP extensions.SIMD (Single Instruction Multiple Data) media processing extensions deliver up to 2x performance for video processing


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ARM TrustZone technology for on-chip security foundation(ARM1176JZ-S and ARM1176JZF-S processors)

Thumb-2 technology (ARM1156(F)-S only) for enhanced performance, energy efficiency and code densityLow power consumption.0.21 mW/MHz (65G) including cache controllers

Energy saving power-down modes address static leakagecurrents in advanced processesHigh performance integer processor.8-stage integer pipeline delivers high clock frequency (9 stagesfor ARM1156T2(F)-S)Separate load-store and arithmetic pipelinesBranch Prediction and Return Stack

High performance memory system design


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Supports 4-64k cache sizes.

Optional tightly coupled memories with DMA for multi-mediaapplications.

High-performance 64-bit memory system speeds data access

for media processing and networking applications.

Vectored interrupt interface and low-interrupt-latency modespeeds interrupt response and real-time performance.

Optional Vector Floating Point coprocessor for automotive/industrial controls and 3D graphics acceleration


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ARM ARCHITECTURE:INTRODUCTION

The ARM is a Reduced Instruction Set Computer(RISC).

o a large uniform register file.

o a load/store architecture, where data-processingoperations only operate on register contents, not directlyon memory contents

o simple addressing modes, with all load/store addresses being determined from register contents and instructionfields only.

o uniform and fixed-length instruction fields, to simplifyinstruction decode .


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o Control over both the Arithmetic Logic Unit(ALU) and

shifter in most data-processing instructions to maximize theuse of an ALU and a shifter

Auto-increment and auto-decrement addressing modes tooptimize program loops.

Load and Store Multiple instructions to maximize datathroughput.

Conditional execution of almost all instructions tomaximize execution throughput.

These enhancements to a basic RISC architecture allowARM processors to achieve a good balance of high

performance, small code size, low power consumption, and

small silicon area.


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ARM REGISTERS

ARM has 31 general-purpose 32-bit registers. At anyone time, 16 of these registers are visible.

Three of the 16 visible registers have special roles:

Stack pointer : Register R13 as a Stack Pointer(SP).

Link register :Register 14 is the Link Register(LR).

Program counter: Register 15 is the Program

Counter(PC).


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General-purpose registers The general-purpose registers R0 to R15 can be split into

three groups. These groups differ in the way they are banked and in their special-purpose uses:

The unbanked registers, R0 to R7

The banked registers, R8 to R14

Register 15, the PC


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The unbanked registers, R0 to R7

Registers R0 to R7 are unbanked registers. Thismeans that each of them refers to the same 32-bit

physical register in all processor modes.

They are completely general-purpose registers, withno special uses implied by the architecture, and can

be used wherever an instruction allows a general- purpose register to be specified.


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The banked registers, R8 to R14

Registers R8 to R14 are banked registers. The physicalregister referred to by each of them depends on the current

processor mode.

Where a particular physical register is intended, withoutdepending on the current processor mode, a more specificname is used.

Almost all instructions allow the banked registers to be usedwherever a general-purpose register is allowed.


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Register 15 and the program counterRegister (R15) is often used in place of the other general-

purpose registers to produce various special-case effects.These are instruction-specific and so are described in theindividual instruction descriptions.

There are also many instruction-specific restrictions on theuse of R15. these are also noted in the individualinstruction descriptions. Usually, the instruction isUNPREDICTABLE if R15 is used in a manner that breaks

these restrictions.If an instruction description neither describes a special-caseeffect when R15 is used nor places restrictions on its use,R15 is used to read or write the Program Counter(PC).


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Program status register

The Current Program Status Register(CPSR) is accessible inall processor modes.It contains condition code flags, interrupt disable bits, thecurrent processor mode, and other status and control

information. Each exception mode also has a Saved ProgramStatus Register(SPSR), that is used to preserve the value of the CPSR when the associated exception occurs.


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STATUS REGISTERSAll processor state other than the general-purpose register contents isheld in status registers. The current operating processor status is inthe Current Program Status Register(CPSR). The CPSR holds:

four condition code flags (Negative, Zero, Carry and Overflow).

one sticky (Q) flag (ARMv5 and above only). This encodes whether saturation has occurred in saturated arithmetic instructions, or signedoverflow in some specific multiply accumulate instructions.

four GE (Greater than or Equal) flags (ARMv6 and above only).These encode the following conditions separately for each operationin parallel instructions:

whether the results of signed operations were non-negative whether unsigned operations produced a carry or a borrow.


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Each exception mode also hasa Saved Program StatusRegister(SPSR) which holdsthe CPSR of the task immediately before theexception occurred. TheCPSR and the SPSRs areaccessed with specialinstructions.

Four GE (Greater than or Equal) flags (ARMv6 and above only).These encode the following conditions separately for eachoperation in parallel instructions:

whether the results of signed operations were non-negative whether unsigned operations produced a carry or a borrow .


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Exceptions and Exception Process

ARM supports seven types of exception, and a privileged processing mode for each type. The seven types of exception are:reset

attempted execution of an Undefined instructionsoftware interrupt (SWI) instructions, can be used tomake a call to an operating system

Prefetch Abort, an instruction fetch memory abortData Abort, a data access memory abortIRQ, normal interrupt

FIQ, fast interrupt.


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The condition field

Most ARM instructions can be conditionallyexecuted if the N, Z, C and V flags in the CPSRsatisfy a condition specified in the instruction.If the flags do not satisfy this condition, the

instruction acts as a NOP: that is, executionadvances to the next instruction as normal.Prior to ARMv5, all ARM instructions could beconditionally executed. A few instructions havebeenintroduced subsequently which can onlybeexecuted unconditionall


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Unconditional instruction extension space


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ARM INSTRUCTION SETS

The ARM instruction set can be divided into six broad classesof instruction:Branch instructions

Data-processing instructionsStatus register transfer instructionsLoad and store instructionsCoprocessor instructions.

Exception-generating instructions.

Almost all ARM instructions contain a 4-bit condition field.One value of this field specifies that the instruction isexecuted unconditionally.

Fourteen other values specify conditional execution of the


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Branch instructions

The Branch with Link (BL) instruction preserves theaddress of the instruction after the branch (the returnaddress) in the LR (R14).The Branch and Exchange (BX) instruction copies the

contents of a general-purpose register Rm to the PC (like aMOV PC,Rm instruction), with the additionalfunctionality that if bit[0] of the transferred value is1, the

processor shifts to Thumb state.

In ARMv5 and above, there are also two types of Branchwith Link and Exchange (BLX) instruction:


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One type takes a register operand Rm, like a BXinstruction. This instruction behaves like a BX instruction,and additionally writes the address of the next instructioninto the LR. This provides a more efficient interworkingsubroutine call than a sequence of MOV LR,PC followed

by BX Rm.

The other type behaves like a BL instruction, branching backwards or forwards by up to 32MB and writing areturn link to the LR, but shifts to Thumb state rather thanstaying in ARM state as BL does.


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Types of Branch Instructions(B,BL)

B(Branch) and BL(Branch and Link) cause a branch to atarget address, and provide both conditional and unconditionalchanges to program flow.BL also stores a return address in the link register, R14 (alsoknown as LR).

Syntax B{L}{} 1. Sign-extending the 24-bit signed (two's complement)

immediate to 30 bits.

2.Shifting the result left two bits to form a 32-bit value.3. Adding this to the contents of the PC, which contains the

address of the branch instruction plus 8 bytes.


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Types of Branch Instructions(BLX1) BLX(1) (Branch with Link and Exchange) calls a Thumb subroutine from theARM instruction set at an address specified in the instruction.

o This form of BLX is unconditional (always causing a change in program flow)and preserves the address of the instruction following the branch in the link register (R14). Execution of Thumb instructions begins at the target address.

o Syntax BLX

1.Sign-extending the 24-bit signed (two's complement) immediate to 30 bits.2. Shifting the result left two bits to form a 32-bit value3.Setting bit[1] of the result of step 2 to the H bit4.Adding the result of step 3 to the contents of the PC, which contains the address

of the branch instruction plus 8.

o Condition :Unlike most other ARM instructions, this instruction cannot beexecuted conditionally.Bit[24] :This bit is used as bit[1] of the target address .


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Types of Branch Instructions(BLX2) BLX(2) calls an ARM or Thumb subroutine from the ARM

instruction set, at an address specified in a register.It sets the CPSR T bit to bit[0] of Rm. This selects theinstruction set to be used in the subroutine.The branch target address is the value of register Rm, with its

bit[0] forced to zero.It sets R14 to a return address. To return from the subroutine,use a BX R14instruction, or store R14 on thestack and reload the stored value into the PC.


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Types of Branch Instructions(BX) BX(Branch and Exchange) branches to an address,with an optional switch to Thumb state.Syntax BX{} Here Holds the value of the branch targetaddress. Bit[0] of Rm is 0 to select a target ARMinstruction, or 1 to select a target Thumb instruction.


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Types of Branch Instructions(BXJ) BXJ(Branch and change to Jazellestate) entersJazelle state if Jazelle is available and enabled.Otherwise BXJ behaves exactly as BXSyntax BXJ{}


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Data-processing instructionsThe data-processing instructions perform calculations on

the general-purpose registers. There are five types of data-processing instructions:Arithmetic/logic instructions

Comparison instructions

Single Instruction Multiple Data (SIMD) instructions

Multiply instructions.

Miscellaneous Data Processing instructions.


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Arithmetic/logic instructions

These perform an arithmetic or logical operationon up to two source operands, and write the resultto a destination register.They can also optionally update the condition

code flags, based on the result.Of the two source operands:

one is always a register the other has two basicforms:

an immediate value a register value, optionally shifted .


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CONTINUED..o If the operand is a shifted register, the shift amount can

be either an immediate value or the value of another register.

o Five types of shift can be specified.o Every arithmetic/logic instruction can therefore perform

an arithmetic/logic operation and a shift operation. As aresult, ARM does not have dedicated shift instructions.

o The Program Counter(PC) is a general-purpose register,and therefore arithmetic/logic instructions can write their results directly to the PC. This allows easyimplementation of a variety of jump instructions.


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Comparison instruction

The comparison instructions use the same instructionformat as the arithmetic/logic instructions. These

perform an arithmetic or logical operation on two source

operands, but do not write the result to a register.They always update the condition flags, based on theresult.The source operands of comparison instructions take thesame forms as those of arithmetic/logicinstructions, including the ability to incorporate a shiftoperation.


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Single Instruction Multiple Data (SIMD)instructions

The add and subtract instructions treat each operand astwo parallel 16-bit numbers, or fourparallel 8-bitnumbers. They can be treated as signed or unsigned.Theoperations can optionally be saturating, wraparound, or the results can be halved to avoid overflow.These instructions are available in ARMv6.


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Multiply instructions

There are several classes of multiply instructions,introduced at different times into the architecture.SeeMultiply instructionson page A3-10 for details.Miscellaneous Data Processing instructionsThese include Count Leading Zeros (CLZ) andUnsigned Sum of AbsoluteDifferences withoptionalAccumulate (USAD8and USADA8)


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Instruction Encoding

I bit Distinguishes between the immediate andregister forms of .S bit Signifies that the instruction updates thecondition codes.Rn Specifies the first source operand register.Rd Specifies the destination register.shifter_operand Specifies the second sourceoperand.


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Data processing Instructions(ADC)ADC(Add with Carry) adds two values and the Carry flag. The first value comes from aregister. The second value can be either an immediate value or a value from a register,

and can be shifted before the addition.ADCcan optionally update the condition code flags, based on the result.

Syntax ADC{}{S} , ,

S Causes the S bit (bit[20]) in the instruction to be set to 1 and specifies that the

instruction updates the CPSR. If Sis omitted, the S bit is set to 0 and the CPSR is notchanged by the instruction. Two types of CPSR update can occur when Sis specified:

If is not R15, the N and Z flags are set according to the result of the addition, and

the C and V flags are set according to whether the addition generated a carry (unsigned

overflow) and a signed overflow, respectively. The rest of the CPSR is unchanged.If is R15, the SPSR of the current mode is copied to the CPSR. This form of the

instruction is UNPREDICTABLE if executed in User mode or System mode, because

these modes do not have an SPSR.


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Data processing Instructions(ADD)

ADDadds two values. The first value comes from aregister. The second value can be either an immediatevalue or a value from a register, and can be shifted

before the addition.ADDcan optionally update the condition code flags,

based on the result.Syntax ADD{}{S} , ,


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Data processing Instructions(AND)

AND performs a bitwise AND of two values. The firstvalue comes from a register. The second value can beeither an immediate value or a value from a register,and can be shifted before the AND operation.AND can optionally update the condition code flags,

based on the result.Syntax AND{}{S} , ,


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Data processing Instructions (BIC) BIC(Bit Clear) performs a bitwise AND of one value with thecomplement of a second value.The first value comes from a register. The second value can

be either an immediate value or a value from a register, and

can be shifted before the BIC operation.BIC can optionally update the condition code flags, based onthe result.Syntax BIC{}{S} , ,


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Data processing Instructions (CMN) CMN(Compare Negative) compares one value with the twoscomplement of a second value.The first value comes from a register. The second value can

be either an immediate value or a value from a register, andcan be shifted before the comparison.CMN updates the condition flags, based on the result of adding the two values.Syntax CMN{} ,


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Data processing Instructions (CMP) CMP(Compare) compares two values. The first value comesfrom a register.The second value can be either an immediate value or a valuefrom a register, and can be shifted before the comparison.CMP updates the condition flags, based on the result of subtracting the second value from the first.Syntax CMP{} ,


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Data processing Instructions (EOR) EOR(Exclusive OR) performs a bitwise Exclusive-OR of twovalues. The first value comes from a register.The second value can be either an immediate value or a valuefrom a register, and can be shifted before theexclusive OR operation.EORcan optionally update the condition code flags, based onthe result.

Syntax EOR{}{S} , ,


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PARALLEL ADDITION AND SUBTRACTIONINSTRUCTIONS

In addition to the normal data-processing and multiplyinstructions, ARMv6 introduces a set of parallel addition andsubtraction instructions.There are six basic instructions.

ADD16 :Adds the top half words of two registers to formthe top half word of the result.Adds the bottom half words of the same two registers toform the bottom half word of the result.

ADDSUBX Does the following:1. Exchanges half words of the second operand register.2. Adds top half words and subtracts bottom half words.


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SUBADDX Does the following:

1. Exchanges half words of the second operand register.

2. Subtracts top half words and adds bottom half words.SUB16 : Subtracts the top half word of the first operandregister from the top half word of the second operandregister to form the top half word of the result.Subtracts the bottom half word of the second operandregisters from the bottom half word of the first operandregister to form the bottom half word of the result.

ADD8 : Adds each byte of the second operand register tothe corresponding byte of the first operand ,register to formthe corresponding byte of the result.SUB8 :Subtracts each byte of the second operand register from the corresponding byte of the first operand register toform the corresponding byte of the result.


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EXTENDED INSTRUCTIONSARMv6 and above provide several instructions for unpacking data

by sign or zero extending bytes to halfwords or words, andhalfwords to words.There are six basic instructions:XTAB16 Extend bits[23:16] and bits[7:0] of one register to 16

bits, and add corresponding halfwords to the values in another register.XTAB Extend bits[7:0] of one register to 32 bits, and add to thevalue in another register.XTAH Extend bits[15:0] of one register to 32 bits, and add to the

value in another register.XTB16 Extend bits[23:16] and bits[7:0] to 16 bits each.XTB Extend bits[7:0] to 32 bits.XTH Extend bits[15:0] to 32 bits.


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OTHER MISCELLANEOUS INSTRUCTIONSPKHBT (Pack Halfword Bottom Top) combines the bottom,

least significant, halfword of its first operand with the top(most significant) halfwordof its shifted second operand.The shift is a left shift, by any amount from 0 to 31.

PKHTB (Pack Halfword Top Bottom) combines the top,most significant, halfword of its first operand with the bottom(least significant) halfword of its shifted second operand.

The shift is an arithmetic right shift, by any amount from 1 to32.


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REV (Byte-Reverse Word) reverses the byte order in a32-bit register.REV16 (Byte-Reverse Packed Halfword) reverses the

byte order in each 16-bit halfword of a 32-bit register.

REVSH (Byte-Reverse Signed Halfword) reverses the

byte order in the lower 16-bit halfword of a 32-bitregister, and sign extends the result to 32-bits.

SEL (Select) selects each byte of its result from either itsfirst operand or its second operand, according to thevalues of the GE flags. The GE flags record the results of

parallel additions or subtractions.


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SSAT (Signed Saturate) saturates a signed value to asigned range..SSAT16 Saturates two 16-bit signed values to a signedrange.USAT (Unsigned Saturate) saturates a signed value toan unsigned range..

USAT16 Saturates two signed 16-bit values to anunsigned range.


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LOAD AND STORE INSTRUCTIONS

The ARM architecture supports two broad types of instructionwhich load or store the value of a single register, or a pair of registers, from or to memory:

The first type can load or store a 32-bit word or an 8-bitunsigned byte.

The second type can load or store a 16-bit unsigned halfword,and can load and sign extend a 16-bit halfword or an 8-bit

byte . In ARMv5TE and above, it can also load or store a pair of 32-bit words.


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Addressing modes

In both types of instruction, the addressing mode is formed

from two parts:the base register the offset.

The base register can be any one of the general-purposeregisters (including the PC, which allows PC-relativeaddressing for position-independent code).

The offset takes one of three formats:Immediate :The offset is an unsigned number that can beadded to or subtracted from the base register


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Register :The offset is a general-purpose register (notthe PC), that can be added to or subtracted from the baseregister.Scaled register : The offset is a general-purpose register (not the PC) shifted by an immediate value, then addedto or subtracted from the base register.

The same shift operations used for data-processinginstructions can be used(Logical Shift Left, Logical ShiftRight, Arithmetic Shift Right and Rotate Right), butLogical Shift Left is the most useful as it allows an arrayindexed to be scaled by the size of each array element .

Load and store word or unsigned byte


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Load and store word or unsigned byteinstructions

Load instructions load a single value from memory andwrite it to a general-purpose register.Store instructions read a value from a general-purposeregister and store it to memory.

These instructions have a single instruction format:LDR|STR{}{B}{T} Rd, I, P, U, W Are bits that distinguish between differenttypes of .

L bit Distinguishes between a Load (L==1)and a Storeinstruction (L==0).B bit Distinguishes between an unsigned byte(B==1)and a word (B==0) access.


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LDR R1, [R0] ; Load R1 from the address in R0LDR R8, [R3, #4] ; Load R8 from the address in R3 + 4

LDR R12, [R13, #-4] ; Load R12 from R13 - 4STR R2, [R1, #0x100] ; Store R2 to the address in R1 +0x100

Rn Specifies the base register used by.Rd Specifies the register whose contents are to be loadedor stored.

E t di g th i t ti t


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Extending the instruction setSuccessive versions of the ARM architecture have extendedthe instruction set in a number of areas.

Some common areas include:Media instruction space

Multiply instruction extension spaceControl and DSP instruction extension spaceLoad/store instruction extension space

Architecturally Undefined Instruction spaceCoprocessor instruction extension spaceUnconditional instruction extension space


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Media instruction space

Instructions with the following opcodes are defined as

residing in the media instruction space:opcode[27:25] = 0b011opcode[4] = 1


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Multiply instruction extension spaceInstructions with the following opcodes are the multiply

instruction extension space:opcode[27:24] == 0b0000opcode[7:4] == 0b1001opcode[31:28] != 0b1111 /* Only required for version 5 andabove */


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Control and DSP instruction extension space

Instructions with the following opcodes are the controlinstruction space.opcode[27:26] == 0b00opcode[24:23] == 0b10opcode[20] == 0opcode[31:28] != 0b1111 /* Only required for version 5and above */

and not:opcode[25] == 0opcode[7] == 1opcode[4] == 1


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Load/store instruction extension spaceInstructions with the following opcodes are the load/store

instruction extension space:opcode[27:25] == 0b000opcode[7] == 1opcode[4] == 1opcode[31:28] != 0b1111 /* Only required for version 5 andabove */and not:

opcode[24] == 0opcode[6:5] == 0


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S i f i i


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Status register transfer instructions

The status register transfer instructions transfer the contentsof the CPSR or an SPSR to or from a general-purposeregister. Writing to the CPSR can:set the values of the condition code flagsset the values of the interrupt enable bitsset the processor mode and statealter the endianness of Load and Store operations.

L d d t i t ti


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Load and store instructions

The following load and store instructions are available:

Load and Store Register Load and Store Multiple registers Load and Store Register Exclusive

There are also swap and swap byte instructions, buttheir use is deprecated in ARMv6. It is recommendedthat all software migrates to using the load and storeregister exclusive instructions.

C i t ti


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Coprocessor instructions There are three types of coprocessor instructions:

Data-processing instructions :These start a coprocessor-specific internal operation.

Data transfer instructions :These transfer coprocessor datato or from memory. The address of the transfer is calculated

by the ARM processor.

Register transfer instructions :These allow a coprocessor value to be transferred to or from an ARM register, or a pair of ARM registers.

E ti g ti g i t ti


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Exception-generating instructions Two types of instruction are designed to cause specific exceptions tooccur.

Software interrupt instructionsSWI instructions cause a software interrupt exception to occur. These arenormally used to make calls to an operating system, to request an OS-defined service. The exception entry caused by a SWI instruction alsochanges to a privileged processor mode.This allows an unprivileged task to gain access to privileged functions,

but only in ways permitted by the OS.

Software breakpoint instructionsBKPT instructions cause an abort exception to occur. If suitabledebugger software is installed on the abort vector, an abort exceptiongenerated in this fashion is treated as a breakpoint.If debug hardware is present in the system, it can instead treat a BKPTinstruction directly as a breakpoint, preventing the abort exception fromoccurring.

The condition code flags


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The condition code flags The N, Z, C, and V (Negative, Zero, Carry and oVerflow) bitsare collectively known as the condition code flags, oftenreferred to as flags.The condition code flags in the CPSR can be tested by mostinstructions to determine whether the instruction is to beexecuted.The condition code flags are usually modified by:Execution of a comparison instruction (CMN, CMP, TEQor TST).

Execution of some other arithmetic, logical or moveinstruction, where the destination register of the instruction isnot R15.

ADDRESSING MODE1-DATA PROCESSING


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OPERENDS

Add i M d 2 L d d S W d


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Addressing Mode 2 - Load and Store Word orUnsigned Byte

Add i M d 3 Mi ll L d d


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Addressing Mode 3 - Miscellaneous Loads andStores


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Add i g M d 4 L d d St M lti l


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Addressing Mode 4 - Load and Store Multiple

Add i g M d 5 L d d St


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Addressing Mode 5 - Load and StoreCoprocessor

ARM introduction with reference to arm 11

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