ARM HARDWARE DEBUGGER Shane Mahon, Lyndsi Parker, and Drew Shafer.

ARM HARDWARE DEBUGGER

Shane Mahon, Lyndsi Parker, and Drew Shafer

Project Objective

To implement a hardware debugger in the FPGA to communicate to the ARM processor through JTAG.

The hardware debugger will be controlled through a serial port to a separate computer running a graphical software interface.

Overview

Hardware JTAG interface to ARM UART interface to RS232 Bridge from UART to JTAG communication

Software Serial communication ISA for JTAG

commands Implement debug commands GUI interface

Teamwork Breakdown

Shane Mahon Physical hardware to connect ARM JTAG pins to FPGA Simulation of JTAG Logic analyzer debug

Lyndsi Parker JTAG interface JTAG to UART interface Presentation preparation

Drew Shafer Software code Graphical interface UART code Simulation of Serial and JTAG

Architecture

ArchitectureARM Processor

ArchitectureARM Processor

ArchitectureARM to FPGA Connections

ARM JTAGARM JTAG

FPGA Accessory

Pins

FPGA Accessory

Pins

Logic Analyzer Probes

Logic Analyzer Probes

ArchitectureJTAG Hardware

ResetReset WaitWait

TLRTLR

DRDR

IRIR

RTIRTI

CompleteComplete

Length

Test Logic Reset (resets JTAG state machine on ARM)

Run Test Idle (advances ARM pipeline once)

Instruction Register

Data Register

ArchitectureBridge Hardware

0000 00000000 0000

1111 11111111 1111

1000 - - - -1000 - - - -

0 - - - - - - -0 - - - - - - -

Instruction

Variable Length Data

ArchitectureUART Hardware

Downloaded open source UART code http://www.opencores.org/cores/sasc/

Began debug by creating a loopback Code required some minor modifications

ImplementationRS232

ImplementationJTAG Software

Implemented Functions Read ID Code Bypass Register Halt the Processor Read/Write a Register Read/Write Multiple Registers Read/Write Memory Execute a Single Instructions Return from Halt

Code developed from JTAG-Arm9 http://jtag-arm9.sourceforge.net/

ImplementationUser Interface

Created in Visual Studio using C#

Demo: JTAG ID Code

Demo: Halting the Processor

Demo: Read/Write Registers

Demo: Execute Add Instruction

Demo: Read/Write Memory

Design Tradeoffs

JTAG data register accesses are not pipelined.

Debug instructions are not interleaved. For simplicity in executing ARM

instructions, entire scan chain was shifted although only 33 bits needed for simple instructions.

Additional Functionality

Execute code loaded from a file View disassembly of code Breakpoints/watch points Block memory accesses Standard connector for JTAG to FPGA

connections

Lessons Learned

Start simulation of Verilog early Ensure that adequate documentation is

available 8 LEDs != Logic Analyzer Never connect 16.5V directly to the ARM

Processor

Backup Slides

Logic Analyzer Trace

ADDI Instruction

Logic Analyzer Trace

Bypass

Logic Analyzer Trace

IDCODE

Logic Analyzer Trace

Read Debug Status Register

Logic Analyzer Trace

Select Scan Chain

Logic Analyzer Trace

Write Debug Control Register

TLL5000 Connections

FPGA Ball

Schematic Name

Functional Use

F26 FPGA_ACC4 tclk

G25 FPGA_ACC5 tms

H25 FPGA_ACC6 tdi

G26 FPGA_ACC7 tdo

H26 FPGA_ACC8 trst

FPGA Ball

Schematic Name

Functional Use

M2 RS232_TX tx_o

M1 RS232_RX rx_i

N1 RS232_CTS cts_i

M6 RS232_RTS rts_o

TLL5000 Connections