- 1 of 27 - Arithmetic, Logic, and ALU Introduction The ability to perform arithmetic and logical computations Critical task for computer ALU is common building block in most CPU type functions Device is able to perform variety of arithmetic and logical operations On two N bit numbers Generate N bit output Control inputs specify operation to be performed Most ALUs today can perform following operations • Simple operations Basic addition, subtraction, multiplication, division In very simple devices operations limited to Addition and subtraction Bit wise logical operations AND, OR, NOR, XOR Bit shift operations Shifting or rotating word Left or right With or without sign extension Comparison • Complex operations As complexity of supported operations increases Cost, size, and power all increase Complexity can branch in different directions Speed Perform elementary arithmetic or logical operations One or several clock cycles Barrel shifter is good example Can shift data word specified number of bits In single clock cycle Functionality Implement operations such as floating point math In hardware During course of our studies Will examine basic implementation of Four fundamental arithmetic functions Add Subtract Multiply Divide Several essential logical operations
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Arithmetic, Logic, and ALU Introduction The ability to ...Basic addition, subtraction, multiplication, division In very simple devices operations limited to . Addition and subtraction
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Arithmetic, Logic, and ALU Introduction
The ability to perform arithmetic and logical computations Critical task for computer
ALU is common building block in most CPU type functions Device is able to perform variety of arithmetic and logical operations
On two N bit numbers Generate N bit output
Control inputs specify operation to be performed Most ALUs today can perform following operations
Carry propagation Carry out from one column as carry in to next
Overflow In several cases
We get a carry out from the most significant bit This is called overflow The result is too large
To fit in word or register designated to hold it
Here we are working with 4 bit words We have a 5 bit result
Can potentially be serious problem If overflow not registered
Result can be interpreted as Adding two large numbers Producing small result
The Full Adder
We can build a hardware circuit To implement such an adder
In rather straight forward way
Begin with single bit adder Called full adder
A full adder has Three inputs
Augend bit Addend bit Carry in bit
Two outputs Sum bit Carry out bit
If we do not have carry in bit
Called half adder
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The full adder block diagram follows
To implement adder in hardware Begin with truth table
Must consider Two inputs and carry in Sum output and carry out X Y Ci S Co 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Can now write 2 equations S = !X!YCi + !XY!Ci + X!Y!Ci + XYCi
Co = !XYCi + X!YCi + XY!Ci + XYCi
These reduce to S = X ⊕Y ⊕ Ci Co = Ci (X ⊕Y)+ XY
Two equations give what we call full adder Inputs
X, Y, Ci Output
S, Co
Ripple Carry Adder Consider now that we are working with 4 bit words 1011 0110 ------------ 10001 The result of adding these two numbers
Generates carry out of MSB Result is too large to fit into 4 bits
Have produced overflow Must be aware of this
X
Y
CiCo
SumFull
Adder
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To compute 4 bit sum in hardware Can use 4 full adders from above We take the carry out from stage i
Treat as carry in to stage i+1 Thus for 4 bit adder we have
If we examine the process of producing the 4 bit sum
We observe that we cannot compute sum in column i+1 until Carry from column i is available
If we define the carry propagation delay as τcarry See that for each additional column
Availability of final sum delayed by τcarry For 32 bit word
Total delay 32 * τcarry Which can become significant
Advantage Design is low cost Simple to implement
Disadvantage Slow Long carry delay path Asynchronous
Carry Save Adder Carry save adder is simple and low cost Like ripple carry adder basic algorithm
Replicates pencil and paper method Components
Single full adder Several shift registers Control logic
Block diagram given in next diagram
In design Data
Loaded into X and Y registers in parallel Read from Sum register in parallel X, Y, and Sum registers n bits long
X
Y
CiCo
Sum
FullAdder
X
Y
Ci Co
Sum
FullAdder
X
Y
CiCo
Sum
FullAdder
X
Y
CiCo
Sum
FullAdder
D Q
QR
reset
clk
X
Y
Ci
sum
Co
load
load
X register
Y register
Sum register
Co
Data in
Data in
Data Out
Full Adder
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Control algorithm Reset Load X Load Y repeat n times
clock X, Y, Sum registers and D flip-flop end repeat Read Sum register and Co
Variations
X and Y registers can be Serially loaded Configured as circular registers
Sum register read serially Advantage
Design is low cost Simple to implement Synchronous Carry does not have long ripple path delay
Disadvantage Slow
Carry Look Ahead
To get around carry delay problem Use technique called carry look ahead
Idea amounts to computing carry at same time as sum Let’s examine the carry out equation from above
Co = Ci (X ⊕ Y) + XY
Examining equation Co will be a true under the following conditions
• When addend and augend bits are both 1 Such a condition generates a carry
• When either bit is 1 and there is a carry in Condition in which either bit is 1 cannot generate a carry However can combine with incoming carry
When working with signed numbers Express positive numbers in natural form
MSB is sign bit – value 0 Indicating positive
Express negative numbers in 2’s complement form MSB is sign bit – value 1
Indicating negative Will find occasions when must work with numeric values
With number of bits less than full word size Require such operations in two common cases
Short jumps in branching or looping operations Must jump forwards or backwards by few instruction addresses Typically implemented by
Adding (algebraically) value to PC
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Working with immediate mode constants as part of instruction Arithmetic with such shortened values proves interesting
When must put shortened value into full word Where do missing most significant bits come from
Consider 2 cases of adding 8 bit quantity to 16 bit word 1001 0011 1010 0110 + 0110 1110 1001 0011 1010 0110 + 1110 1110 When second operand placed into register
What goes into upper 8 bits In first case
Can simply fill with 0’s Following operation resulting sum will be correct
In second case Since MSB is 1 – number is negative 2’s complement Filling with 0’s will not give correct answer Now want upper 8 bits to be 1’s
To preserve 2’s complement We see then to ensure correct results
Positive number must be filled with 0’s Negative (2’s complement) number must be filled with 1’s
In reality such operations called sign extension Extending sign bit to fill MSB positions
Logical Operations
In addition to arithmetic operations ALU must be able to perform various logical type operations
Operations include Logic
AND, OR, XOR, complement Shifting
Left, right Circular (rotate), arithmetic, logical
Comparison >, >=, <. <=
Logic AND, OR, XOR
Can easily be implemented using standard logic gates Complement
Useful in arithmetic operations Can be implemented simply by
Inverting Q output from register Reading ~Q output from register
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Shift Several different kinds of shifts defined
Bit shift or logical shift All bits in register
Shifted left or right 0’s entered into register on left or right respectively
Often used when operand is interpreted as set of bits Rather than (signed) number
Logical shifts illustrated in next diagram
Logical left shift by 1 bit Logical right shift by 1 bit
Arithmetic shift
Also known as signed shift Similar to logical shift
One simple difference All bits in register
Shifted left or right Right shifts
MSB continually entered into register on left Preserves the sign
Called sign extension For signed operands
Left shift 0’s entered into register on right
Arithmetic shifts illustrated in next diagram
Arithmetic right shift by 1 bit Same as logical shift left
Logical right shift by 1 bit
Circular shift Circular shifts appear in cryptographic applications
Used to permute bit sequences
1 1 1 1 10 0 0
1 0 0 0 01 1 1 0
1 1 1 1 10 0 0
0 0 1 0 0 01 1 1
1 1 1 1 10 0 0
1 0 0 0 01 1 1 0
1 1 1 1 10 0 0
1 1 0 0 01 1 1
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Similar to logical and arithmetic shift One simple difference
All bits in register Shifted left or right Right shifts
LSB continually entered into register on left Left shift
MSB entered into register on right Circular shifts illustrated in next diagram
Circular right shift by 1 bit Circular left shift by 1 bit
Comparison Device will accept two N bit binary numbers Depending upon design
Will produce • Single output
Indicating that two input numbers are equal High level diagram given in accompanying figure
• Two outputs N1 is larger than N2 N2 is larger than N1 If both are true
Numbers are equal • Three outputs
N1 is larger than N2 N2 is larger than N1 N1 is equal to N2
More complex designs
Include inputs signaling Less than Greater than Equal
Using such inputs Can cascade series of comparators
To compare two M digit numbers High level diagram given in accompanying figure
Summary
Have introduced studied and developed Number of fundamental algorithms for
Performing basic arithmetic and logical computations Such computations are building block commonly found