Area and Speed Oriented Area and Speed Oriented Implementations Implementations of Asynchronous Logic of Asynchronous Logic Operating Under Strong Operating Under Strong Constraints Constraints Igor Lemberski Baltic International Academy Riga, Latvia e-mail: [email protected]Petr Fišer Czech Technical University in Prague Faculty of Information Technology e-mail: [email protected]
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Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints.
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Area and Speed Oriented ImplementationsArea and Speed Oriented Implementationsof Asynchronous Logicof Asynchronous Logic
Operating Under Strong ConstraintsOperating Under Strong Constraints
State-of-the-art Nodes are implemented as simple gates (NAND, XOR)
Proposed Nodes are implemented as complex gates, i.e. gates of a
given number of inputs and any function Can be implemented both in DIMS and Direct logic Like FPGA LUTs Tools for synchronous synthesis can be used
FPGA mapping
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 1616
Where’s the Problem?Where’s the Problem?
Facts:Increase of the number of node inputs will:
Decrease the number of nodesDecrease the number of levelsIncrease the node sizeIncrease the node delay
Question:
Where is the trade-off?Where is the trade-off?
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 1717
Experimental SetupExperimental Setup
228 circuits processed (MCNC, ISCAS)
Optimized by ABC choice script1. Mapped into k-input NANDs (ABC map command )
state-of-the-art (k-NAND)
2. Mapped into k-LUTs (ABC fpga command) complex gates (k-CG)
3. Mapped into MCNC standard cells (ABC map) something in-between (SC)
k = 2…6
Implemented as DIMS, Direct logic, and NCL
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 1818
Results – DIMS - AreaResults – DIMS - Area
SC
6-CG
5-CG
4-CG
3-CG
2-CG
6-NAND
5-NAND
4-NAND
3-NAND
2-NAND
0,0 2,0M 4,0M 6,0M 8,0M 10,0M 12,0M 14,0M 16,0M
Transistors
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 1919
Results – DIMS - AreaResults – DIMS - Area
SC
6-CG
5-CG
4-CG
3-CG
2-CG
6-NAND
5-NAND
4-NAND
3-NAND
2-NAND
0% 10% 20% 30% 40% 50% 60% 70%
Best in
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 2020
Results – DIMS – DelayResults – DIMS – Delay
SC
4-CG
3-CG
2-CG
4-NAND
3-NAND
2-NAND
0,0 5,0k 10,0k 15,0k 20,0k 25,0k
Delay
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 2121
Results – DIMS – DelayResults – DIMS – Delay
SC
4-CG
3-CG
2-CG
4-NAND
3-NAND
2-NAND
0% 10% 20% 30% 40% 50% 60%
Best in
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 2222
Discussion - DIMSDiscussion - DIMS
Implementation using arbitrary 2-input gates is the best one, both in area and delay
No big surprise. Complexity (and delay)of DIMS grows exponentially with the number of gate inputs
Results are consistent – the more node inputs, the higher area and delay
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 2323
Results – Direct Logic - AreaResults – Direct Logic - Area
SC
NCL
6-CG
5-CG
4-CG
3-CG
2-CG
6-NAND
5-NAND
4-NAND
3-NAND
2-NAND
0,0 500,0k 1,0M 1,5M 2,0M 2,5M 3,0M
Transistors
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 2424
Results - Direct Logic - AreaResults - Direct Logic - Area
SC
NCL
6-CG
5-CG
4-CG
3-CG
2-CG
6-NAND
5-NAND
4-NAND
3-NAND
2-NAND
0% 10% 20% 30% 40% 50%
Best in
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 2525
Results – Direct Logic - DelayResults – Direct Logic - Delay
SC
NCL
4-CG
3-CG
2-CG
4-NAND
3-NAND
2-NAND
0,0 5,0k 10,0k 15,0k 20,0k
Delay
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 2626
Results – Direct Logic - DelayResults – Direct Logic - Delay
SC
NCL
4-CG
3-CG
2-CG
4-NAND
3-NAND
2-NAND
0% 10% 20% 30% 40% 50% 60% 70%
Best in
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 2727
Discussion - Direct LogicDiscussion - Direct Logic
Implementation using 3-input complex gates is the best one, both in area and delay
This is a good result confirming our theoryResults are consistent - no coincidenceState-of-the-art 2-NAND implementation is extremely inefficient: 21% area improvement 19% delay improvement
3-CG implementation is even better than NCL 10% area improvement 19% delay improvement
EUROMICRO DSD 2010, LilleEUROMICRO DSD 2010, Lille 2828
ConclusionsConclusions
Efficient implementation of asynchronous logic Efficient implementation of asynchronous logic operating under strong constraints proposedoperating under strong constraints proposed
Tools (& methods) for synchronous synthesis Tools (& methods) for synchronous synthesis are used for asynchronous synthesisare used for asynchronous synthesis
3-input complex nodes implemented using Direct 3-input complex nodes implemented using Direct logiclogic
Extensive experiments confirmed the theoryExtensive experiments confirmed the theory
cca. 20% area and delay improvement vs. all cca. 20% area and delay improvement vs. all state-of-the-art methodsstate-of-the-art methods