Are Embedded Systems Ready for DDR3 DRAM Memory - …rtcgroup.com/arm/2007/presentations/146 - Are Embedd… · · 2007-10-25Are embedded systems ready for DDR3 DRAM memory? Marc

Are embedded systems ready for DDR3 DRAM memory?

Marc Greenberg, Technical Marketing Manager, Denali Badawi Dweik, Technical Marketing Manager, ARM

2© Copyright Denali Software, Inc. 2007 Confidential – Do Not Distribute or Reproduce

Agenda

How to select DRAM (including DDR3) for embedded systems

How to manage system speed and memory density issues when working with DDR3

How to solve physical interface challenges at the DDR3 interface


DDR Memory Pricing

1 DIMM = 8 billion units$39.99 retail

1 bag = 115 million units70 bags = 8 billion units$207.90 retail


Memory: The Blessing and the Curse

The Blessing: You get to use memory parts that offer great speed and density for very little cost, because they are produced in great volumeThe Curse: You have to interface to memory parts that have great speed and density, but were produced at very little cost because they are used in great volume


Selecting memory for embedded systems

How much memory (or how little?)How much bandwidth do you need? How many package pins can you use economically?

• Don’t forget power/ground for DDR signaling…


SDR(16) SDR(32)

Commodity DRAM Memory Selection

8MB

16MB

32MB

64MB

128MB

3.2Gb/s 6.4Gb/s 12.8Gb/s 25.6Gb/s 51.2Gb/s

DDR1 (16bit)

DDR2 (16bit)

DDR2(2*16bit)

DDR3 (16bit)

DDR3(2*16bit)

Predict

ed 20

10+ pr

ice pe

r bit

and a

vaila

bility

better

worse

Capacity

Bandwidth


Why DDR3? New standard propagated by JEDEC– Will be made by all major memory manufacturers– Like DDR1 & DDR2, main users will be PCs– Intel reference boards demonstrated at CeBIT, IDF early 2007

FasterLargerLower VoltageLower PowerLower Cost after price crossover– DDR2/3 Price crossover expected in 2009 – 2010

New Signal Integrity FeaturesSpecial features for DIMM support


DDR3 Cost / Price CrossoverEvery system should consider DDR3 if:– the system needs 128MByte or more, and if– the system will be in production in 2010

Example: DDR1/DDR2 price crossover – Price crossover happened Aug 2006– May 2007 DRAM spot prices:

• 512Mbit DDR1-400 device: $3.31 • 512Mbit DDR2-400 device: $2.01 --- 38% cheaper

If DDR2/3 price crossover happens in 2009, and if this pattern is repeated, then – DDR3 could be ~40% cheaper than DDR2 in 2010

• This is just an example. Denali cannot predict future commodity DRAM prices.


DDR3 – How does it work? Mem Array 100-200MHz

Mux

I/O 100-200MHz SDR

I/O100-200MHz DDR(DDR200-DDR400)

Mux I/O200-400MHz DDR2

(DDR2-400-DDR2-800)

Mem Array 100-200MHzMem Array 100-200MHz

Mem Array 100-200MHzMem Array 100-200MHzMem Array 100-200MHzMem Array 100-200MHz



Mux I/O400-800MHz DDR3

(DDR3-800-DDR3-1600)


DDR3 in Embedded SystemsMost of Denali’s Embedded customers using 16 or 32 bits of memory, and one rank (Chip Select) of memory.Smallest DDR3 devices will be 1Gbit (128MByte)– Some 512Mbit available, but probably won’t last long

Example 128MByte system needing 21Gbit/s peak bandwidth:

=

DDR3 is a savings in pins, power, board area– Expected to be lower cost per bit by 2010 as well

EmbeddedSystem333MHz

DDR2-667X16

DDR2-667X16

EmbeddedSystem667MHz

DDR3-1333X16

16bit

16bit

16bit

333MHz

667MHz

468mW*

322mW*estimated

* Based on DDR2-533/DDR3-1066 operation


DDR3 in Larger SystemsDenser Devices = More memory capacity– 2Gbit, 4Gbit devices on the horizon– Potential for 16GByte R-DIMMs

Faster = More BandwidthSaves Power = Runs Cooler (at a given frequency)– IDD4R power scales with voltage– Chip driver power on writes scales also– PASR and TCSR features

Special Features to support DIMM operation– Read Leveling and Write Leveling– Signal Integrity Features


DDR3 DIMM supportDDR3 U-DIMMs will use “Fly-By” Clk/Ctrl

Makes timing on control signals easierWrites must be sent for each memory at different times– Requires write leveling and read leveling at higher speeds– Only required for DIMMs, no read/write leveling needed for 1-2

chip systems

Unbuffered DIMM

Clock and Control signals

DDR3

Data/D

QS

DDR3

Data/D

QS

DDR3

Data/D

QS

DDR3

Data/D

QS

DDR3

Data/D

QS

DDR3

Data/D

QS

DDR3

Data/D

QS

DDR3

Data/D

QS


Denali Databahn support for DDR3

Built on proven, flexible, high-quality Databahnplatform as DDR2/3 Combo Includes all DDR2 Databahn featuresSupport for major DDR3 enhancements:– Initialization and Reset enhancements– Signal Integrity enhancements (ZQCL)– Array Changes (Nibble seq Burst-8)– Power Reductions (Precharge PD, PASR, TCSR)– Higher CAS latencies for higher speeds

First Customer delivery December 2006Available Now


Denali Memory Controller Compiler

XML based controller specificationSelect memories, denote library and speedGet delivery and demo environmentDenali industry-standard SOMA infrastructure


Denali’s Proven, High Quality Design IP

2407018

121516

109

Designs

240.14, 0.13, 0.09, 65nmOthers 90.18,0.11, 0.09

93Totals

70.18, 0.13, 0.09, 65nm90.18, 0.11, 0.0880.18, 0.15, 0.09

360.18,0.15, 0.13, 0.09, 65nm

SiliconProcessVendor


Total DDR solution

ProvenFlexible

MemoryController

(Soft IP)Configurable

Tuned

PhysicalInterface

(PHY)

DDR2

DDR2

DDR2

DDR2

DDR2/3

DDR2/3

DDR2/3

DDR2/3

DFIModule

A

ModuleB

ModuleN

ConfigurableTuned to application

High efficiency

SoC


PHY Choices

Wide range of PHY options– Your own– Denali’s– ARM’s– Hybridized (the architecture of Vendor X with hard

IP components such as DLLs from Vendor Y)– your ASIC vendor’s PHY, or – 3rd party PHY

DFI specification for controller-PHY connection– Makes PHY reuse a reality


DDR PHY Interface Spec (DFI)

Ensures reusability and promotes DDR solutionsDenali lead a collaboration of Intel, Denali, ARM, Samsung, and Synopsys to create the spec1000 engineers from 500 companies have downloaded itSpec recently extended to support DDR3

MemoryController

DDRPHY


Denali PHY Architectural ChoicesOverall Architecture– Proven in more than 50 customer designs– Denali’s 3rd generation PHY– Highly flexible, highly tunable

• 1X Clock, multiple DLLs

Correct “Slice” Hierarchy for design reuse– Enables rapid retargeting to new chips

Every tuning option is a “Get out of Jail Free” card…


Denali PHYDo it yourself from 100-266MHz– First order delay approximations go to zero about 266MHz

400MHz with expertise, SI help and hardened DLL– being done successfully now

New 533MHz DDR2 spec667MHz…800MHz… DDR3 and GDDR


Key Points of the Denali PHY Solution

ConfigurableComplete

– Timing closed Slice or complete GDSII PHY TOP– Logical views: RTL/models for simulations and tuning– Physical views for Floor planning and implementation– Timing budget tools– Verification suite – All scripts, constraints, .lib files and users manual

Flexible– IO-agnostic

Brings complete domain knowledgeBuilt on proven, high quality technology platform

– Built on Databahn configurable platform, which has produced 240 designs, 93 in silicon (100% success)


The Perfect DDR Sub-system

Cost

DensityPerformance


System Cost Variables

PHY Area Delta $0.01~ $0.25– Signal : Power ratio– x32,x16,x8 @ 400,800,1600MT/s

Package Delta $0.50~$2.50– FC vs WB– Pwr planes

PCB Layers Delta $2~$5– 4, 6, 8…layers– Etch spacing

DRAM Delta $2~$12– DDR2, DDR3, GDDR3– 256Mb, 512Mb, 1Gb– $/MByte & total Density


System Density & Configuration

512Mb– 32M x16– 64M x8– 128M x4

DDR264MB/device

256Mb– 16M x16– 32M x8– 64M x4

DDR132MB/device

1Gb– 64M x16– 128M x8– 256M x4

DDR3,2128MB/device

For System 256 MBytes– x32 Interface

• Option1: Two 64Mx16• Option2: Four 64Mx8• Option3: Eight 16Mx4


Define the ParametersFixed Parameters– Bus Width 8-bit, 16-bit, 32-bit, etc…– Max Data Rate 400Mbps, 667Mbps, 1066Mbps, etc..

PHY Pad Slice– x8 or x16 Data slice, Address, Controls, CLKs, Miscellaneous pads– Chip floor planning

Package – Staggered (Wirebond) or Flip Chip– Parasitic tolerated

System Topology– Total number of memory devices, 1 or 2 Ranks– PCB Routing Topology, package breakouts


Pad Slices Considerations

SoC

Signal to Power ratioCore SuppliesAnalog SuppliesOn-die Decoupling Crosstalk & SkewsEMShielding (noise coupling)Clock TreeESD Rules DDR Combo pad set


Package Design Considerations

Power/ground planesSignal couplingCrosstalkNoise couplingRLCG ParasiticSimultaneous Switching


Board Design Considerations

Board Power suppliesNumber of LayersTrace impedanceTrace width/spacingRouting topologyBoard Cross talkVia control


Timing Budget Analysis

End-to-End Timing Analysis (Si-to-Si) RequiredIn Both Directions (Write Analysis, Read Analysis)

Timing Budget broken:– Controller/PHY– Interconnect Link (PCB)– DRAM

Timing Budget (Margin) = Ideal UI – Total UncertaintiesDDR2-800 TB = 1.25ns – Σ abs(ĒTx, ĒLnk, ĒRx)DDR2-1066 TB = 938ps – Σ abs(ĒTx, ĒLnk, ĒRx)DDR3-1600 TB = 625ps – Σ abs(ĒTx, ĒLnk, ĒRx)


Write Cycle 800MT/sImpedance mismatchISIPCB CrosstalkTrace mismatch

DQ/DQS JitterDQ/DQS DCD

Pin-to Pin skewSSO Pushout

Package OffsetSetup/HoldSignal De-ratingVref Noise

PHY

PCB

DRAM 32%

34%

34%

0 1250


Write Cycle 1066MT/sImpedance mismatchISIPCB CrosstalkTrace mismatch

DQ/DQS JitterDQ/DQS DCD

Pin-to Pin skewSSO Pushout

Package OffsetSetup/HoldSignal De-ratingVref Noise

PHY

PCB

DRAM 42%

37%

21%

0 938


Read Cycle 800MT/sImpedance mismatchISIPCB CrosstalkTrace mismatch

Package offsetData/DQS skew

DLL/PLL JitterDLL/PLL DCD

ODT MismatchRx Setup/Hold

tDQSQDCD, tQHSVref Noise

DRAM 44%

0 1250

PCB 34%

PHY 22%


Read Cycle 1066MT/sImpedance mismatchISIPCB CrosstalkTrace mismatch

Package offsetData/DQS skew

DLL/PLL JitterDLL/PLL DCD

ODT MismatchRx Setup/Hold

tDQSQDCD, tQHSVref Noise

DRAM 50%

0 938

PCB 45%

PHY 5% ???20%X

30%X


Summary

Higher DDR speeds increases the need for an End-to-End System DesignDetermine Cost, Density, Performance trade-offs achievable by your sub-systemChoose Silicon validated IP blocks Use System level approach to achieve timing closure


ConclusionAdvanced Memory Controller/PHY/IO design is hard!Look for IP that provide you with most flexibility, scalability and reliabilityDenali and ARM can give you – Access to High-Speed, High-Density, Low-Cost DDR-SDRAM– Choices of memory controllers– Choices of PHYs– Choices of I/Os

Total DDR memory connectivity!

Are Embedded Systems Ready for DDR3 DRAM Memory - …rtcgroup.com/arm/2007/presentations/146 - Are Embedd… · · 2007-10-25Are embedded systems ready for DDR3 DRAM memory? Marc

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