Architecting Phase Change Memory as a Scalable DRAM Alternative Benjamin Lee † , Engin Ipek † , Onur Mutlu ‡ , Doug Burger † † Computer Architecture Group Microsoft Research ‡ Computer Architecture Lab Carnegie Mellon University International Symposium on Computer Architecture 22 June 2009 Benjamin C. Lee et al. 1 :: ISCA :: 22 June 09
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Architecting Phase Change Memory as aScalable DRAM Alternative
Benjamin Lee†, Engin Ipek†, Onur Mutlu‡, Doug Burger†
† Computer Architecture GroupMicrosoft Research
‡ Computer Architecture LabCarnegie Mellon University
International Symposium on Computer Architecture22 June 2009
Benjamin C. Lee et al. 1 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Memory ScalingCharge MemoryResistive Memory
Memory in Transition
I Charge MemoryB Write data by capturing charge QB Read data by detecting voltage VB Examples: Flash, DRAM
I Resistive MemoryB Write data by driving current dQ/dtB Read data by detecting resistance RB Examples: PCM, MRAM, memristor
Benjamin C. Lee et al. 2 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Memory ScalingCharge MemoryResistive Memory
Limits of Charge Memory
B Unscalable charge placement and control
B Flash: floating gate charge
B DRAM: capacitor charge, transistor leakage
Benjamin C. Lee et al. 3 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Memory ScalingCharge MemoryResistive Memory
Towards Resistive Memory
I ScalableB Program with current ∝ cell sizeB Map resistance to logical state
I Non-VolatileB Set atomic structure in cellB Incur activation cost
I CompetitiveB Achieve viable delay, energy, enduranceB Scale to further improve metrics
Benjamin C. Lee et al. 4 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Memory ScalingCharge MemoryResistive Memory
PCM Deployment
B Deploy PCM on the memory bus
B Begin by co-locating PCM, DRAM
B Begin by deploying in low-power platforms
Benjamin C. Lee et al. 5 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Outline
I MotivationB Memory ScalingB Charge MemoryB Resistive Memory
I TechnologyB Phase Change MemoryB Technology ParametersB Price of Scalability
I ArchitectureB Design ObjectivesB Buffer OrganizationB Partial Writes
Benjamin C. Lee et al. 6 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Phase Change Memory
B Store data within phase change material [Ovshinsky68]
B Set phase via current pulse
B Detect phase via resistance (amorphous/crystalline)
Benjamin C. Lee et al. 7 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
PCM Scalability
B Program with current pulses, which scale linearly
B PCM roadmap to 30nm [Raoux+08]
B Flash/DRAM roadmap to 40nm [ITRS07]
Benjamin C. Lee et al. 8 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
PCM Non-Volatility
I Atomic StructureB Program with current pulsesB Melt material at 650 ◦CB Cool material to desired phase
I Activation CostB Crystallize with high activation energyB Isolate thermal effects to target cellB Retain data for >10 years at 85 ◦C
Benjamin C. Lee et al. 9 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Technology ParametersB Survey prototypes from 2003-2008 [ISSCC][VLSI][IEDM][ITRS]
B Derive parameters for F=90nm
DensityB 9 - 12F2 using BJT
B 1.5× DRAM
EnduranceB 1E+08 writes
B 1E-08× DRAM
LatencyB 50ns Rd, 150ns Wr
B 4×, 12× DRAM
EnergyB 40µA Rd, 150µA Wr
B 2×, 43× DRAM
Benjamin C. Lee et al. 10 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Technology ParametersB Survey prototypes from 2003-2008 [ISSCC][VLSI][IEDM][ITRS]
B Derive parameters for F=90nm
DensityB 9 - 12F2 using BJT
B 1.5× DRAM
EnduranceB 1E+08 writes
B 1E-08× DRAM
LatencyB 50ns Rd, 150ns Wr
B 4×, 12× DRAM
EnergyB 40µA Rd, 150µA Wr
B 2×, 43× DRAM
Benjamin C. Lee et al. 10 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Technology ParametersB Survey prototypes from 2003-2008 [ISSCC][VLSI][IEDM][ITRS]
B Derive parameters for F=90nm
DensityB 9 - 12F2 using BJT
B 1.5× DRAM
EnduranceB 1E+08 writes
B 1E-08× DRAM
LatencyB 50ns Rd, 150ns Wr
B 4×, 12× DRAM
EnergyB 40µA Rd, 150µA Wr
B 2×, 43× DRAM
Benjamin C. Lee et al. 10 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Technology ParametersB Survey prototypes from 2003-2008 [ISSCC][VLSI][IEDM][ITRS]
B Derive parameters for F=90nm
DensityB 9 - 12F2 using BJT
B 1.5× DRAM
EnduranceB 1E+08 writes
B 1E-08× DRAM
LatencyB 50ns Rd, 150ns Wr
B 4×, 12× DRAM
EnergyB 40µA Rd, 150µA Wr
B 2×, 43× DRAM
Benjamin C. Lee et al. 10 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Price of ScalabilityB 1.6× delay, 2.2× energy, 500-hour lifetime
I Wear MechanismB Writes induce phase change at 650 ◦CB Contacts degrade from thermal expansion/contractionB Current injection is less reliable after 1E+08 writes
I Partial WritesB Reduce writes to PCM arrayB Write only stored lines (64B), words (4B)B Add cache line state with 0.2%, 3.1% overhead
J.Condit et al. “Better I/O through byte-addressable, persistentmemory.” SOSP-22: Symposium on Operating System Principles,October 2009. (To Appear)
I File System PropertiesB Consistency :: COW with atomicity, orderingB Safety :: Reflect writes to PCM in O(ms), not O(s)B Performance :: Outperform NTFS on RAM disk
I Architectural SupportB Atomic 8B writes with capacitive supportB Ordered writes with barrier-delimited epochs
Benjamin C. Lee et al. 22 :: ISCA :: 22 June 09
Architecting Phase Change Memory as aScalable DRAM Alternative
Benjamin Lee†, Engin Ipek†, Onur Mutlu‡, Doug Burger†
† Computer Architecture GroupMicrosoft Research
‡ Computer Architecture LabCarnegie Mellon University
International Symposium on Computer Architecture22 June 2009