Applying Model-Based Design to a GPS Receiver Mike Donovan Senior Applications Engineer The MathWorks June 15, 2006 © 2006 The MathWorks, Inc.
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Applying Model-Based Design to a GPS Receiver
Mike Donovan Senior Applications Engineer The MathWorks June 15, 2006
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Outline
� Goals and Objectives � GPS History and Basics � A Simple Receiver Model � Detailed Model with Tracking Loops � Acquiring Actual GPS Signals � Searching for Satellites � Receiver Using Actual Data � Transition to Fixed Point � FPGA Partition � DSP Partition
Boeing Delta II lofting a� Hardware Demo new GPS satellite, June 2004
2
Goals and Objectives
� Model-Based Design example – from concept to operating hardware
� Contemporary communications concepts – Fixed-rate receiver sampling
� Fractional delay timing adjustment � Amenable to FPGA and ASIC
– Code division multiple access � Signal acquisition � Signal tracking
� Hardware implementation – FPGA for heavy lifting – DSP for acquisition and control laws
3
Global Positioning System Facts
� There are 24 satellites in the constellation. � They orbit the earth about 12,255 miles (20,200 Km) above us. � Traveling at 7000 miles an hour, they complete two orbits
in less than 24 hours. � Transmitter power is <=50 watts in the “L” band (1-2GHz),
10 dB antenna gain. � Civilian GPS uses the frequency of 1575.42 MHz in the UHF band. � All GPS timing is a multiple of 1.023 MHz
(e.g., 1540*1.023MHz=1.57542 GHz).
(Garmin: http://www.garmin.com/aboutGPS/)
4
A Simple GPS ModelSimple GPS Model � Two clear acquisition
(C/A) code (base band) transmitters
� Band limiting filters � Simple channel model � Cross correlating receiver
Q: How does one tell time? A: Cross correlation of local code
with received codeC/A = "Clear Acquistion"
Clear = Unencrypted
z -i
In
Delay Out
path 2
z -i
In
Delay Out
path 1
down== Channel Bypass
dBm
In1 Channel
By pass
Tx-> Channel -> Rx Model1
prn Out
Satel l ite B C/A code
prn Out
Satel l ite A C/A code
22
Rx PRN1
21
Rx PRN
Time
Rx Correlation prn Out1
Rx C/A code
In1 Out1
Pwr Est
200
Path 2 Delay (samples)
100
Path 1 Delay (samples)
PRN Select
One or Both
D
Gain2
D
Phase/
Phase/
Doppler 1
Discrete-Time
Scope Cross Correlator
Add
[1023x1]
[1023x1]
[1023x1]
Gain1
x[8n]
FIR Decimation
Frequency Offset
Doppler 2
Frequency Offset
Scatter Plot
In1
In2
Out1
22
C/A prn id 2
21
C/A prn id 1
1024
[1023x1] [1023x1]
[1023x1]
[1023x1]
[1023x1]
[1023x1]
[1023x1]
[1023x1]
[1023x1]
[1023x1]
[1023x1]
[1023x1]
[1023x1]
[1023x1]
[1023x1]
[1023x1] [1023x1]
[1023x1]
� Model purpose – Investigation of basic GPS
concepts
– CDMA example
5
Limitations of Simple Model
� Doesn’t use real GPS satellite source data � No acquisition mode (search through possible
Doppler shift and C/A code phase) � Assumes perfect clock synchronization
between Rx and Tx
6
Capturing Satellite Signals (LeCroy)
� Need down conversion hardware for rational data set size � Instrument Control Toolbox or LeCroy interface
GPS Down Converter and Signal Capture Hardware
Antenna LNA
Amplifiers, Filter, Mixer (Down Converter)
Local Oscillator
1575.42+17.0 MHz Local Oscillator
RF
Spectrum of 17 MHz IF
LeCroy Oscilloscope 50 MSPS, 48MS deep
17MHz IF
7
Simple Script to Capture 17 MHz IF
� Scope parameters – Fs= 50 MSPS – 48e6 MS deep memory
� Script: Eight lines of MATLAB®
8
Searching for Satellites in the Data Set � Typically three parameters to search
– Which birds are visible (PRN ID) – C/A code phase – Doppler shift
� Commercial GPS used to identify visible birds (simplify search)
doppler freq
-700
k2
z -i
In
Delay Out
Variable Integer Delay
yout
Signal From Workspace
Manual Switch
In1 Out1
Local C/A code
Out1
Freq_slew
x[8n]
FIR Decimation
0
Doppler Search
Discrete-Time VCO
Discrete-Time VCO
De-Rotate
single
Data Type Conversion
l im
Counter Limited
22
C/A prn id
single [1023x1] int8 (c) [8184x1]
[8184x1]
[1023x1]
int8 (c) [8184x1] uint8
Buffer
single (c) [1023x1]
double (c)
single (c) [1023x1]
[1023x1]
double (c) [1023x1] double double
double
double
single (c) [8184x1]
local C/A
Rx
Freq
sample
sample phase
Doppler
Max Value
delay/data estimator
uint8 2
sample phase � Key model double 100outputs single 1364– Verification
max correlation value of signal level Data Set: GPS_long_2
ID Doppler
Max prn 3 -800
748– Doppler prn 14 -2800 818prn 15 0
883prn 18 1600 983shift value prn 21 2000 1041prn 22
100 1364
9
GPS Model with Timing Recovery � Variable clock rate at Tx (Fs_Tx = 8*1.023e6*(1 +/- delta)) � Essentially the same channel model including Doppler � Fixed sampling rate receiver (Fs_Rx = 8*1.023e6) � Fractional delay scheme for C/A Rx code loop � Doppler NCO loop
GPS Tx & Rx Model
10
up=Scatter Plot On 0
k6
1
k3
-C
k1
dBm
In1 Channel
By pass
Tx-> Channel -> Rx Model with Doppler
Sy mbol Rate Error
TX_PRN
Tx Out
Chip Clock
Transmitter with Variable Symbol Timing Error
3
TX PRN ID
0.01
Sym bol Rate Error i n Percent
In1
Scatter Plot
B-FFT
RX Spectrum 3
RX PRN ID
In1 Out1
Pwr Est
I/Q In
PRN ID
Rx Chip Clock
Sig Monitor
Rx Out
GPS Receiver
Correl ation
Chipping Clocks
Channel Bypass Xmit Chip Clock
Fs=8*1.023MHz
Fs=8*1.023MHz
Receiver Processing Satellite Data
� Fixed 8.000 MSPS I/Q data rate � Partitioning of tasks to FPGA and DSP � Inputs: PRN, Doppler, and initial C/A code phase � Simple code acquisition control � Model verifies that the processing scheme is
soundGPS Receiver Processing Captured Satellite Data.
GPS I/Q Signal 8MSPS
22single single
RX PRN ID 1 single single
k1 init code phase
725
FPGA_Partition 1 single
1 single
singlesingle single
k3
100
Init Doppler DSP Partition k2
Init Delay20
Terminator
yout_8msps_long_2 8 MSPS GPS I/Q
Doppler_NCO_Control
Code_NCO_Control
PRN
Code Phase
Load Code Phase
Acc_Strobe
Sig Lev el
TP
Acc_Early
Acc_Late
Acc_Prompt
z -1
Lev el
Early
Late
Prompt
Doppler
Carrier NCO
Code NCO Control
single (c)
single
single (c)
int8 (c)
single (c)
single
single
single
single
k4
11
0.9766
0.9775
Data Type Conversion2
Transition to Fixed Point – First, Take it Apart � Multiple subsystems with local and global feedback are a challenge � My preferred method: Transition one subsystem at a time
((2/D)/1023 )
k1
Control In
Clock Out
Delay Control
Timing Control Unit Scope
4000
Gain
Control In
Clock Out
Delay Control
Fixed Point Timing Control Unit
Display1
Display
single
single
Data Type Conversion1
Convert
Data Type Conversion
single single
single
boolean
single single
sf ix8_En7
sf ix8_En7 single
single
single
0.25
k1
Pulse Generator
Xin
Mu Y out
Fixed Point
Xin
Mu
Yout
Farrow Variable Delay
single
Data Type Conversion3
single
Data Type Conversion2
Convert
Data Type Conversion1
Convert
Data Type Conversion
single
double
single single
sf ix8_En7
sf ix8_En7
sf ix8_En7
single
single
Scope
12
Then, Put it Back Together � High probability of success � Re-test with actual GPS signals
GPS Receiver Processing Captured Satellite Data.
0
k4
1
k3
1
k2
1
k1
725
init code phase
Terminator 22
RX PRN ID
100
Init Doppler Init
yout_8msps_long_2
GPS I/Q Signal 8MSPS
8 MSPS GPS I/Q
Doppler_NCO_Control
Code_NCO_Control
PRN
Code Phase
Load Code Phase
Acc_Strobe
Sig Lev el
TP
Acc_Early
Acc_Late
Acc_Prompt
FPGA_Processing
z -1
Delay2
single
Data Type Conversion9
single
Data Type Conversion8 Convert
Data Type Conversion4 single
Data Type Conversion10
Lev el
Early
Late
Prompt
Doppler
Carrier NCO
Code NCO Control
DSP Chip Processing
sf ix16_En6 (c)
boolean
sf ix16_En6 (c)
sf ix16_En6 (c)
int8 (c)
uint8
single single
single
single
single
sf ix8_En7
single single boolean boolean
boolean
boolean
uf ix10
single (c)
single (c)
single (c)
13
Transition to FPGA � Plan Ahead
– Use blocks that will easily map to the target hardware or IP – Avoid divides, square roots, logs, trig functions if possible – Use techniques amenable to hardware
� Enabled, not triggered, subsystems
� Same strategy: Transition one subsystem at a time
Control In
Clock Out
Delay Control
fpt dbl
fpt dbl
Control In
Clock Out
Delay Control
Control In
Clock Out
Delay Control
single Data Type Conversion6
single
Data Type Conversion5
single
single sf ix8_En7
double
boolean single
single
single
single
single single
((2/D)/1023 )
k1
dbl fpt
Gateway In1
4e3
Gain
0.9775
Display
Convert
Data Type Conversion4
Data Type Conversion2
double double sf ix8_En7
Fix_8_7
clocks single
Timing Control Unit
single
single control
Fixed Point Timing Control Unit Data Type Conversion1
Bool double
Gateway Out2 Fix_8_7 single
Gateway Out1 FPGA Data Type Conversion3
Sy stem Generator
14
0
0
FPGA Partition � Reassemble the “transitioned” subsystems � Add interface to DSP
GPS Signal Processor, FPGA Partition – Static gateways to control � PRN selection
In1
TCU
PRN
TCU and PRN Interface
((2/D)/1023 )
TCU
I_in
Q_in1
Doppler Freq
TCU
PRN
Strobe
Lev el
Early _R
Early _I
Prompt_R
Prompt_I
Late_R
Late_I
Rx5
RX PRN
Strobe
Lev el
Early _R
Early _I
Prompt_R
Prompt_I
Late_R
Late_I
Data
Load
Interface
IF test
ADC
IQtp
I_f p
Q_f p
IF Processor
fpt dbl
Gateway Out3
fpt dbl
Gateway Out1
-K-
Gain
In1 Out1
Doppler VCO Interface
100/(Fs_adc/16)
Doppler Frequency
Display1
Display
Re(u)
Im(u)
Complex to Real-Imag
TCU
PRN Out1
Combine TCU PRN (DSP) REG 1
Board configuration
ADC1
ADC1 17 MHz IF input
doubledouble Fix_14_13
UFix_32_32
double (c)
single
double
single
Fix_7_6
Fix_7_6
uint32
uint32 Fix_8_7
UFix_5_0
Bool
UFix_16_0
Fix_16_5
Fix_16_5
Fix_16_5
Fix_16_5
Fix_16_5
Fix_16_5
double
double
double
double double
Log Viewer Sy stem Generator � Doppler NCO
removed callback � Code NCO UFix_32_0
– FIFO buffered interface DSP Bus1 for correlation data and
Write to DSP is at 1 MHz burst rate
Bool signal level
Terminator
bus0
uint32
� FPGA design includes GPS signal generator for stand-alone operation
0 single Tx TCU
Tx PRN In1
TCU
PRN
TCU
PRN Out1
-K- single Fix_8_7 uint32
T CU Error Gain1 UFix_5_0
uint32 Combine TX TCU PRN TX TCU and PRN Test CA Generator(DSP) Interface (Xmitter@17MHz IF)
5
15
Built In Tx(FPGA)
DSP Partition � Includes
– C/A code timing loop filter – Doppler loop filter – Automatic gain control – Stateflow® signal acquisition
controller – Control of built-in GPS test
signal � Two modes of operation
– Lab needs RF hardware – Stand alone uses test signal
� Extensive use of external mode for (20) controls anddisplays
� 1 KHz C/A update rate consumes < 5% of CPU
100
sync word
In1
Sy nc_Word
Lev el
Early
Prompt
Late
index 0
Data Phase
uint32
single
uint8
single (c)
single
single (c)
single (c)
FPGA TCU & PRN
For stand alone demo, use antennas OR coax
to connect RF out to RF in
951.1
Sat Doppler in Hz
14
PRN
0.2059
Level
FPGA Doppler Register 0
Sig Lev el
Early
Prompt
Late
Carrier NCO Control
Code NCO Control
Sat Doppler
Lev el
DSP Partition
PRN
Combine TCU PRN (DSP)
single
single
single uint32
single
TCU Out1 uint32
Register 1 DSP Bus Rx
SignalWAVe FPGA Interface RTW Options
single ICLKA 0double 4.254
0
0 single
Clock Sel CPU % Clock Error (-0.2 -> 0.2) uint32
Profiler FPGA ADC&DAC TX PRN
1 -> 31, 0 turns Tx OFF
Clock Error
PRN
16
Development Hardware: Lyrtech SignalWAVe
� Texas Instruments C6713 DSP � Xilinx Virtex-II XC2V3000 FPGA � Memory
– 32 MB SDRAM (DSP) – 32 MB SDRAM (FPGA)
� Input/Output – 65MSPS 14-bit ADC with programmable
gain – 125MSPS 14-bit DAC – NTSC/PAL composite video Decoder – NTSC/PAL composite video encoder – Audio codec
17
Resources Consumed
� FPGA Resources – 364 *.vhd entries, 794 KB source – 22% of xc2v3000 fabric (RX+Tx) – 64 MSPS Rx in, 64 MSPS Tx out
� DSP Resources – 10 files, 155 KB of source code – <5% of CPU horsepower – 8 KSPS in, 4 KSPS out (16b)
18
The first prototype of the digital IF receiver module
Sandia implements high-performance radar receiver using MathWorks and Xilinx DSP design tools The Challenge� To design a digital radar receiver and
implement it on the Virtex-II platform FPGA within strict time and budgetary limits
The Solution � Use MathWorks and Xilinx DSP design
software to create, simulate, test, and synthesize designs into hardware
The Results � Accelerated design “We are so impressed with the
tools and the direction in which � High-speed simulation The MathWorks and Xilinx are � Accurate representation of the actual going that we plan to make this our
system mainstream DSP design flow.” Dale Dubbert
Sandia National Laboratories
19
Rockwell Collins accelerates development of next-generation military GPS receivers with code generated by Embedded Target for TI C6000™ DSP
20
The Challenge To study and validate the new requirements of nextgeneration advanced military GPS receivers The Solution Use MathWorks tools for Model-Based Design to streamline modeling, simulation, automatic code generation, and hardware-in-the-loop testing of GPS functionality The Results � Prototype iterations accelerated � Customer expectations exceeded � Target debugging minimized
“MathWorks tools for Model-Based Design provide us with an integrated environment and a push-button solution for automatically generating quality code that significantly cuts development time.”
Kevin Neigum, Rockwell Collins
“MathWorks tools for Model-Based Design provide us with an integrated environmentand a push-button solution for automatically generating qualitycode that significantly cuts development time.”
Kevin Neigum, Rockwell Collins
Next-generation GPS device
Conclusion � Challenging problem
(“needles in a haystack”) � Entire Model-Based Design flow
– Signal Processing – T&M – Control Systems – Control Logic
� Contemporary comms concepts – CDMA – Fractional delay timing recovery
� Hardware and software design – FPGA using Xilinx System Generator – DSP using Real-Time Workshop® and
Embedded Target for TI C6000™ DSP– Implemented on SignalWave
� SDR example, hardware can be – SSB Tx/Rx
An F-16 drops a JDAM-equipped GBU-31 – GPS Tx/Rx 2,000-pound bomb.
21
More Information on this Example
� Google Search: “Dick Benson GPS”
� MathWorks recorded webinar (10/06/2005) www.mathworks.com/cmspro/req11242.html?eventid=31371
� DSP-FPGA.com article online (01/07/2006) www.dsp-fpga.com/articles/benson/
22
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