Kwang-Hyun Cho, Jaebeom Kim, Chi-Ho Cha, Junhyung Um, Euibong Jung, Sik Kim, Byeong Min, Kyu-Myung Choi Design Technology Team, System LSI Division, Samsung Electronics Applications of Platform Explorer, Integrator and Verifier in SoC Designs Applications of Platform Explorer, Integrator and Verifier in SoC Designs July July 2 2 9 9 , , 200 200 9 9 DAC 2009 User Forum Poster DAC 2009 User Forum Poster
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Kwang-Hyun Cho, Jaebeom Kim, Chi-Ho Cha, Junhyung Um,Euibong Jung, Sik Kim, Byeong Min, Kyu-Myung Choi
SoC Architecture DesignSoC Architecture Design•• Performance verification and Performance verification and
validation with architecturevalidation with architecture•• Architecture optimizationArchitecture optimization•• High speed simulation with TLMHigh speed simulation with TLM
Platform IntegrationPlatform Integration•• IP configuration and packagingIP configuration and packaging•• System configuration and integrationSystem configuration and integration•• RTL Generation AutomationRTL Generation Automation
Platform VerificationPlatform Verification•• IP verificationIP verification•• Bus fabric based verificationBus fabric based verification•• Full chip level verificationFull chip level verification
SoC Platform Architecture ExplorationSoC Platform Architecture ExplorationPlatform Explorer
Virtual PlatformVirtual Platform(ViP)(ViP)
Adaptor in ViP
HWiInterface SW (API)
HWiDevice Driver
HWiControl Logic
Top level Signals
DUT(with Tracer Chain)
SW P
art
HW P
art
FPGA #1HWi Engine
FPGA #2DUT (1)
PLX
HWi SWHWi SWAdaptorAdaptor
PCI 2.0
•Legacy RTL IP and FPGA co-simulation (with HW Integrator)
Usability and ScalabilitySimulation speed improvement
•Legacy RTL IP and FPGA co-simulation (with HW Integrator)
Usability and ScalabilitySimulation speed improvement
•System-level Power ManagementDynamic Voltage SchedulingDynamic Power Management
•System-level Power ManagementDynamic Voltage SchedulingDynamic Power Management
IP Packaging and Platform IntegrationIP Packaging and Platform Integration
Integration Tool
System Configuration • Easy to integrate IPs into a Platform• Correct by Construction• Automatic error checking • Effective database management for reuse
Connection (Standard I/F)
Memory Map
Parameters Management
Synthesis / Verification
Packaged IPs with IP-XACT
Integration AutomationPlatform Integration
AHBMaster
Slave
AXIMaster
IP1AHB Slave
IP2AHB Master
IP3AXI Slave
ConnectionCandidateSelection
Automatic
Connection
SoC Platform
Platform Integrator
Flow Automation for Platform IntegrationFlow Automation for Platform Integration
Custom Bus Interface Definition
Memory map
RTL IP code, document
Component Interface Mapping
Configured RTL & IP-XACT
IP Packaging
System Integration
Subsystem Integration
BUS RTL Generation
SPIRIT Database
IP.xmlIP.xmlIP.xml Subsystem.xml
RTL Doc
Memory Map
Interfaces
Testbench Parameters
Interfacesdefinition
• Legacy, Imported IPFixed / Parameterized / Configurable IP
Full Chip RTL from Platform Integrator RTL Bus Fabric
• # of master• # of slave• configuration• address map• connectivity
IP-XACT
Random Transaction Gen.
Random Response Gen.
CoverageMonitor
Automatic RTL code manipulationTest sequence generationCoverage model generationConfigurable testbench for various verification purpose
- No change in top RTL- Replacing IPs with
fake modules
TestSequence
Full ChipBUS Interconnect
Coverage chart shows which master/slave connection is checked
- No change in top RTL,- IP is replaced with a fake
module to setup eVC
Platform Verifier: Register Access TestPlatform Verifier: Register Access Test
IP Component
Signals
ViewsFiles
Bus Interface
Memory map
Choices
Generator
Packaged IP (IP-XACT)
Register (SFR) Info• Name• Fields• Size• Offset• Access Type (RO, WO, RW)• Reset Value
Register (SFR) Info• Name• Fields• Size• Offset• Access Type (RO, WO, RW)• Reset Value
Testbench and Test Sequence Generation for Register Access TestAutomated Register Reset Value Test
Automatic setup of full chip verification environment Automatic setup of full chip verification environment
Platform Verifier: Configurable TestbenchPlatform Verifier: Configurable TestbenchGenerate Testbenches for Various Verification PurposeGenerate Testbenches for Various Verification Purpose
Bus1Bus2
CPU IP1 IP2IP3 IP4
IP5 IP6 IP7IP8
Bus1Bus2
CPU IP1 IP2IP3 IP4
IP5 IP6 IP7IP8
eVC
eVCeVC eVC
eVC
Bus1Bus2
CPU IP1 IP2IP3 IP4
IP5 IP6 IP7IP8
eVC eVC
eVC
eVC
Integrated Platform
Config A
Config B
IP Component
Signals
ViewsFiles
Bus Interface
Memory map
Choices
Generator
IP Component
Signals
ViewsFiles
Bus Interface
Memory map
Choices
Generator
Case Study: Applications to SoC Platforms (1/2)Case Study: Applications to SoC Platforms (1/2)
IP Interface Definition and Mapping IP Interface Definition and Mapping
• Reduce the number of connections• Reduce the human errors• Reduce the integration design time
- Mother version of platform : 30%- Derivative platform : over 50%
Automation of topAutomation of top--level interconnect based on the interface level interconnect based on the interface definition (RPTKit)definition (RPTKit)
Design 1 Design 2 Design 3
Bus
M1
M2
M3
S1
S2
S3
Bus
M1
M2
M3
S1
S2
S3
Case Study: Applications to SoC Platforms (2/2)Case Study: Applications to SoC Platforms (2/2)
Full ChipFull ChipBus InterconnectBus Interconnect
Detected one bug in 2 days70% reduction of verification effort
Verification of SoC full chip busVerification of SoC full chip bus
Code Generation Lines
Specman TB 27,155(103 files)
Verilog RTL 20,313(40 files)
Script etc. 2,500
GeneratedVerification
Env.
Benefit of Reusable Platform Design MethodologyBenefit of Reusable Platform Design Methodology
Design steps for platform integration and verificationDesign steps for platform integration and verification
BUS FabricGeneration
Interface basedTop Generation
Bus FabricVerification
Fully connected Top RTL
Generation
Full ChipVerification
Full Chip RTL
Bus Fabric basedPlatform Integration
• Derivative Platforms : Reuse of packaged IPs TAT ↓
IP Preparation & Packaging (40~60ea)
IP Packaging (20~30ea)
Mother
Derivative
Bus Fabric based Platform Verification
Manual Top Integration
Full Chip Verification
Full Chip RTL
TAT Reduction over 50%
Bus FabricGeneration IP Preparation
TAT Reduction30%
IP Wrapper(IP-XACT)
Sub-systemGeneration
SummarySummary
Reusable SoC Platform Design MethodologyReusable SoC Platform Design MethodologyNovel platform based SoC design methodology and flowNovel platform based SoC design methodology and flowFully exploit the IP Reuse with SPIRIT IPFully exploit the IP Reuse with SPIRIT IP--XACTXACTPlatform ExplorerPlatform Explorer
Architecture exploration and optimization Architecture exploration and optimization for high performance & low power for high performance & low power SoCsSoCs
Platform IntegratorPlatform IntegratorAutomation of SoC platform integration Automation of SoC platform integration Efficiency and reliability with RPTKitEfficiency and reliability with RPTKit
Platform VerifierPlatform VerifierAutomation of verification environment setupAutomation of verification environment setupfor buses fabric, topfor buses fabric, top--level testbenchlevel testbench
A lot of Experiences of SoC ApplicationA lot of Experiences of SoC ApplicationDemonstrated the validity and capabilityDemonstrated the validity and capabilityReduced platform design time 30% in mother versionReduced platform design time 30% in mother versionMore than 50% in derivative platformsMore than 50% in derivative platforms