Application of UML for Hardware Design Based on Design Process Model

Application of UML for Hardware Design Based on Design Process Model

Application of UML for Hardware Design Based on Design Process Model

Speaker: Prof. Vytautas STUIKYS, Software Engineering Department,

Kaunas University of Technology,

Kaunas, Lithuania

E-mail: [email protected]

Phone: +370-37-300399

Authors: R. Damasevicius, V. StuikysAuthors: R. Damasevicius, V. Stuikys

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ContentContent

Motivation

Higher-Level Abstractions: Design Processes & UML-Based Specification Taxonomy, Definition, Examples

Metamodel for Conversion of a given Specification from UML to VHDL

Design Flow, Experiments

Evaluation, Discussion, Conclusions

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MOTIVATIONMOTIVATION

MAIN DESIGN PROBLEM (Complexity and its derivatives - quality, productivity, time-to market) can be solved through: Higher Reuse content at all design levels System-Level Design Novel design methodologies (e.g., Platform-Based

Design) Standardization initiatives RAISING THE ABSTRACTION LEVEL IN DESIGN

We INTRODUCE 3 higher-level abstractions DESIGN PROCESSES UML for specifying Design Processes (PD) METAPROGRAMMING for specifying generic functionality

within a DP

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Design Processes within Platform-Based Design: General View

Design Processes within Platform-Based Design: General View

Analysis

Specification

Metamodeling

Generation

Adaptation

Domain

Target system

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Object-Oriented (OO) View to HL Design Processes

Object-Oriented (OO) View to HL Design Processes

Hardware Design Process

Design Operation Design Pattern

Hardware Design

Gate-Level Design System-Level Design

has

depends depends

1*

depends

is is

is is

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High-level (HL) and Low-level (LL) Design Processes

High-level (HL) and Low-level (LL) Design Processes

Higher-level Platform

Lower-level Platform

Higher-level Representationof a System

Lower-level Representationof a System

Specification view

DesignProcess

Abstraction

TransformationTools

Implementation view

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UML Class Diagrams: Graphical Notation

UML Class Diagrams: Graphical Notation

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Object-Oriented (OO) View to HL HW Design Processes: TaxonomyObject-Oriented (OO) View to HL

HW Design Processes: Taxonomy Basic Operations:

Refinement, Widening Narrowing, Containment Logical Composition, Physical Composition

Design Patterns (processes) as a specific combination of Basic Operations: Wrapping, Specialization Composition, Recursive Composition

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Example 1: RefinementExample 1: Refinement

Interface class is given in italic

Refinement (HW domain) = Realization (SW domain)

entity A is port( x, y : in bit;

z : out bit);end A;

architecture B of A is begin z <= x and y;end B;

entity A is port( x, y : in bit;

z : out bit);end A;

architecture B of A is begin z <= x and y;end B;

A

B

VHDLUML

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Example 2: WideningExample 2: Widening

Widening (HW domain) = Inheritance (SW domain)

Narrowing (HW domain) = inversion of Widening (HW domain)

-- A is a counter without the reset signalentity A is port ( clk : in bit;

count : out natural);end A;-- There should be an architecture of A

-- B is a counter with the reset signalentity B is port( clk, reset : in bit;

count : out natural);end B;-- There should be an architecture of B

A

B

VHDLUML

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Example 4: ContainmentExample 4: Containment

Containment (HW domain) = Composition (SW domain)

-- There should be entity C of architecture Aarchithecture A of C is component B port ( ... … ) ; end component B;… …begin… … p1: B port map ( ... ... );… …end A;

A

B

VHDLUML

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Example 5: Logical CompositionExample 5: Logical Composition

Logical Composition (HW domain) = Multiple Inheritance (SW domain)

entity A is port( X1, X2 : in bit;

Y : out bit);end A;

entity B is port( X3, X4 : in bit;

Z : out bit);end B;

entity C is port( X1, X2, X3, X4 : in bit;

Y, Z : out bit);end C;

A

C

B

VHDLUML

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Example 6: Physical CompositionExample 6: Physical Composition

Physical Composition (HW domain) = Composition (SW domain)

-- There should be entity AI-- of architecture Aarchithecture A of AI is component B port ( ... … ) ; end component B; component C port ( ... … ) ; end component C;… …begin … … p1: B port map ( ... ... ); p2: C port map ( ... ... ); … …end A;

A

B C

VHDLUML

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Wrapping Design ProcessWrapping Design Process

IP

WrapperModel

Wrapper

IPModel

Handshake wrapper

Data_inIP

HandshakeFSM

Req Ack

Data_in

Data_outReset

Clock

En_data

Evnto

For details, and VHDL code see http://soften.ktu.lt/~stuik/dac03/

Wrapping Design Process (HW domain) Decorator Design Pattern (SW domain)

Block diagramUML

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Metamodel and Transformation from UML to VHDL (1)


UML Interface = VHDL Entity

Interface1

+attributes

-- VHDL entity corresponds to UML interfaceENTITY Interface1 IS PORT (-- public attributes are used as VHDL ports );END Interface1;

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UML Inheritance VHDL abstraction

Inheritance (widening) is implemented using the metaprogramming techniques

Interface2

+attributes

Interface1

+attributes-- VHDL entity corresponds to UML interfaceENTITY Interface1 IS PORT (-- public attributes are used as VHDL ports );END Interface1;

ENTITY Interface2 IS PORT ( --Interface2 inherits some ports from Interface1 --Interface2 declares some new ports );END Interface2;

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UML Realization = Refinement (VHDL entity-architecture)

Class

-attributes

+methods()

Interface2

+attributes

realization

-- VHDL architecture corresponds to UML classARCHITECTURE Class OF Interface2 IS-- Class provides an implementation or refinement-- for Interface2

-- private attributes are used as VHDL signals BEGIN-- processes are described using UML class methods

method: PROCESS() BEGIN ... END PROCESS;

END Class;

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UML Composition = HW Containment (VHDL Port map)

Class

-attributes

+methods()

Interface3

+attributes

composition

ARCHITECTURE Class OF Interface2 IS COMPONENT Interface3 IS PORT (…, … ); END COMPONENT Interface3 ;

-- Private attributes are implemented-- through local signals

BEGINmethod: PROCESS()

BEGIN ... END PROCESS;

-- Class contains component Interface3p1: Interface3 PORT MAP ( ... );

END Class;

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What Is a Design Process?What Is a Design Process?

Design Process (DP) is:

More than a simple design pattern A domain-specific generative process A pattern that includes

– documentation (well-proven models, natural language descriptions, UML diagrams), which describes a design solution,

– domain code components, and

– tools (parsers, generators, etc.), which implement the solution

For properties of DPs (see paper)

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Detailed Design Flow & Automatic Generation of Instances in VHDL

Detailed Design Flow & Automatic Generation of Instances in VHDL

UMLStudio

translationUML model(class diagram)

PragScriptinterpreter

script fortranslationinto VHDL

UML metamodel(mapping)

VHDLmodel(s)

(structural)

domain knowledge

designproblem

parameters

scripting

Meta-specifications

(Java + VHDL)Java

processor

VHDLparser

parameters

Wrapperpattern

soft IP(VHDL)

thirdparty

well-provenmodel(s)

specification

generation VHDLmodel(s)

(behavioral)

Targetsystem

(VHDL)

AST

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Experimental ApprovalExperimental Approval Design Problems very close to the Real World Design

Problems we have solved:

IP Communication Problems Based on HandShake Model Based on FIFO Communication Model

Reliable Components (sub-systems, IPs) based on TRM Based on SPACE redundancy Based on DATA redundancy Based on TIME redundancy

Third-party Soft IPs: Freely available the coarse-grained components in VHDL (Free-6502 core, DRAGONFLY core, AX8 core, i8051 micro-controller, etc.)

Important note: All above stated design problems can be specified using the same PD- WRAPPER DESIGN PATTERN

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Evaluation of the Approach at the Design Process Level

Evaluation of the Approach at the Design Process Level

HW Design Processes (DPs) reside within some framework such as Platform-Based Design

HW designers conceive DPs usually intuitively (on previous knowledge and design experience basis)

In our view, DP is an abstraction (model) and it can be treated at different levels of abstractions

A HW DP not always matches to the SW DP (Patterns) Perhaps (our vision) HW DPs are richer than SW

DPs The same DP can be expressed using different

relationships

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Evaluation of the Approach at the Specification Level

Evaluation of the Approach at the Specification Level

Advantages of using UML for HW design: Graphical, OO, standard, well-documented, serious efforts

for applying in HW domain now, may serve for converging SW/HW design

High level specification (abstraction) of a designed system Soft IP reusability, adaptability, maintainability for reuse

Difficulties of using UML for HW design relate with: Specification of interconnections between components,

generic domain functionality Model validation, increased initial development time Relationship UML /non-OO HDL is not well-understood yet Expressiveness of UML for HW DP is not enough A little maturity in usage of UML for HW design Some problems with metamodel (UML subset/VHDL subset)

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General Evaluation of the Proposed Approach

General Evaluation of the Proposed Approach

Several problems are still left to be solved: How to select a HDL to implement the OO

model of a system? SystemC (an OO HDL) is better for HW modeling,

HW/SW co-simulation and IP reuse VHDL (not an OO HDL) is better for optimization and

synthesis Which specification method is better for HW

design: block-based or OO? Block diagrams are more common for HW

designers. They are more straightforward and are oriented at interconnecting components

UML class diagrams are more intuitive and oriented at reusing and customizing components

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SUMMARY & CONCLUSIONSUMMARY & CONCLUSION

We have shown that High-level Abstractions play a key role in System-Level Design

We have introduced and discussed 3 types of Abstractions for System-Level Design: Design Process as a higher-level (or meta) model UML for Specification and Implementation of the model MetaProgramming for generic Specification (partially)

We have (1) introduced taxonomy of UML- based Design Processes at two levels: Operations and Design Patterns, (2) discussed Design Flow based on MetaModel (UML-VHDL) and its implementation using UMLStudio Tools, and (3) evaluated the proposed methodology

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Application of UML for Hardware Design Based on

Design Process Model

Application of UML for Hardware Design Based on

Design Process Model

Thank You for Your attention !

http://soften.ktu.lt/~stuik/group/

Application of UML for Hardware Design Based on Design Process Model

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