명함 붙이는 곳 2007년 8월 졸업 공학석사 박보현 [1] S. J. Hong, B-H. Park, D.S. Seo, and C.-R. Ryu, “Characterisation of lead free solderability of immersion Sn finish on PWBs using wetting balance technique,” Surface Engineering, Vol. 24, No. 5, pp. 337-340, 2008. [2] B-H. Park, H. Oh, S. Hong, and S.J. Hong, “Analysis of Surface Roughness of Immersion Sn Plating Film via Micro Etch Process,” Advanced Materials Research, Vols. 26-28, pp. 425-428, 2007. 발표논문 및 연구성과 주어진 상황을 불평하지 않고 꾸준히 노력하는 엔지니어가 되었으면 합 니다. 당장의 이익을 위해 갈팡질팡 하기 보다는 미래에 나타날 기회를 위해 앞으로 나아간다면 요령으로 얻은 한번의 기회보다 더 많은 기회가 주어질 것입니다. 단순한 테크니션이 아닌 문제를 찾아서 해결하는 엔지 니어가 될 수 있도록 노력하세요. 후배를 위한 한마디 Analysis of Surface Immersion Sn Plated Film after Micro Etch Process Current electronic components industry is moving toward multi function, smaller size and lead (Pb) free due to the restriction of hazardous substances (RoHS) policy. RoHS boosts the study Sn, SnCu, and SnAg instead of SnPb micro-joining application in microelectronic packaging. However, there include complex and hard problems that lead-free materials cannot be used in manufacturing systems any more due to the RoHS. Immersion Sn plating is a method of pure Sn coating. Previously many studies for immersion Sn plating has only focused on plating process itself to remove whisker, improve the quality of the plating solution and improve surface property of plated Sn film. Micro etch process was not focused even though micro etch process can affect the roughness of plated film. Utilizing statistical methods, a predictive modeling method for Sn plated film and after micro etch w.r.t. roughness of Sn plated film and wettability is suggested. In order to perform the experiment, statistical design of experiment (DOE) was employed for an economical experimental scheme. As a result, we confirmed the trend of Sn plating process as well as correlation of film roughness after micro etch with Sn plated surface. 명함 붙이는 곳 2008년 2월 졸업 공학석사 이성준 [1] S. Lee, A. Pandey, D. Kim, A. Rohatgi, G. May, S.J. Hong, S. Han, “Characterization and Optimization of the Contact Formation for High-Performance Silicon Solar Cells,” ISNN 2007, LNCS Part III, Vol. 4493, pp. 246-251, 2007. [2] S. Lee, S. Jung, S. Moon, S.J. Hong, and S. Han, “Characterization of Contact Formation Process for High Efficient Solar Cell Using Design of Experiment (DOE),”Material Science Forum, Vol. 580- 582, pp. 197-200, 2007. 발표논문 및 연구성과 Carpe Diem! 영화 [죽은 시인의 사회]에서 키팅 선생이 했던 명대사가 제가 사회 생 활을 하기 전 학부/연구실 생활에 있어서 현재에 더욱 충실하게 임할 수 있었던 기 폭제가 되었습니다. 여러분도 언젠가 돌아올 그 날을 상상하며 현재의 자기 자신이 할 수 있는 모든 것을 총동원하여 쏟아 부어 젊은 날을 결코 헛되이 만들지 말고 잘 활용하였으면 합니다. 소중한 여러분의 시간을... 후배를 위한 한마디 Microstructure Characterization of TiO 2 Photoelectrode for dye-sensitized Solar Cell Using Design of Experiment Nanocrystalline dye-sensitized solar cell (DSC), known as the Crätzel solar cell has emerged as a powerful alternative of photovoltaic device based on broad-band absorption of light by tailor made organometallic dye molecules dispersed on a high surface of TiO2. The objective of the DSC research is to fabricate cost-effective and nanocrystalline electrodes have been investigated extensively as a key material for DSC. To increase cell efficiency, statistical design of experiment (DOE) is applied to characterize fabrication process of DSC. Furthermore, the use of DOE allowed quantification and ranking of the importance of the factors relative to one another for each property studied. By using statistical methodology, cell efficiency can be improved with finite controllable process parameters. Application of DOE in this work is applicable to other fabrication processes of DSC. 2008년 2월 졸업 공학석사 안종환 [1] J. Ahn, T. Kang, W. Lim, S. Han, H. Kim, and S.J Hong, “RepTor: An Intelligent Hybrid Neural Network Based Recipe Generator for Semiconductor Process Modeling and Characterization,”IEEE 6 th NISS, pp. 1118-1123, 2009. [2] 안종환, 이석준, 김이철, 홍상진, “PCB 제조공정을 위한 화학약품 용 액의 실시간 모니터링 시스템,”한국전기전자재료학회 논문지, 21권 5호, pp. 397-401, 2008. 발표논문 및 연구성과 처음엔 아무것도 모르고 내가 갖고 있는 능력이 큰 줄만 알았는데 교수 님의 지도 덕분에 많은 것을 깨닫게 되었습니다. 힘들다고 피하면 더 큰 어려움이 온다는 것을 배웠습니다. 내가 가질 수 있는 것을 위해 공부하 기 보다는 내가 남기고 갈 수 있는 것을 위한 시간을 보낼 수 있는 사람 이 됩시다. 후배를 위한 한마디 Recipe Optimizer for Semiconductor Manufacturing An intelligent hybrid neural network based recipe-generator is presented as a convenient tool for process optimization typically aiming highly-nonlinear plasma process in semiconductor manufacturing. As the wafer size continuously expanding up to 300mm in current high-volume manufacturing (even forecasting 450mm in 2012), fast and convenient process settlement cannot be over emphasized to meet the time-to-market of the newly developed products. In this paper, we suggest a recipe generator based on neural network and particle swamp optimization, nominally RepTor, to help minimizing material cost for process setup and maximizing accuracy of process modeling. It has a semi-hybrid neural network modeling feature for the prediction of muti-input multi-output (MIMO) process data, which is to be used for derivation phenomenological process models based on unknown process chemistry and physics. RepTor is, then, verified using SiO 2 deposition process for modeling and predicting the wafer geometry in conjunction with tool parameter. We have convinced the capability of the suggested recipe generator, and it provides a good starting point for further fine tuning of process optimization. 명함 붙이는 곳 2008년 2월 졸업 공학석사 김희연 [1] H. Kim, D.S. Seo, and S.J. Hong, “Failure Mechanism and Effect Analysis (FMEA) of Tombstone Defect in Flexible Printed Circuit Bo ard Assembly Process,” Microelectronic Engineering, 2009 (Submit ted). [2] H. Kim, S. Han, S. Hong, and S.J. Hong, “Statistical Process Monitoring System for SMT Industry using Automatic Optical Inspection System,” Material Science Forum, Vol. 580-582, pp. 561-564, 2008. 발표논문 및 연구성과 때로는 기쁘고 때로는 힘들어도 여러분들과 함께 있어서 행복했습니다. 작지만 행복한 우리들의 미래를 위한 발걸음을 시작하세요. 파이팅! 후배를 위한 한마디 Failure Modes & Effects Analysis (FMEA) of Tombstone Defect in Flexible Printed Circuit Board Assembly Process Continued development of newer technology cannot substitute all the existing technology, and the role of SMT passives assembly cannot be neglected for successful PCB assembly. It is true that fine-pitch BGA and CSP are lay out with conventional SMT passives, and assembly defects of SMT passives takes a good portion of the total defect per board in current board level assembly. Tombstone (or Manhattan) phenomenon is called when the chip component is raised and detached from the PCB land at one side while the remaining is bonded to the other land for chip assembly. Suggested process variables that contribute to tombstone defect are land design, component and board oxidation, solder paste, stencil design, screen printing, chip-mounting, and reflow. We have defined a number of potential process variables that contribute to tombstone defect and investigated their correlation with respect to tombstone defect employing statistical designed experiment. 명함 붙이는 곳 2008년 2월 졸업 공학석사 황종하 [1] J. Hwang and S. Hong, “Performance Optimization of HDP-CVD with Multiple Responses using Response Surface Methodology (RSM),” Journal of Process Control (in preparation), 2009. [2] J. Hwang and S.J Hong, “Process Characterization for Undensified Phosphosilicate Glass CMP using Design of Experiment,” KIEEME (in review) 2009. [3] K. H. Ryu, J. Hwang, D.S. Seo, and S.J. Hong, “Optimized Process Design of High Density Plasma-Chemical Vapor Deposition of Silicon Oxide Film,” 28 th Int. Conf. Phenomena in Ionized Gases, 426-429, 2007. 발표논문 및 연구성과 목표를 정하고, 도전하라!!! 후배를 위한 한마디 Performance Optimization of HDP-CVD with Multiple Responses using Response Surface Methodology (RSM) Performance optimization plays a crucial role in the process design of semiconductor manufacturing. Due to the ubiquitous complexity and nonlinearity of plasma process, the process characterization and optimization for high density plasma-chemical vapor deposition (HDP- CVD) for the desire to achieve rigorous production goals and achieve the best possible efficient fabrication is the key to success in current semiconductor manufacturing industry. Utilizing statistical methods of response surface methodology (RSM), this thesis investigates three steps for the optimization: 1) first-order model or screening experiment; 2) path of steepest ascent (PSA); and 3) second-order model. It is proposed that the predictive modeling and analysis for characterizing HDP-CVD process with respect to responses of deposition rate (A/sec) and within wafer uniformity (%) are performed. A 2 5-1 fractional factorial design with 3 center points were employed to characterize the process, in which the variables that were varied include a top and bottom RF power, top and bottom SiH 4 and O 2 . Three major variables, such as top RF power, top and bottom SiH 4 were chosen for the next steps through fitting the first-order models. To compute a path of steepest ascent (PSA), the weighting factors of 0.2 and 0.8 were added to the response of deposition rate and uniformity, respectively. By the PSA with k=3, Box-Bhenken Design (BBD) was employed for the purpose of which is to optimize the process. Finally, process performance optimization is generated to simultaneously satisfy the weighted multiple responses of interest using performance index (PI) which was calculated by the similar method with PSA. By the PI method, we can select the best recipe including significant variable terms. 명함 붙이는 곳 2009년 2월 졸업 공학석사 김광범 [1] G. Kim, D.S. Seo, W. Hur, S.J. Hong, “Statistical Modeling of Ion En ergy measured with Non-Invasive Ion Energy Analyzer (NIEA) from Reactive Ion Etching of Au films,” JKPS (Accepted) [2] T. Kang, G. Kim, I. Cho, D.S. Seo, and S.J. Hong, “Process Optimization of CF 4 /Ar plasma etching of Au using I-optimal design, Thin Solid Films, Vol. 517, pp. 3919-3922, 2009. [3] G. Kim, C. Park, D.S. Seo, and S.J. Hong, “Delamination Analysis of Low-Temperature Processed SU-8 Photoresist for MEMS Device Fabrication,” Key Engineering Materials, Vol. 345-346, pp. 1397- 1400, 2007. 발표논문 및 연구성과 영어공부 열심히 하세요. 저는 영어로 인한 맘고생, 몸고생이 심했지만 그래도 건너뛸 수 없는 것이 영어더군요. 전공은 연구실 생활하면 자연스 럽게 배우게 됩니다. 후배를 위한 한마디 Optimization of Au (gold) Etching by Fluoride Gases Plasma Using Statistical Method Reactive ion etching of Au has performed with CF4/Ar gases, and process optimization method is suggested using statistically established process model. I-Optimal design was employed to set up the etch experiment with operating parameters, namely, gas composition, RF power and chamber pressure, and analysis of it was performed on etch rate, selectivity, and profile, individually. In addition, the process optimization including all three responses of interest simultaneously is provided. Suggested optimization considers three responses of interests simultaneously, it is crucial in the process development and optimization for fast ramping up for high volume manufacturing. The additional objective of this study is to develop plasma etching process of Au pattering through statistical modeling employing non-invasive ion energy analyzer (NIEA) data. A series of plasma etching was performed followed by the design of experiment, and ANOVA analysis and response surface analysis, regarding the factors of RF power, Pressure, CF4, and Ar, were provided. We have noticed that measured ion energy during Au etch is directly related with RF power, and etch rate is also positively proportional to the measured ion energy. 2009년 2월 졸업 공학석사 박진수 [1] J.S. Park, D.S. Seo, W, hur, and S.J. Hong, “Statistical Analysis of E mission Intensity for Silicon Dioxide Inductively Coupled Plasma Etchi ng Using Optical Emission Spectroscopy Data,” Journal of Korean Ph ysics Society, 2009. (Accepted) [2] J.S. Park and S.J. Hong, “Statistical Analysis of Emission Intensity for Generated Oxygen Plasma using Optical Emission Spectroscopy,” EU-Japan JSPP, 2007. 발표논문 및 연구성과 End-point Detection Method of Plasma Etching Process Using O ptical Emission Spectroscopy and RGB Sensor Adequate determination of the end point of a plasma-etching proce- ss is very important for integrated circuit fabrication. Etch endpoint detection is practiced with optical emission spectroscopy data, and a new way of endpoint detection is proposed using chromatic RGB sensor data. For the etching of a silicon dioxide film with CF 4 plasma using a reactive ion etching (RIE) system, this method yields a reproducible and reliable signal, which was successfully demonstrated to detect the end point for several wafers through the experiment. Diagnostics are needed for two different roles in processing plasmas; characterization and control. Favored diagnostics for characterization include optical emission spectroscopy for monitoring etch rate and selectivity in real time fashion. Real time control requires sensors of the plasma process that are utilized for in-situ diagnostics. In order to determine etch endpoint in time order, we used to optical emission spectroscopy (OES) and RGB sensor. Through the analysis of OES data in statistical way of average and standard deviation, we could successively confirm etch endpoint detection. However, in case of RGB sensor data, it is not clearly changed for etch endpoint. So, we can only expect that RGB sensor is able to measure process change for endpoint detection. Do not hesitate to do it! 여러분이 하고 있는 일, 앞으로 하고자 하는 일들 앞 에는 많은 장애물 들이 있을 것입니다. 망설이고 주저한다면 절대 해낼 수 없 습니다. 부딪히고 고민하고 또 노력하세요. 성공한 사람들의 가장 큰 비결은 “실패를 통한 경험”이라는 것을 명심하시고 도전하시기 바랍니다. 후배를 위한 한마디 2009년 2월 졸업 공학석사 문세영 [1] S. Moon, C.W. Cha, and S.J. Hong, “Optimization of High Q-Factor Embedded Inductors in LTCC based on Design of Experiments (DOE) Technique,” MINT-MIS 2007 and TSMMW, pp. 101-104, 2007. [2] S. Lee, S. Jung, S. Moon, S.J. Hong, and S. Han, “Characterization of Contact Formation Process for High Efficient Solar Cell Using Design of Experiment (DOE),”Material Science Forum, Vol. 580- 582, pp. 197-200, 2007. 발표논문 및 연구성과 무조건 하는 겁니다! 한다면 하는 것이고, 어려우면 그냥 하면 되는 겁니 다. 우연히 선배의 연구를 도와주다가 기회가 되어 그 분야로 취업을 하 게 되었습니다. 작지만 몸으로 한 경험만큼 소중한 보상은 없었습니다. 후배를 위한 한마디 Modeling and Optimization of The magnetic Coupled Resonant Circuit Using Design of Experiment (DOE) The reading range between aggregator and tag is a crucial factor for the low frequency radio frequency identification (RFID) system to broaden the applications. The reading range of the magnetic coupled communications is determined by magnetic coupling efficiency between the reader and tag. The most important factor to maximize the reading range between aggregator and tag is Q-factor of the inductor. However, there is a trade-off between bandwidth and reading range. This is the reason to optimize and model the Q-factor using proper modeling methodology with design of experiment (DOE) analysis. In this study, we used the DOE to obtain fast and accurate methodology for the design of Q-factor of the LC resonant circuit in the front-end of the RFID system. Through this research, arduous design steps in determining individual values of the LC resonant antenna circuit have been simplified. 2009년 2월 졸업 공학석사 홍세환 [1] S. Hong and S.J. Hong “Real-time Process Diagnostic Algorithm Using Optical Emission Spectroscopy,” IEEE Transactions on Semiconductor Manufacturing (in preparation) [2] S. Hong, J. Park, W. Choi, and S.J. Hong, “Atmospheric Plasma Treatment on Copper for Organic Cleaning in Copper Electroplating Process: Towards Microelectronics Packaging Industry,” Vol. 10, No. 3, pp. 71-74, 2009. 발표논문 및 연구성과 석사과정 동안 별로 중요하지 않다고 생각했던 일을 취업을 해서도 계속 하고 있습니다. 프로그래밍을 좋아해서 한가지만 하려고 했었는데 시간 이 지날 수록 수학과 반도체공정 공부를 게을리 한 것이 후회 됩니다. 후 회하지 않는 미래를 위해서 열심히 공부하세요. 후배를 위한 한마디 Real-time Process Diagnostic Algorithm Using Optical Emission Spectroscopy In semiconductor industry, technology of yield enhancement is being researched more than before. Critical dimension (CD) size is coming to limit of physical meaning. Wafer size of chip manufacturing is bigger than the past and this will be larger size in shorter time. These state boost development of yield enhancement technology. This thesis represents software algorithm that can be applied to plasma process. Representing plasma processes are plasma reactive ion etching (RIE), plasma enhanced chemical vapor deposition (PECVD), and others. Three algorithms are presented and each was designed for process monitoring and fault detection application. Algorithms were based on optical emission spectroscopy (OES), and the proposed three algorithms are; 1) integral, 2) triangle, and 3) standard deviation algorithm. First algorithm calculates integral operation on real-time spectrum area, second utilizes triangle to monitor plasma process variation, and the third employs standard deviation model on real-time fault detection. To verify these algorithms, operating software program was developed in C # , and it was tested under actual plasma etch experiments. 명함 붙이는 곳 2010년 2월 졸업 공학석사 강태윤 [1] T. Kang, G. Kim, I. Cho, D. Seo, and S.J. Hong “Process optimization of CF4/Ar plasma etching of Au using I-optimal design,”Thin Solid Films, Vol. 517, pp. 3919-3922, 2009. [2] T. Kang, C. Park, W. Seo, G. Kim, S. Hong, “Reactive Ion Etching of WPR for Via Formation in High Density 3-D Chip Stacking Technology, Vol. 55, No. 5, pp. 1877-1881, 2008. 발표논문 및 연구성과 선배의 연구에 대한 관심을 갖고 실험에 함께 참여하면서 내가 알게 된 것이 많아졌다. 장비와 공정에 대한 지식이 좋은 연구논문의 밑거름이 된 것 같다. 다른 이의 실험을 돕는 만큼 나에게 더 큰 것으로 돌아왔다. 후배를 위한 한마디 Virtual Metrology on Silicon Oxide Etch Rate Using Optical Emission Spectroscopy Data Over the past few years, semiconductor manufacturing are investigating a software based process controlling scheme known as virtual metrology (VM). By virtue of prediction, VM enables wafer- level control (or even down to die level), reduce within-lot variability, and increases process capability, C pk . In this research, we have practiced VM on oxide etch rate with optical emission spectroscopy data acquired in-situ while the process parameters are simultaneously correlated. To build process model of oxide via etching, we first performed a series of etch runs according to the statistically designed experiment followed by design of experiment (DOE). Established process model is verified with additional experiments that reside within the process space, but not the same recipe used in the model construction. The accuracy of the proposed VM is still need to be developed in order to successfully replace the existing metrology, but it is no doubt that VM can support engineering decision of “Go or Not-go” in the consecutive processing steps. 명함 붙이는 곳 2011년 8월 졸업 공학석사 왕 리 [1] L. Wang, J. H. Ahn, H. J. Lee, S. Hong, “A New Approach of Intensity Prediction in Copper Electroplating Monitoring Using Hybrid HSMM and ANN,”Korea Vacuum Society Winter Conference, 2010. [2] S. Hong, L. Wang, D. Seo, and T.-S. Yoon, “In-situ Optical Monitoring of Electrochemical Copper Deposition Process for Semiconductor Interconnection Technology,” Trans. Electrical and Electronics Materials, Vol. 13, No. 2, pp. 78-84, 2012. 발표논문 및 연구성과 아는 만큼 답을 할 수 있고, 직접 해 본 만큼 자신감을 갖게 된다. 후배를 위한 한마디 Real-time Copper Electrochemical Deposition Process Monitoring and Diagnosis for Semiconductor Interconnect As the semiconductor manufacturing technology develops, copper via filling is considered to be the core of 3-D microelectronics interconnection technology. Copper (111) compact structure is known as the desired material growth orientation in favor of the low electrical resistivity, high resistance to electro-migration, and stress-migration requirement in the interconnection technology. Electro-chemically deposited copper plays more and more important role in copper metallization as well as through silicon via (TSV) in 3- D packaging for depositing high quality interconnections onto wafers. In this thesis, we suggest several optical measurements to monitor copper electroplating solution: (1) RGB sensor to monitor color changes in copper sulfate solution; (2) optical transmission spectroscopy (OTS) to detect optical signal changes in UV/VIS region; and (3) near-infrared (NIR) spectroscopy for NIR/IR region. The result is compared with traditional pH sensor, it can be seen that optical sensor are more sensitive than pH sensor. Finally, obtained the conclusion is optical sensor can be used to do the real-time monitoring in electrochemical deposition experiment. 명함 붙이는 곳 2012년 2월 졸업 공학석사 손동주 [1] D. Son, Y. Ji, Y. Jeon, D. Soh, and S. Hong, “Defective Surface Analysis of Aluminum Bonding Pads for Au Wire Bonding,” KIEEME Winter Conference, 2009. [2] S. Hong and D. Son, “Defective Surface Analysis on Au/Al Wire Bonding for Multichip Stacking NAND Flash Memory Package,” ICMAP 2012. 발표논문 및 연구성과 처음엔 반도체에 관심을 갖게 되었고, 휴학을 하면서 Embedded SW 개 발자가 될 꿈이 있었고, 대학원 진학 후에 패키징 공부를 하면서, 반도체 관련 기업 M&A 컨설턴트의 경험을 갖게 되었다. 모든 것이 하나였다. 후배를 위한 한마디 Surface Analysis on Weakly Bonded Pads in Wire- bonded SDRAM and NAND Flash Memory Multi-chip Stacking Technology Despite the emersion of advanced chip bonding technologies, gold wire-bonded 3-dimensional chip stacking is still in good use for multi-chip package (MCP) in semiconductor mobile chip memory (SDRAM+NAND) assembly process. Although gold wire bonding technique is mature in semiconductor manufacturing, but weakly bonded wires in mobile chip memory assembly can jeopardize the reliability of final product. In this paper, weakly bonded or failed of aluminum bonding pads are analyzed using X-ray photoelectron spectroscopy (XPS), Auger electron Spectroscopy (AES), and energy dispersive X-ray analysis (EDS) to investigate the potential contaminants on bond pad, and the source of contaminants are related to the dry etching process in the front-end manufacturing step. Fluorinated plasma exposed bonding pads in over glass opening (OVGL) process presents significant evidence of fluorine on the bond pad in the form of AlF x . Surface analysis of the contaminated aluminum layer revealed the presence of fluorinated compounds AlOF x , Al(OF)x, Al(OH) x , and CF x . 명함 붙이는 곳 2012년 2월 졸업 공학석사 임우엽 [1] W. Lim, S. Park, S. Hong, “The Diagnosis of Plasma Through RGB Data Using Rough Set Theory, “Korean Vacuum Society Winder Conference, 2010. [2] S. Hong, W. Lim, T. Jeong, G. May, “Fault Detection and Classification in Plasma Etch Equipment for Semiconductor Manufacturing e-Diagnostics, “ IEEE Trans. Semi. Manufac., Vol. 25, No. 1. pp. 83-92, 2012. 발표논문 및 연구성과 앞에서 이끌고 가는 것과 뒤에서 따라 가는 것의 차이는 내가 생각한 것 보다 더 큰 차이를 가지고 있다. 믿음과 신뢰가 바탕이 되지 않으면 누구 도 앞설 수 없고 따라갈 수 없을 것이다. 후배를 위한 한마디 Fault Detection and Classification Using Dempster Shafer Thoery To prevent yield loss and maximize equipment utilization, various roles of FDC, such as detecting failures and identifying root cause of faults, have become significant. General FDC dealt with a stationary model is limited to the increases in accuracy of diagnosis. Furthermore, Analysis of tool data acquired from production equipment requires intricate systems due to its enormous size and complexity. It is the reason why the data is collected from various sensors to manage its process. False alarms and miss fault detection are frequently caused, since the data also has uncertainty. We defined these phenomena as uncertainty of equipment and model data. Dempster-Shafer theory (DST) can be a key to solve these problems. It allows for the direct representation of uncertainty of system responses, and combination rules in DST are crucial paradigms for the aggregation of information. We realized that successful fault detection and classification could be accomplished by combining various related information and by incorporating engineering expert knowledge. APLE (에이플) 2012년 2월 졸업 공학석사 김범수 [1] B. Kim, S. Chun, S. S. Han, G. May, and S. Hong, “Wavelength Selection for the Analysis of the Plasma Etch Process Using Optical Emission Spectroscopy Data,” Korea Semiconductor Conference, 2012. [2] B. Kim, and S. Hong, “Actinometric Investigaton of In-Situ Optical Emission Spectroscopy Data in SiO 2 Plasma Etch,”Trans. EEM, 2012 (Accepted). 발표논문 및 연구성과 처음엔 장비를 배우고, 공정을 배우고, OES를 배우고, 통계도 배우고… 배운 것 보다는 스스로 공부한 것이 더 많다고 생각이 되지만, 그 것이 대학원에 진학한 목적이 아닐까 라는 생각을 해 본다. 끝까지 도전할 것 입니다. 후배님들도 끝까지 도전해 보세요. 후배를 위한 한마디 Virtual Metrology for SiO 2 Plasma Etch Process Using Optical Emission Spectroscopy in semiconductor manufacturing industry, advanced process control (APC) became more important than ever before to improve the manufacturing yield and throughput. Virtual metrology (VM) in the APC is a one of key factors for realizing real-time process control process to minimize wafer-to-wafer variation. In this thesis, we have practiced VM on silicon dioxide etch rate in inductive coupled plasma-reactive ion etching (ICP-RIE) using both process parameters and in-situ optical emission spectroscopy (OES) data . OES is often used for the analysis of plasma processes in real-time. We propose a useful and practical method for the selection of OES wavelengths to monitor both etchant and by-product gas species. The method is based on measuring standard deviations and correlation coefficients. To establish VM model, we employ statistical regression modeling which shows relationship between input variables and output response. We build several different models from different sets of input variances in order to enhance the modeling accuracy. Established process model is then verified with additionally augmented experiments that reside within the space of process recipe. The accuracy of the proposed VM is still need to be improved in order to successfully replace the existing metrology; however, the suggested method successfully presents a promising result in early stage of virtual metrology in semiconductor manufacturing. 명함 붙이는 곳 2012년 2월 졸업 공학석사 박수경 [1] B. Kim, S. Chun, S. S. Han, G. May, and S. Hong, “Wavelength Selection for the Analysis of the Plasma Etch Process Using Optical Emission Spectroscopy Data,” Korea Semiconductor Conference, 2012. [2] B. Kim, and S. Hong, “Actinometric Investigaton of In-Situ Optical Emission Spectroscopy Data in SiO 2 Plasma Etch,”Trans. EEM, 2012 (Accepted). 발표논문 및 연구성과 처음엔 장비를 배우고, 공정을 배우고, OES를 배우고, 통계도 배우고… 배운 것 보다는 스스로 공부한 것이 더 많다고 생각이 되지만, 그 것이 대학원에 진학한 목적이 아닐까 라는 생각을 해 본다. 후배를 위한 한마디 Virtual Metrology for SiO 2 Plasma Etch Process Using Optical Emission Spectroscopy in semiconductor manufacturing industry, advanced process control (APC) became more important than ever before to improve the manufacturing yield and throughput. Virtual metrology (VM) in the APC is a one of key factors for realizing real-time process control process to minimize wafer-to-wafer variation. In this thesis, we have practiced VM on silicon dioxide etch rate in inductive coupled plasma-reactive ion etching (ICP-RIE) using both process parameters and in-situ optical emission spectroscopy (OES) data . OES is often used for the analysis of plasma processes in real-time. We propose a useful and practical method for the selection of OES wavelengths to monitor both etchant and by-product gas species. The method is based on measuring standard deviations and correlation coefficients. To establish VM model, we employ statistical regression modeling which shows relationship between input variables and output response. We build several different models from different sets of input variances in order to enhance the modeling accuracy. Established process model is then verified with additionally augmented experiments that reside within the space of process recipe. The accuracy of the proposed VM is still need to be improved in order to successfully replace the existing metrology; however, the suggested method successfully presents a promising result in early stage of virtual metrology in semiconductor manufacturing. 명함 붙이는 곳 2012년 2월 졸업 공학석사 전상현 [1] B. Kim, S. Chun, S. S. Han, G. May, and S. Hong, “Wavelength Selection for the Analysis of the Plasma Etch Process Using Optical Emission Spectroscopy Data,” Korea Semiconductor Conference, 2012. [2] S. Chun, H. Lee, and S. Hong, “End Time Detection (ETD) of Etch Chamber Cleaning Using Optical Emission Spectroscopy (OES), 한국 반도체디스플레이장비학회 추계 학술대회, 2011. 발표논문 및 연구성과 초심은 컸지만 시간이 지날 수록 작아지는 마음을 다스릴 줄 알아야 할 것이며, 함께 일하는 것이 번거롭다는 생각에 혼자 일을 하게 되면 모든 것을 혼자 해야 하는 부담이 남는 다는 것을 알게 되었다. 후배를 위한 한마디 In-Situ MONITORING OF PLASMA INDUCED ELECTRICAL CHARGE/DISCHARGE USING OPTICAL EMISSION MONITORING TECHNIQUE Recently, the semiconductor industry is steadily developing through the integration of circuit. Etch process, the one of semiconductor manufacturing process is essential process to form the dense pattern. Furthermore, etch process is based on the plasma, and the density of plasma is changing to high density to improve the throughput and to achieve the nano-scale device. However, high density plasma (HDP) could be a damage source such as charging damage, antenna effect, physical damage. All of these damages is related with ion in the plasma. Accurate control of ion is a way to reduce the plasma damage. In this thesis, plasma damage monitoring sensor (PDMS) development is introduced. PDMS is a sensor which can detect the plasma voltage by voltage control oscillator (VCO). In addition, PECS gather the plasma status as a form of light, and detect the plasma voltage through the matching PECS data with PDMS reference data. We confirmed the relation between RF power and plasma voltage in Ar, O 2 gas. And also, the possibility to adapt this method is confirmed to analyze the relation between gas flow and plasma voltage. 명함 붙이는 곳 2012년 2월 졸업 공학석사 손승남 [1] T. Kang, G. Kim, I. Cho, D. Seo, and S.J. Hong “Process optimization of CF4/Ar plasma etching of Au using I-optimal design,”Thin Solid Films, Vol. 517, pp. 3919-3922, 2009. [2] T. Kang, C. Park, W. Seo, G. Kim, S. Hong, “Reactive Ion Etching of WPR for Via Formation in High Density 3-D Chip Stacking Technology, Vol. 55, No. 5, pp. 1877-1881, 2008. 발표논문 및 연구성과 선배의 연구에 대한 관심을 갖고 실험에 함께 참여하면서 내가 알게 된 것이 많아졌다. 장비와 공정에 대한 지식이 좋은 연구논문의 밑거름이 된 것 같다. 다른 이의 실험을 돕는 만큼 나에게 더 큰 것으로 돌아왔다. 후배를 위한 한마디 Method for Etch Profile Evaluation in Through Silicon Via (TSV) Advanced packaging technologies, such as three-dimensional (3-D) packaging and 3-D ICs can help to make heterogeneous integration, shorter interconnection, low power loss in the interconnection and etc. Through silicon vias (TSVs) which is made by Bosch and non-Bosch process are used to realize benefit of advanced packaging technologies. Once TSV is made, TSV needs to be vertical, lower under-cut and scallop. In the analysis of the cross-section image, Illusion Bowing Effect (IBE) where the etch profile can easily appears due to the cylindrical shape of TSV. Compensation Method (CM) parameter is suggested to compensate IBE. And, through the CM parameter, angle and real bowing in cross-section image can be correctly evaluated using Angle Match (AM) and Curvature Profile (CP) parameter respectively. Also, Degree of Undercut (DoU) and Degree of Scallop (DoS) parameters are suggested to evaluate undercut and scallop. AM, CP, DoU and DoS parameters can be expressed in Total Scores (TS) from 0 to 100 based on weight which can be determined by process/design engineer’s decision, allowing anyone to easily know TSV profile condition. And then, Through Uniformity parameter, overall quality of wafer which has formed the TSVs can be expressed.. 명함 붙이는 곳 2012년 8월 졸업 공학석사 한아름 [1] A. Han, S. Jeon, S.-S. Han, S. Hong, “Real-time Monitoring of Enhanced SiO 2 Etch Rate with Augmented Oxygen Using Optical Emission Spectroscopy (OES),”한국반도체디스플레이장비학회 추계 학술대회, 2011. [2] S. Hong, A. Han, T. Ha, D. Seo, “Process Monitoring of Spin-on Dielectric (SOD) Hardmask Spacer Formation for Self-Aligned Double Patterning (SADP),” ICMAP, 2012. 발표논문 및 연구성과 3.99 라는 학부학점 때문에 신입학 장학금을 받지 못한 설움에 울었고, 며칠 밤을 세워서 스스로 수행한 과제를 올게 인정받지 못해서 울었고, 많은 노력에도 불구하고 실험 결과가 원하는 대로 나오지 않아 울었고, 하지만, 그 모든 것을 성실과 끈기를 통해 웃음으로 받을 수 있었습니다. 후배를 위한 한마디 Spin-on Dielectric (SOD) Hardmask Spacer Formation for Self-Aligned Double Patterning (SADP) A variety of resolution enhancement technology has been investigated for nano-scale semiconductor device fabrication, and recent advancement in double patterning technology (DPT) employing hardmask material has emerged as a promising solution in semiconductor manufacturing. Several double patterning techniques have been investigated, such as litho-etch-litho-etch (LELE), litho-litho- etch (LLE), and self-aligned spacer double patterning. Self-aligned double pattering (SADP) which is the pattern-splitting type double patterning becomes the most suitable double patterning process due to the process capability and compatibility with concurrent CMOS process. We employed optical emission spectroscopy (OES) and IV probe, non- invasive in-situ plasma process monitoring sensors, to determine a proper time of spacer etching end point. Various size of gate structures are fabricated in the order of micrometers with aluminum on LPCVD deposited silicon nitride on 4 inches silicon wafers. Considering the university research environment, physical dimensions of the prepared sample structure may deviate from industry level double patterning geometry; however, real-time plasma process monitoring of spacer etching for SADP still conceptually holds for semiconductor manufacturing industry. 명함 붙이는 곳 2012년 8월 졸업 공학석사 문대호 [1] S. Hong, T. Ha, D. Moon, B. Kim, and C. Park, “Copper Interconnection and Flip Chip Packaging Laboratory Activity for Microelectronics Manufacturing Engineers,”Korea Vacuum Society Winter Conference, 2011. [2] S. Hong and D. Moon “Enhancing Self-Motivation on Microelectronics Engineering Education via Hands-on Fabrication of Integrated Passive Devices (IPD)” in Preparation, IEEE Trans. Eng. Edu., 2012. 발표논문 및 연구성과 관심과 애정이 있어야 장비를 배울 수 있고, 장비를 다룰 줄 알아야 공정을 할 수 있고, 공정을 할 줄 알아야 소자를 만들 수 있다. 후배를 위한 한마디 Fabrication of Integrated Passive Devices for Microelectronics 패키징 기술은 현대에 이르러 외부환경으로부터 소자를 보호하는 전통 적인 역할에서 그치지 않고 제품의 성능을 향상시킬 수 있는 주요한 기 술로 발전해왔다. 특히 System on Package(SoP) 기술이 현재 각광을 받 고 있다. SoP기술의 발전에 따라 제품의 소형화, 경량화를 이루면서 동 시에 고성능의 제품의 개발이 시장의 트렌드에 맞추어 빠르게 대응 할 수 있었다. 특히 무선통신분야에서 SoP기술이 두드러지게 활용되어지고 있다. 본 연구에서는 무선통신분야에서 활용되어지는 SoP에 관한 것이 다. 그중에서도 전체 시스템의 상당수를 차지하고 있는 수동소자의 집적 화를 통해 보다 제품의 소형화와 고성능을 이룰 수 있도록 기존의 세라 믹으로 구성된 수동소자를 대체할 수 있는 실리콘 프로세스 기반의 집 적수동소자를 제조하는 연구이다. 디자인 된 마스크를 기반으로 반도체 공정을 통하여 집적수동소자를 제조를 하였다. 제조된 수동소자의 특성 을 확인하기 위하여 LCR미터의 측정과 SEM이미지를 통해서 확인하였다. 그 결과 Interdigitated capacitor의 구조에서 Metal간의 거리에 따른 capacitance변화를 확인하였으며 Spiral inductor는 코일의 회전수에 의 한 Inductance는 확인하였지만 Metal이 차지하는 면적 비율에 대한 경 향은 확인 할 수 없었다. 끝으로 SEM이미지를 통해 실리콘웨이퍼에 하 나의 다이안에 총 25개의 집적수동소자를 제조 한 것을 확인하였다. 명함 붙이는 곳 2013년 2월 졸업 공학석사 이호재 [1] A 발표논문 및 연구성과 나도 했다. 목표를 가지고 한번에 하나씩 도전하길 바랍니다. 후배를 위한 한마디 [1] H.J. Lee, D. George O. Park, and S. Hong, “In-Situ Dry- cleaning Monitoring of Amorphous Carbon Layer (ACL) Coated Chamber,”제 42회 한국진공학회 동계학술대회 2011. [2] H.J. Lee, D. Seo, G. S. May, and S. Hong, “Use of In- situ Optical Emission Spectroscopy for Leak Fault Detection and Classification in Plasma Etching,”Journal of Semiconductor Technology and Science, Vol 13, No. 4, pp. 395-401, 2013. In-Situ Plasma Process Monitoring using Optical Emission Spectroscopy (OES) Sensor based monitoring in the APC is a one of key for real-time process monitoring and control process. In this thesis, optical emission spectroscopy (OES) was employed for sensor based AEC/APC in semiconductor manufacturing process. OES is widely used for the analysis of plasma processes in real-time. We propose an application of plasma chamber cleaning monitoring and endpoint detection (EPD) in Bosch etch process for through silicon via (TSV). OES data is including thousands information. But high dimensional OES data require advanced algorism for reducing dimension of OES data. Therefore, we implemented principle component analysis (PCA) for decreasing dimension of data. Through the generated PCA signals, chamber cleaning monitoring and Bosch process EPD was performed. As a result, in chamber cleaning monitoring application, we acquired cleaning time reduction of 53% through chamber cleaning monitoring using OES. In Bosch etch process EPD application, we detected etch end step in generated EPD signal. Through that result, we confirmed that possibility of sensor based monitoring applications able to contribute to goal of AEC/APC. 명함 붙이는 곳 2013년 2월 졸업 공학석사 김혜정 [1] H. Kim, S. H. Chun J. Lee, and S. Hong “A Preliminary Research on Optical In-Situ Monitoring of RF Plasma Induced Ion Current Using Optical Plasma Monitoring System (OPMS),”한국진공학회 동계학술 대회, 2012. 발표논문 및 연구성과 수업시간에 뒷자리에 조용히 앉아 있었던 저에게 공부를 할 기회가 있을 것을 상상하지 못했습니다. 하지만 작은 것 부터 배워가다 보니, 중소기 업과 산학협력을 한 결과 외국계 반도체 장비기업에 취업하게 되었습니 다. 여러분도 작은 것에 만족하면서 내실을 기헤서 좋은 기회를 잡으세요. 후배를 위한 한마디 Savitzky-Golay 필터를 이용한 플라즈마 공정 진단 및 아크 검출 플라즈마 공정에서 발생하는 플라즈마 이상 방전, 즉 아크(Arc) 현상 은 공정의 제어에서 중요한 요인 중 하나이다. 전기적 충격으로 공정 대상인 웨이퍼에 심각한 손상을 일으키고 챔버에 발생한 아크로 인해 파티클이 발생하여 오염을 초래함으로써 공정 오류를 일으키는 원인이 되기 때문이다. 아크로 인해 손상되는 다이(Die)의 수가 웨이퍼 크기 에 비례하여 증가하는 점도 웨이퍼 대구경화 시 발생될 수 있는 주요 한 문제점 중 하나로 지적되고 있다. 본 연구에서는 플라즈마 공정의 모니터링을 통해 플라즈마의 상태를 진단하고 특징 추출이 가능한 평활화 필터인 Savitzky-Golay 필터 알고리즘을 이용해 가공 된 데이터를 분석 및 비교하여 아크의 유무를 판단하였다. 공정 모니터링 및 데이터 수집은 장비와 공정에 영향을 미치지 않는 비침투식 고속 광센서인 Optical Plasma Monitoring System (OPMS) 센서를 통해 진행 되었으며 Savitzky-Golay 필터 알고리즘을 통한 데이터 결과는 공정의 특성과 조건을 반영하여 비교 및 분석되었다. 실험 결과, 데이터에 잡음이 포함되었거나 플라즈마의 특성이 불분명하게 나타났던 원래의 데이터를 Savitzky-Golay 필터 알고리즘으로 가공했을 때 플라즈마 양상 및 특성의 구별이 용이하였 으며 육안으로 확인하기 어려웠던 아크 현상에 대해 추정하는 것이 가 능했다. 명함 붙이는 곳 2013년 8월 졸업 공학석사 Javeria Nawaz 발표논문 및 연구성과 Set up your destination and Stay tuned. Prof. Hong will guide you to your goal. He was always with me when I needed his help. 후배를 위한 한마디 In-Situ Plasma Process Monitoring using Optical Emission Spectroscopy (OES) This work presents a model of Elman recurrent neural network (ERNN) for time series fault prediction and Bayesian Network based generalized framework for the diagnosis of faults in semiconductor etch equipment. The ERNN maintains a copy of previous state of the input in its context units, as well as the current state of the input. The principal component analysis (PCA) was used to reduce the feature size of the data. Derivative dynamic time warping (DDTW) method is also discussed for the synchronization of time series data set acquired from plasma etcher. For each parameter of the data, the best ERNN structure was selected and trained using Levenberg Marquardt to generate one-step-ahead prediction for 10 experimental runs. The faulty experimental runs were successfully distinguished from healthy experimental runs with one missed alarm out of ten experimental runs. For the fault diagnosis, a Bayesian Network based generalized framework is presented. [1] J. Nawaz, Z. Arshad, and S. Hong, “Recurrent Neural Network Modeling of Etch Tool Data: a Preliminary for ault Inference via Bayesian Networks,” 한국진공학회 동계학 술대회 2012. [2] J. Nawaz, Z. Arshad, and S. Hong, “Time Series Fault Prediction in Semiconductor Equipment Using Recurrent Neural Network,”Lecture Note on Computer Science, 7952, pp. 463-472, 2013. 명함 붙이는 곳 2013년 8월 졸업 공학석사 Zeeshan Ashad 발표논문 및 연구성과 Set up your destination and Stay tuned. Prof. Hong will guide you to your goal. He was always with me when I needed his help. 후배를 위한 한마디 Fault Detection and Classification in Semiconductor Etch Process using Time Series Modeling and Dempster- Shafer Theory In this research, a fault detection and classification (FDC) methodology based on seasonal autoregressive integrated moving average (SARIMA) time series models for fault detection and Dempster-Shafer theory for classification through semiconductor etch equipment data was investigated. The derivative dynamic time warping (DDTW) was employed for the synchronization of data. The models were generated using a set of data from healthy runs, and the established models were compared with the experimental runs to find the faulty runs. Using SARIMA modeling of this data 9 out of 10 runs were correctly identified as faulty and healthy runs. Also Dempster-Shafer theory was employed for the diagnosis of detected faults to find the root cause. It was found that this methodology is quite useful to detect incipient faults in semiconductor fabrication. [1] Z. Arshad, J. Nawaz, and S. Hong, “Process Fault Probability Generation va ARIMA Time Series Modeling of Etch Tool Data,” 한국진공학회 동계학술대회 2012. [2] Z. Arshad, J. Nawaz, and S. Hong, “Fault Detection in the Semiconductor Etch Process Using the Seasonal Autoregressive Integrated Moving Average Modeling,” J. Information. Process System, 7952, pp. 463-472, 2013. 명함 붙이는 곳 2013년 8월 졸업 공학석사 Zeeshan Ashad 발표논문 및 연구성과 Set up your destination and Stay tuned. Prof. Hong will guide you to your goal. He was always with me when I needed his help. 후배를 위한 한마디 Fault Detection and Classification in Semiconductor Etch Process using Time Series Modeling and Dempster- Shafer Theory In this research, a fault detection and classification (FDC) methodology based on seasonal autoregressive integrated moving average (SARIMA) time series models for fault detection and Dempster-Shafer theory for classification through semiconductor etch equipment data was investigated. The derivative dynamic time warping (DDTW) was employed for the synchronization of data. The models were generated using a set of data from healthy runs, and the established models were compared with the experimental runs to find the faulty runs. Using SARIMA modeling of this data 9 out of 10 runs were correctly identified as faulty and healthy runs. Also Dempster-Shafer theory was employed for the diagnosis of detected faults to find the root cause. It was found that this methodology is quite useful to detect incipient faults in semiconductor fabrication. [1] Z. Arshad, J. Nawaz, and S. Hong, “Process Fault Probability Generation va ARIMA Time Series Modeling of Etch Tool Data,” 한국진공학회 동계학술대회 2012. [2] Z. Arshad, J. Nawaz, and S. Hong, “Fault Detection in the Semiconductor Etch Process Using the Seasonal Autoregressive Integrated Moving Average Modeling,” J. Information. Process System, 7952, pp. 463-472, 2013.