Announcements - University of California, Berkeleybwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s04/lectures/Lectur… · Power savings for T OFF > ~100 idle cycles PMOS sleep transistor

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EE241 - Spring 2004Advanced Digital Integrated Circuits

Borivoje Nikolic

Lecture 17Low-Power Design:

Dynamic Body BiasEnergy Recovery in CMOSSOI

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Announcements

Midterm project reports due this FridayPlease post links on your project web page

Homework #3 due after the Spring break

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Class Material

Last lectureDynamic voltage scalingLeakage control

Today’s lectureDynamic body biasEnergy recovery techniquesSilicon-on-insulator

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Dynamic Body Bias

Similar concept to dynamic voltage scalingControl loop adjusts the substrate bias to meet the timing

Can be used just as runtime/sleep

Limited range of threshold adjustments (<100mV)Limited leakage reduction (<10x)No delay penalty

Can increase speed by forward bias

Energy cost of charging/discharging the substrate capacitance

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5

Dynamic Body Bias

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VTCMOS Variants

Courtesy of IEEE Press, New York. 2000

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7

Substrate Bias in VT

Kuroda, JSSC 11/96

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Dynamic Body Bias

... ...

450mVFBB

450mVFBB

VCC

VSS

PMOSbody

NMOSbody

PMOSbias

NMOSbias

PMOSbias

... ...NMOS

bias

500mVRBB

500mVRBB

VCC

VSS

PMOSbody

NMOSbody

VHIGH

VLOW

Forward body bias (FBB)

Local VCC tracking

Active mode

Reverse body bias (RBB)

Triple well needed

Idle mode

Dual-VTcore

Tschanz, ISSCC’03

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9

Substrate Bias Effect

BSTBSFTTH VVVVV 100 2 γ−≈−φγ−=

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Body Bias Layout

Sleep transistor LBGs

10Number of sleep transistor LBGs

8%Area overhead

13mmPMOS device width

30Number of ALU core LBGs

ALU core LBGs

Sleep transistor LBGsALU core LBGs

ALU

6

11

0

0.2

0.4

0.6

0.8

1

0.01 1 100 10000

1.32V75°C

Leakage Power Savings vs. Decap

Minimize capacitance on virtual VCC

Overhead: charging & discharging of virtual VCCcapacitance

Dual-VTcore

Virtual VCC1.32V, 75°C

Idle time10ns 1µs 100µs 10ms10µsN

orm

aliz

ed le

akag

e p

ow

er

in id

le m

od

e

90%

40%

Low-leakage 133nF decap on

virtual VCC

No decap on virtual VCC

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Decoupling Capacitor Placement

OxideleakageDual-VT

core

Reducedleakage

Longertime

constant

Dual-VTcore

Decap on full supply Decap on virtual supply

PPerformance

Convergence time

Oxide leakage savings PP

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0%

5%

10%

15%

20%

10 100 1000 10000 100000 1000000Number of idle cycles

Tot

al p

ower

sav

ings

Total Active Power Savings(Fixed activity: α = 0.05)

Body bias (1.28V): active: FBB, idle: ZBB

Reference: 450mV FBB to core with clock gating, 1.28V, 4.05GHz, 75°C

0.5 5 50 500 5000 50000

Number of consecutive idle cycles (TOFF)

Number of consecutive active cycles (TON)

Power savings for TOFF > ~100 idle cycles

PMOS sleep transistor (1.32V)

Tot

al p

ower

sav

ings Max 18%

Max 8%

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Body Biasing

Body biasing with a local control loop can be used to lower the impact of process variationsUsed to limit die-to-die and within-die variations

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Normalized Delay vs VDD & VTH

Sakurai, Kuroda

VTH (V)

0 0.2 0.4 0.7 1

1.5 V

3.0 V

5.0 V

0.6

1.0

1.4

1.8

No

rmal

ized

Del

ay ±0.15V

VDD =1.0 V

±0.05V

? VTH =

0.5

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Self-Adjusting Threshold-Voltage Scheme (SATS)

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SATS Experimental Results

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Substrate Biasing

Tschanz, JSSC 11/02

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Effectiveness of Substrate Bias

Die-to-die variations

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Effectiveness of Substrate Bias

Within-die variations

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Dynamic Voltage Scaled MicroprocessorExternal VDD 3.3V±10% Internal VDDL 0.8V~2.9V ±5%

TX3900

User Logic PLL

VT

VS

Po

wer

Dis

sip

atio

n (

mW

)Operating Frequency (MHz)

0

100

200

300

0 10 20 30 40

Theory

CMOS:V DD

=3.3V

VS scheme : Internal VDD=optimized

Measurement

Courtesy: Prof. Kuroda

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Adapting VDD and VTH

Miyazaki, ISSCC’02

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Adapting VDD and VTH

Miyazaki, ISSCC’02

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Optimal EDP Contours

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10%1%0.1%(ELk/ESw)ref

DecAddInvTopology

Technology parameters (Vddmax, Vth

ref) rarely optimalTechnology parameters (Vddmax, Vth

ref) rarely optimal

Reference Design:Dref (Vdd

max,Vthref)

Large variation in optimal circuit parameters Vddopt, Vth

opt, wopt

Vddmax

Vddmin Vth

min

Vthmax

Sizing, Supply, Threshold Optimization

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Adiabatic Circuits

R

Ctr

E = (RC/tr)CV2 (for tr >> RC)

Applying slow input slopes reduces E below CV2

Useful for driving large capacitors (Buffers)Power reduction > 4 for pad drivers (1 MHz) ISI

ADIABATIC CHARGING

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Adiabatic Computing

Basic ConceptsWhen charging a capacitor through RC-network with a slowly changing ramp, power dissipation is reduced by reducing the slope of the ramp.No switch should ever be enabled when a voltage is over itMake sure every node is reset to the original stage before performing the next operation!“reversible computing”-> take energy back to the source-> ensure that state is known

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Adiabatic Computing

Principles of storing and erasing information:Energy dissipation of the combinational logic can be made arbitrarily small by operating the circuit slowly enoughInformation can be loaded into memory circuits dissipating only arbitrarily small energyInformation can be copied with arbitrarily small energyErasing the last copy of a piece of information dissipates an irreducible finite amount of energy.

Koller, Athas, PhysComp’92, Landauer, IBM J. ResDev’61

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Six-Phase Charge Transfer

Watkins, JSSC 12/67

One-bit delay

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Split-Level Charge Recovery

Younis, Knight, IWLPD’94

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Adiabatic Circuits

A B C

φ0

φ1

φ2

from Athas

Holding the inputs for the each stageuntil the output energy has been returned

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Reversible Pipelines

In

OutLogic

return logic

clkC

Make return path different

Problem: always results in CVth2/2 loss!

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Reversible Pipelines

holdresetφ0

φ1

φ2

φ3

di

di-1

di+1

φi

retrun

din

φ1 φ3

φ0 φ2

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Partially Erasable Latches

Pck

M1F1 F1

M2

M3 M4

V

0

Output stays at Vth

Stored energy is½ CVth

2, vs. ½ CV2

How to use this?

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Partially Erasable Latches

Pck

M1F1 F1

M2

M3 M4M5 M6F0 F0

Denker, ISLPED’94

Pck

Pck1

Pck

Pck1

Requires 4-clocks for interfacing

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Single Pck + Auxiliary Clock

Pck

M1F1 F1

M2

M3 M4

M5 M6

M8M7F0 F0

CXCX

2 412..

µµ

2 412..

µµ

2 412..

µµ

2 412..

µµ

2 412..

µµ

2 412..

µµ

2 412..

µµ

2 412..

µµ

1

0

0

1 1 0

PckCX

F0

F1A B

Maksimovic et al,ISLPED’97

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Clock Generation

Logi

c

VDD 2 Clk QR

C

PckL

VG

01 fc

Clk

÷ 2QQ

Stage1

Stage2

Stagen

L

VB

Q

F0

F0

F1

F1

Pck

Ck

CX

CX

Clk

F0 F2

F2

Fn

Fn

F1 F1 F2 Fn−1

72012

µµ.

Enable

Principle

Implementation

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Single Pck + Reference Voltages

Kim, Papaefthymiou, ISLPED’98

Cascading Gates:

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Adiabatic µP

Athas, et al, JSSC 12/97Athas, et al, JSSC 11/00

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Adiabatic µP

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E-R Latch

W/ dynamic logic

W/ PTL

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Other Ideas

Charge recycling busH. Yamauchi, et al, JSSC, 4/95

Adiabatic display driverJ. Ammer, ISSCC’99

Various examples of charge-recycling logic

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Silicon on Insulator (SOI)

References:Chapter 5 by Shahidi, Assaderaghi, AntoniadisK. Bernstein, N.J. Rohrer, “SOI Circuit Design Concepts,” Kluwer2000.K. Bernstein, ISSCC’00 SOI Tutorial2001 Microprocessor Design Workshop, lectures by C.T Chuangand R. PrestonArticles from Chandrakasan/Brodersen, IEEE Press 1998.

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SOI Transistor

Bernstein, ISSCC’00

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SOI DevicesPartially depleted (PD)

Pros: Easier to manufacture (Si thickness)Scalable, tolerance to variationsDecoupling VT from Si thickness

Cons: Floating body effects: I-V kink, parasitic bipolar effect

Fully depleted (FD)Pros:

Significantly reduced floating body effectsSharper subthreshold S

Cons:VT is a function of the charge in the body – variesManufacturability, compatibility with bulk CMOS

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Soi Microprocessors

IEDM 9720% Perf. Over Bulk

PD/SOI

0.35 um

230 MHz

(Tester Limit)

StrongArm-110

(Core Only)

DEC

ISSCC 99Bulk 433 MHz

0.35 um Lgate

FD/SOI

0.25 um Lgate, 4LM Al

600 MHz64b DEC AlphaSamsung


0.12 um Leff

PD/SOI

0.12 um Leff, 6LM Cu

580 MHz32b PowerPC

(PowerPC750)

IBM


0.12 um Leff

PD/SOI


550 MHz64b PowerPCIBM

ISSCC 00Migration from

0.12 um Leff

PD/SOI


660 MHz64b PowerPCIBM

Hot Chip 99

EE Times 99

PD/SOI


1.00 GHz64b Power4IBM

IEDM 99PD/SOI


1.00 GHz64b Power4

(Test Chip)

IBM

ISSCC 01PD/SOI


1.10 GHz64b Power4IBM

SourceCommentTechnologyFreq.ProcessorComp.

From C.T. Chuang

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SOI Design

Advantages:Less Capacitance (~5-40%)Lower powerReduced effective VT, short channel effects, body effectLayout simplicity (no wells, plugs, …)

Disadvantages:History-dependent timingIncreased device leakageBody effect issuesSelf heatingDecoupling capacitance

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SOI Timing Issues

µs constants ps constants


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Floating Body Effects in PD SOI

Neither S or D junction biased – body floats. Effects:Threshold Variability “Kink” in output characteristics

PD

FD

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Floating Body Effects in PD SOI (cont’d)

Parasitic Bipolar Transistor

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SOI Circuit ConsiderationsStatic circuits – history-dependent delayFirst switch (often slowest) vs. second switch (often fastest)


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Initial State

Initial input at “low”

nFET VB determined by back-to-back diodes

pFET VB at VDD initially

pFET VB before input falling transition determined by capacitive coupling

Initial input at “high”

nFET VB at GND initially

nFET VB before input rising transition determined by capacitive coupling

pFET VB determined by back-to-back diodes

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First Two Transitions


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History-Dependent Delay


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55


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Convergence to steady state

Noise Margins!

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Dynamic Circuits in SOI

Dynamic HistoryBipolar effectLess charge sharing

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Parasitic Bipolar

Dynamic lookahead adderCumulative Effect of Parasitic Bipolar Current and PropagatedNoise Cause Data Corruption after 3rd Stage in The Chain

C.T. Chuang (M. Canada et al., ISSCC, 1999)

Parasitic Bipolar Current

Propagated NoisefromPrevious Stage

VDD VDD

GND

PCH C0

T7 T8 T9 T10

T5 T6XC0XPCH

T1 T2 T3VD

D

T0CLK

ND1

ND2

gz gp gg

xci ci

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Pre-discharging Nodes

C.T. Chuang (D. H. Allen et al., ISSCC, 1999)

Bulk Design SOI Design

CLK

A1A1 B1

OUTOUTA0Y

X

B0

CLKCLK

A0A0B0

A1 B1

OUT

X

Y

Intermediate nodes discharged to prevent parasitic bipolar effect

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Dynamic Circuit Techniques

Conditional Feedback

Pre-dischargeIntermediate Node

Re-order Pulldown Tree

Setup Inputsduring Precharge

Cross-connectedInputs(Stack swizzling)

CLKFB_L

CLK

OUT

A B

E

E

F

F

C.T. Chuang (D. H. Allen et al., ISSCC, 1999)

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Pass-Transistor Logic in SOI

Inverter:

Keeper:

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PTL in SOI

(Assaderaghi 94): DTMOS

Example: VT = 0.4V at 0 V; 0.17V at 0.5 V

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DTMOS

Body and gatetied together

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DTMOS

ID vs. VDS for normal and DT operation

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DTMOS

Subthreshold currents for SOI NMOS and PMOS transistors with bodies grounded vs. DTMOS

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0.5V SOI Pass-Gate Logic

CPL

Fuse, et al, ISSCC’96

Buffer “type A”Gate-body connection

(GBC)

Buffer type BInput-body connection

(IBC)

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0.5V SOI Pass-Gate Logic

Announcements - University of California, Berkeleybwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s04/lectures/Lectur… · Power savings for T OFF > ~100 idle cycles PMOS sleep transistor

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