Announcements Assignment 7 posted, due Friday 18 th All project components ordered Dates –Thursday 12/1 review lecture –Tuesday 12/6 project demonstrations.

Announcements

• Assignment 7 posted, due Friday 18th

• All project components ordered

• Dates– Thursday 12/1 review lecture– Tuesday 12/6 project demonstrations in the lab

(no presentations)– Sunday 12/11 project reports due to me by

email– Tuesday 12/13 final exam, 1pm-3pm here.

Lecture 20 Overview

• Sequential Logic

• Timing Methodology

• Registers and counters.

Sequential Logic

• So far we have dealt mainly with combinational logic - arrays of gates which have an output determined by the present state of the inputs

• output=f(present inputs)

• Sequential logic deals with devices with memory - where the output depends on the present and past states of the inputs and outputs

http://fac-web.spsu.edu/cs/faculty/bbrown/web_lectures/sequential/

Principal of sequential circuits

• A simple example: This thermostat system has loops. The output of the temperature changing functions affects the input of the temperature-checking function. Its output affects the operation of the temperature changing function(s).

• Sequential circuits use feedback – results (outputs) are fed back as input• outputs=f(present inputs, past inputs, past outputs)• This means the logic circuit has "memory”

Summary of latches and flip-flops

•Flip-flops come in two main types– Level sensitive; usually called a latch -

simplest type, can be made with as few as four switches (two cross-coupled logic gates)

– Edge-triggered (e.g. master-slave, D-type)

•A clock or enable input is used to specify when a change to the input matters

Compare Latches and Flip-Flops

The behaviour is the same unless the input changes while the clock is low. The latch is transparent when the clock is low - any change on the input is reflected on the output. The edge-triggered FF is only affected by the input present at the clock edge

Note the inversion symbols at the CLK inputs

http://fac-web.spsu.edu/cs/faculty/bbrown/web_lectures/sequential/

Edge triggered Flip-Flops

• Two basic types• Positive-edge triggered: Inputs are sampled on the rising edge of the clock pulse. Outputs change after the rising edge• Negative-edge triggered: Inputs are sampled on the falling edge of the clock pulse. Outputs change after the falling edge

Timing methodologies

• What are TSU, TH, Propagation time?• Timing specifications describe the rules for

interconnecting components and clocks– They guarantee correct operation of the system when

strictly followed• The correct approach depends on which building

blocks are used as memory elements– i.e. edge-triggered flip-flops or level sensitive latches

• Basic rules for correct timing– correct inputs, with respect to time, must be provided

to the flip-flops– No flip-flop changes state more than once per

clocking event

Timing Methodologies• Definitions

– Clock event:• a periodic event. Causes state of memory element to change. Can be a

rising edge, falling edge or a high level or low level.– Setup Time:

• Minimum time before the clocking event during which the input to the flip-flop must be stable (Tsu)

– Hold Time:• Minimum time after the clocking event during which the input to the flip-flop

must remain stable (Th)– Propagation Delay:

• Time take for an input change to be reflected on the output

Typical Timing Specifications

• Example: A positive edge-triggered D flip-flop will have specified– setup and hold times (Tsu and Th)– minimum clock pulse width (Tw)– propagation delays (low to high (Tplh), high to low (Tphl), max and

typical)

All measurements are made from the clocking event - in this case the rising edge of the clock.

www.onsemi.com/pub_link/Collateral/74HC74.PDF

Dealing with Timing Specifications

Divide circuit into combinational logic and flip-flop

Combinational Logic

FF

FF

FF

CLK

Q D

D

D

Q

Q

TXn Xn+1

Dealing with Timing Specifications

Divide circuit into combinational logic and flip-flop

Combinational Logic

FF

FF

FF

CLK

Q D

D

D

Q

Q

TXn+1 FF(TP)

Xn+1 Xn+2

Logic(TP)

Xn+2 must be

ready FF(TSU) before clock edge

Dealing with Timing Specifications

Divide circuit into combinational logic and flip-flop

Combinational Logic

FF

FF

FF

CLK

Q D

D

D

Q

Q

TXn+1 FF(TP)

Xn+1 Xn+2

Logic(TP)

Xn+2 must be

ready FF(TSU) before clock edge

Defines minimum clock period:T > FF(TP) + Logic(TP) + FF(TSU)

Other Flip-flop features

• As well as input (D), clock (C) and output (Q, Q'), often have additional features:

• Reset – forces output state to 0: R– Synchronous: Q=R'·D (when next clock edge

arrives)– Asynchronous: Doesn't wait for next clock edge;

quick but dangerous

• Preset (or Set) - forces state to 1: S (or P)– Synchronous: Q=D+S (when next clock edge

arrives)– Asynchronous

• Both Reset and Preset– Q=R'·D+S (set-dominant)– Q=R'·D+R'·S (reset-dominant)

Other Flip-flop features• Selective input capability (input enable or load): LD or EN

– multiplexer at input: Qnew=LD'·Qold+LD·D– So, LD=0 : Qnow=Qold

– LD=1: Qnow=D– load may or may not override reset/set (usually R/S have priority)

•Note: all unused inputs should be tied either HIGH or LOW.

Using Flip-Flops: Registers• Collections of flip-flops with similar controls and logic

– Stored values are somehow related (for example, they form a binary number)

– Share clock, reset and set lines– A register is a group of memory elements read or written as a unit

• Examples– storage register– shift register– Counters

This is the simplest form of register: a parallel input/output register.A Clock signal causes the inputs to be read and stored and made available at the outputs. Stores bits, but does nothing with them Parallel Input

Parallel Output

Shift Register

• Often, however, the bits will not arrive in parallel but in serial - one bit at a time– Use a shift register– Input is applied to first flip-flop and shifted along one at each

clock event– This example is a 4-bit shift register– It accepts serial input, stores the last 4 bits in the sequence and

makes them available as parallel output

Serial Input

Parallel Output

Shift Register

• Often, however, the bits will not arrive in parallel but in serial - one bit at a time– Use a shift register– Input is applied to first flip-flop and shifted along one at each

clock event– This example is a 4-bit shift register– It accepts serial input, stores the last 4 bits in the sequence and

makes them available as parallel output

Serial Input

Parallel Output

http://www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/register03.html

Universal Shift Register

• Holds 4 values– serial or parallel inputs– serial or parallel outputs– permits shift right or left– new values can be applied from left or right

Shift Register Application

• Often only one line is available for data transmission (eg computer networks)– Shift register can perform parallel to serial conversion at one end– serial to parallel conversion at the other

Another Application: Pattern recognizer• Performs some combinational function of input samples

– In this case, recognizing the pattern 1001 on the single input line

0 1 0 0 1

Digital counters: Ripple (Asynchronous) Counters

Input

InputOutput

Output

Counters are sequential logic circuits that proceed through a well-defined sequence of states. For a "divide-by-2" counter, simply connect the Q' output to the D input and feed an external clock signal in as the input:

Input

InputOutput

OutputFor a "divide-by-4" counter, connect 2 flipflops together in a chain:

• For a "divide-by-n" : connect 2n flipflops together.• Note that the FF outputs do not change at exactly the same time because of the propagation delay in each FF. • These counters are known as ripple or asynchronous counters.

+'ve edge-triggered D flipflop

Synchronous Counters• Connect all flip-flops to the same clock• All flipflops change state at the same time (synchronous)• A counter is a device which sequences through a fixed set of patterns

• in this case, 1000, 0100, 0010, 0001 (if one of these patterns is the initial state, defined by set/reset)• Counts to n (n=number of flipflops) before repeating

• Mobius (or Johnson) Counter• in this case, get 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000• counts to 2*n before repeating

http://www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/register07.html

Binary Counter

• We normally want to count in a more useful fashion: e.g. binary• This requires combinational logic between the flipflops• Need a rule for binary counting

•"The least significant bit always changes"• "A bit changes state if all less significant bits are HIGH"

• Can implement this with an XOR gate• Note Xxor1=X'

Decimal Binary Hex

0 0000 0

1 0001 1

2 0010 2

3 0011 3

4 0100 4

5 0101 5

6 0110 6

7 0111 7

8 1000 8

9 1001 9

10 1010 A

11 1011 B

12 1100 C

13 1101 D

14 1110 E

15 1111 F

AD

A B C D

So A+=Axor1, B+=BxorA, C+=CxorAB, D+=DxorABC

Binary Down Counter

• How do you modify this circuit to count down?• The rule is

• "The least significant bit always changes"• "A bit changes state if all less significant bits are LOW"• Note AXOR1=A' AXNOR0=A'

Decimal Binary Hex

0 0000 0

1 0001 1

2 0010 2

3 0011 3

4 0100 4

5 0101 5

6 0110 6

7 0111 7

8 1000 8

9 1001 9

10 1010 A

11 1011 B

12 1100 C

13 1101 D

14 1110 E

15 1111 F

AD

So A+=Axor1, B+=BxnorA, C+=CxnorAB, D+=DxnorABC

A B C D

Binary Counters• Counters can be bought pre-packaged: e.g. a synchronous four-bit binary up-counter• Standard component with many applications•Typical features:

• Positive edge-triggered FFs with synchronous LOAD and CLEAR inputs• LOAD input allows parallel load of data from D, C, B, A • CLEAR input resets outputs to 0000

• EN input: must be asserted to enable counting• RCO: ripple-carry output used for cascading counters

• High when counter is in its highest state 1111• Implemented using an AND gate: RCO= QA·QB·QC·QD

EN

DCBA

LOAD

CLK

CLR

RCO

QDQCQBQA

Binary Counters• For an 8-bit synchronous binary up counter, cascade two 4-bit devices together• Connect RCO from the first to EN of the second

Offset Counters

• Two types; for a "starting offset counter" use the synchronous LOAD input.• The counter counts like this:•0110,0111,1000,1001,1010,1011,1100,1101,1111,0110,...

• For an "ending offset counter" use a comparator for the ending value• The counter counts like this:•0000,0001,0010, ... , 1100,1101,0000, ....

Load value 0110

Sequential Logic Summary

• Fundamental building blocks of circuits with memory– latch and flipflop– R-S latch, R-S master-slave flipflop, D master-slave flipflop,

edge-triggered D flipflop

• Timing Methodologies– use of clocks

• Basic registers– Storage register– Shift registers– pattern detectors– counters