Ani(Ovionic Unfied Memory)

8/14/2019 Ani(Ovionic Unfied Memory)

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OVONIC UNIFIED MEMORY

SUBMITTED BY,

ANI GOPAL

01 605

S7 ECE

DEPT. OF ELECTRONICS AND COMN.

GOVT. ENGG. COLLEGE

THRISSUR


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Ovonic Unified Memory

Abstract

Ovonic unified memory (OUM) is an advanced memorytechnology that uses a chalcogenide alloy (GeSbTe).The alloyhas two states: a high resistance amorphous state and a lowresistance polycrystalline state. These states are used for therepresentation of reset and set states respectively. The

performance and attributes of the memory make it anattractive alternative to flash memory and potentiallycompetitive with the existing non volatile memory technology.

DEPT. OF ELECTRONICS AND COMN. GOVT. ENGG.COLLEGE THRISSUR

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Review of memory basics

Every computer system contains a variety of devices tostore the instructions and data required for its operation. These

storage devices plus the algorithms needed to control ormanage the stored information constitute the memory systemof the computer. In general, it is desirable that processorsshould have immediate and interrupted access to memory, sothe time required to transfer information between theprocessor and memory should be such that the processor canoperate at, close to, its maximum speed. Unfortunately,memories that operate at speeds comparable to processors

speed are very costly. It is not feasible to employ a singlememory using just one type of technology. Instead the storedinformation is distributed in complex fashion over a variety ofdifferent memory units with very different physicalcharacteristics.

The memory components of a computer can besubdivided into three main groups:

1)Internal processor memory: this usually comprises of asmall set of high speed registers used as working registersfor temporary storage of instructions and data.

2) Main memory: this is a relatively large fast memoryused for program and data storage during computer


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operation. It is characterized by the fact that location inthe main memory can be directly accessed by the CPUinstruction set. The principal technologies used for mainmemory are semiconductor integrated circuits and ferrite

cores.

3) Secondary memory: this is generally much larger incapacity but also much slower than main memory. It isused for storing system programs and large data files andthe likes which are not continually required by the CPU;italso serves as an overflow memory when the capacity ofthe main memory when the capacity of the main memory

is exceeded. Information in secondary storage is usuallyaccessed directly via special programs that first transferthe required information to main memory. Representativetechnologies used for secondary memory are magneticdisks and tapes.

The major objective in designing any memory is toprovide adequate storage capacity with an acceptable level of

performance at a reasonable cost.

Memory device characteristics


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The computer architect is faced with a bewilderingvariety of memory devices to use.However; all memories arebased on a relatively small number of physical phenomena andemploy relatively few organizational principles. The

characteristics and the underlying physical principles of somespecific representative technologies are also discussed.

Cost:

The cost of a memory unit is almost meaningfullymeasured by the purchase or lease price to the user of the

complete unit. The price should include not only the cost of theinformation storage cells themselves but also the cost of theperipheral equipment or access circuitry essential to theoperation of the memory.

Access time and access rate:

The performance of a memory device is primarilydetermined by the rate at which information can be read fromor written into the memory. A convenient performancemeasure is the average time required to read a fixed amount ofinformation from the memory. This is termed read access time.

The write access time is defined similarly; it is typically but notalways equal to the read access time. Access time depends onthe physical characteristics of the storage medium, and also onthe type of access mechanism used. It is usually calculatedfrom the time a read request is received by the memory and tothe time at which all the requested information has been madeavailable at the memory output terminals. The access rate ofthe memory is defined is the inverse of the access time.


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Clearly low cost and high access rate are desirablememory characteristics; unfortunately they appear to belargely compatible. Memory units with high access rates aregenerally expensive, while low cost memory are relatively slow.

Access mode-random and serial:

An important property of a memory device is the orderor sequence in which information can be accessed. If locationsmay be accessed in any order and the access time isindependent of the location being accessed, the memory is

termed as a random access memory.

Ferrite core memory and semiconductor memory areusually of this type. Memories where storage locations can beaccessed only in a certain predetermined sequence are calledserial access memories. Magnetic tape units and magneticbubble memories employ serial access methods.

In a random access memory each storage location canbe accessed independently of the other locations. There is, ineffect, a separate access mechanism, or read-write, for everylocation. In serial memories, on the other hand, the accessmechanism is shared among different locations. It must beassigned to different locations at different times. This isaccomplished by moving the stored information ,the read writehead or both. Many serial access memories operate bycontinually moving the storage locations around a closed pathor track. A particular location can be accessed only when itpasses the fixed read write head; thus the time required toaccess a particular location depends on the relative location ofthe read/write head when the access request is received.


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Since every location has its own addressing mechanism,random access memory tends to be more costly than the serialtype. In serial type memory, however the time required to bringthe desired location into correspondence with a read/write

head increases the effective access time, so access tends to beslower than the random access. Thus the access modeemployed contributes significantly to the inverse relationbetween cost and access time.

Some memory devices such as magnetic disks and drums contain large number of independently rotating tracks. Ifeach track has its own read-write head, the track may be

accessed randomly, although access within track in serial.In such cases the access mode is sometimes called semirandom or direct access. It should be noted that the accessis a function of the memory technology used.

Alterability-ROMS:

The method used to write information into a memorymay be irreversible, in that once the information has beenwritten, it cannot be altered while the memory is inuse,i.e.,online. Punching holes in cards in cards and printing onpaper are examples of essentially permanent storagetechniques. Memories whose contents cannot be altered onlineare called read only memories. A Rom is therefore a nonalterable storage device. ROMs are widely used for storingcontrol programs such as micro programs. ROMs whosecontents can be changed are called programmable read onlymemories (PROMs).

Memories in which reading or writing can be done withimpunity online are sometimes called read-write memories


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(RWMs) to contrast them with ROMs. All memories used fortemporary storage are RWMs.

Permanence of storage:

The physical processes involved in storage are

sometimes inherently unstable, so that the stored informationmay be lost over a period of time unless appropriate action istaken. There are important memory characteristics that candestroy information:1. Destructive read out2. Dynamic volatility

3. Volatility

Ferrite core memories have the property that the methodof reading the memory alters, i.e., destroys,the storedinformation; this phenomenon is called destructive readout(DRO). Memories in which reading does not affect the storeddata are said to have nondestructive readout (NRDO). In DROmemories, each read operation must be followed by a write

operation followed by a write operation that restores theoriginal state of the memory. This restoration is usually carriedout by automatically using a buffer register.

Certain memory devices have the property that astored 1 tends to become a 0, or viceversa, due to somephysical decay processes. Over a period of time, a storedcharge tends to leak away, causing a loss of information unlessthe stored charge is restored. This process of restoring is calledrefreshing. Memories which require periodic refreshing arecalled dynamic memories, as opposed to static memories,which require no refreshing. Most memories that usingmagnetic storage techniques are static. Refreshing in dynamicmemories can be carried out in the same way data is restored


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in a DRO memory. The contents of every location aretransferred systematically to a buffer register and thenreturned, in suitably amplified form, to their original locations.

Another physical process that can destroy the contentsof a memory is the failure of power supply. A memory is said tobe volatile if the stored information can be destroyed by apower failure. Most semiconductor memories are volatile, whilemost magnetic memories are non volatile.

Cycle time and data transfer rate:

The access time of a memory is defined as the timebetween the receipt of a read request and the delivery of therequested information to its external output terminals. In DROand dynamic memories, it may not be possible to initiateanother memory access until a restore or refresh operation hasbeen carried out. This means that the minimum time that mustelapse between the initiations of two different accesses by thememory can be greater than the access time: this rather

loosely defined time is called the cycle time of the memory.

It is generally convenient to assume the cycle timeas the time needed to complete any read or write operation inthe memory. Hence the maximum amount of information thatcan be transferred to or from the memory every second is thereciprocal of cycle time. This quantity is called the data transferrate or band width.

Random access memory


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Random access memories are characterized by thefact that every location can be accessed independently. Theaccess time and the cycle time are constant independent of theposition. Figure below gives the main components of a random

access unit. The storage cell unit comprises N cells each ofwhich can store one bit of information. The memory operatesas follows. The address of the required location is transferredvia the address bus to the memory address register . Theaddress is then processed by the address decoder whichselects the required location in the storage cell unit. A read-write select control line specifies the type of access to beperformed. If read is requested, the contents of the selected

location is transferred to the output data register. If write isrequested, the word to be written is first placed in the memoryinput data register and then transferred to the selected cell.Since it is not usually desirable to permit simultaneous readingand writing, the input and the output data registers arefrequently combined to form a single data register.

Each storage cell has a number of lines connected to it.

The address lines are used to select the cell for either readingor writing, as determined by the read-write control lines. A setof data lines is used for transferring data to and from thememory. The actual of physical lines connected to a storagecell is very much a function of the technology being used.Frequently one physical line has several functions, e.g., it maybe used as both an address and a data line.

RAMs are available in the static and the dynamicversions.


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FLASH

An interesting MOS device is the flash memory which isan important type of non volatile memory. It is very simple andcompact and looks like a MOSFET, except that it has two gateelectrodes one on top of another. The top electrode is the onethat we have direct access to, and is known as the control gate.Below that we have the so called floating gate that is


Addressdecoder

Storage

cell driver

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capacitively coupled to the control gate and the underlyingsilicon.

The basic cell operation involves putting charge on the

floating gate or removing gate, in order to program theMOSFET to have two different VTs, corresponding to two logiclevels.

To program the cell, we apply a high field to both thedrain and the floating gate such that the MOSFET is insaturation. The high longitudinal electric fielding the pinch offregion accelerates electrons towards the drain and make them

energetic. If the kinetic energy of the electrons is high enough,a few can become hot enough to be scattered into the floatinggate. Once they get into the floating gate, electrons becometrapped in the potential well between the floating polysilicongate and the oxide on either side.This barrier is extremely highfor a trapped electron. Therefore the trapped electronsessentially stay in the floating gate forever, unless the cells areintentionally erased. Thats why a flash memory is non volatile.

To erase the cell, we use Fowler Nordheim tunnelingbetween the floating gate and the source in the overlap region.A high voltage is applied to the source with the control gategrounded. The polarity of the field is such that the electronstunnel from the floating gate, through the oxide barrier.

Introduction to OUM

Almost 25% of the world wide chip markets arememory devices, each type used for their specific advantages:


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the high speed of an SRAM, the high integration density of aDRAM, or the nonvolatile capability of a FLASH memory device.

The industry is searching for a holy grail of future

memory technologies to service the upcoming market ofportable and wireless devices. These applications are alreadyavailable based on existing memory technology, but for asuccessful market penetration. A higher performance at a lowerprice is required.

The existing technologies are characterized by thefollowing limitations. DRAMs are difficult to intergrate.SRAMs

are expensive. FLASH memory can have only a limited numberof read and write cycles.EPROMs have high power requirementand poor flexibility.

None of the present memory technologies combinefeatures like

The ability to retain stored charge for long periods

with zero applied or refreshed power. High speed of data writes.

Low power consumption.

Large number of write cycles.

Therefore, the whole industry is investigating differentadvanced memory technologies like MRAM, FRAM, OUM orpolymer devices etc.

FRAM: this technology uses a crystal unit cell of pervoskitePZT (lead zirconate titanate).data is stored by applying a verylow voltage. The electric field moves the central atom by


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changing crystal orientation of unit cell which results in thepolarization of internal dipoles.

MRAM: It uses a magnetic tunnel junction and transistor. The

electric current switches the magnetic polarity and this changeis sensed as a resistance change.

OUM: There is a growing need for nonvolatile memorytechnology for high density stand alone embedded CMOSapplication with faster write speed and higher endurance thanexisting nonvolatile memories. OUM is a promising technologyto meet this need. R.G.Neale, D.L.Nelson, and Gorden.E.Moore

originally reported a phase-change memory array based onchalcogenide materials in 1970. Improvements in phase-change materials technology subsequently paved the way fordevelopment of commercially available rewriteable CDs andDVD optical memory disks. These advances, coupled withsignificant technology scaling and better understanding of thefundamental electrical device operation, have motivateddevelopment of the OUM technology at the present day

technology node.

OUM is the non volatile memory that utilizes areversible structural phase change between amorphous andpolycrystalline states in a GeSbTe chalcogenide alloy material.

This transition is accomplished by heating a small volume ofthe material with a write current pulse and results in aconsiderable change in alloy resistivity. The amorphous phasehas high resistance and is defined as the RESET state. The lowresistance polycrystalline phase is defined as the SET state.


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Memory Structure

The above figure shows the memory structure of OUM


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Key advantages of OUM

The following are the key advantages of OUM:1.Endurance2. Read-write performance

3. Low programming energy4. Process simplicity5.Cost6.CMOS embeddability7.Scalability

Write endurance is competitive with other potentialnon volatile memory technology, is superior to Flash. Readendurance is unlimited. The write/read performance iscomparable to DRAM. The OUM technology offers overwritecapablility, and bit/byte data can be written randomly with noblock erase required. Scaling is a key advantage of OUM.

Write speed and write energy both scales withprogrammed volume. Its low voltage operation is compatiblewith continued CMOS feature and power supply scaling. Lowvoltage operation and short programming pulse widths yield

low energy operation for the OUM, a key metric for mobileportable applications.


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BASIC DEVICE OPERATION

The basic device operation can be explained from thetemperature versus time graph. During the amorphizing resetpulse, the temperature of the programmed volume of phasechange material exceeds the melting point which eliminatesthe poly crystalline order in the material. When the reset pulseis terminated the device quenches to freeze in the disorderedstructural state. The quench time is determined by the thermalenvironment of the device and the fall time of the pulse. Thecrystallizing set pulse is of lower amplitude and of sufficient

duration to maintain the device temperature in the rapidcrystallization range for a time sufficient for crystal growth.


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Technology and performance

The figure below shows device resistance versus writepulse width. The reset resistance saturates when the pulsewidth is long enough to achieve melting of the phase changematerial. The set pulse adequately crystallizes the bit in 50 nswith a RESET/SET resistance ratio of greater than 100.

I-v characteristics


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The figure above shows I-V characteristics of the OUMdevice. At low voltages, the device exhibits either a lowresistance (~1k) or high resistance (>100k), depending on itsprogrammed state. This is the read region of operation. Toprogram the device, a pulse of sufficient voltage is applied to

drive the device into a high conduction dynamic on state. Fora reset device, this requires a voltage greater than Vth.

Vth is the device design parameter and for currentmemory application is chosen to be in the range of 0.5 to 0.9 V.to avoid read disturb, the device read region as shown in thefigure, is well below Vth and also below the reset regime.

The device is programmed while it is in the dynamic on state.The final programmed state of the device is determined by thecurrent amplitude and the pulse duration in the dynamic onstate. The reciprocal slope of the I-V curve in the dynamic onstate is the series device resistance.


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R-I characteristics


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The above figure shows the device read resistanceresulting from application of the programming current pulseamplitude. Starting in the set condition, moving from left to

right, the device continues to remain in SET state as theamplitude is increased. Further increase in the pulse amplitudebegins to reset the device with still further increase resettingthe device to a standard amorphous resistance. Beginningagain with a device initially in the RESET state, low amplitudepulses at voltages less than Vth do not set the device. OnceVth is surpassed, the device switches to the dynamic on stateand programmed resistance is dramatically reduced as

crystallization of the material is achieved. Further increase inprogramming current further crystallizes the material, whichdrops the resistance to a minimum value. As the programmingpulse amplitude is increased further, resetting again isexhibited as in the case above. Devices can be safely resetabove the saturation point for margin. Importantly, the rightside of the curve exhibits direct overwrite capability, where aparticular resistance value can be obtained from aprogramming pulse, irrespective of the prior state of thematerial. The slope of the right side of the curve is the devicedesign parameter and can be adjusted to enable a multi- statememory cell.


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About Chalcogenide alloy

Chalcogenide or phase change alloys is a ternary system ofGallium, Antimony and Tellurium. Chemically it is Ge2Sb2Te5.


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Production Process: Powders for the phase change targetsare produced by state-of the art alloying through melting ofthe raw material and subsequent milling. This achieves thedefined particle size distribution. Then powders are processedto discs through Hot Isotactic Pressing

Comparison of amorphous and crystalline states

Amorphous Crystalline

Short range atomic order Long range atomic orderLow free electron density High free electron densityHigh activation energy Low activation energy


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High resistivity Low resistivity

Conclusion

Non volatile OUM with fast read and write speeds, highendurance, low voltage/low energy operation, ease ofintegration and competitive cost structure is suitable for ultrahigh density ,stand alone and embedded memory applications.

These attributes make OUM an attractive alternative to flash


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memory technology and potentially competitive with volatilememory technologies.

References

1. OUM a 180 nm non volatile memory cell elementtechnology for stand alone and embedded applications Stefan Lai and Tyler Lowrey

2.Current status of Phase change memory Stefan Lai3. Computer Organization V Carl Hamacher, Zvonko G

Vranesic, Safwat G Zaky


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4. Computer Architecture and Organization - John P Hayes.5.Solid State Devices- Ben G Streetman,Sanjay Banerjee

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Ani(Ovionic Unfied Memory)

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