May 2, 2012 1 Analyzing Chips in a System Context May 2, 2012 May 2, 2012 Srdjan Djordjevic Srdjan Djordjevic Senior Applications Engineer Senior Applications Engineer [email protected]
Nov 18, 2014
May 2, 2012 1
Analyzing Chips in a System Context
May 2, 2012May 2, 2012Srdjan DjordjevicSrdjan DjordjevicSenior Applications EngineerSenior Applications Engineer
May 2, 2012 2
Why Analyze Chips in a System Context?
Red = Chip Only Blue = Includes System-Level PDS
May 2, 2012 3
Voltage Noise TransferSystem-Level Effects Can Dominate
Chip•High impedance•Localized voltage noise
effects
Package•Low impedance•Global voltage noise effects
Chip Alone Chip with Package
Result:The low-loss power distribution system of the package readily
transfers voltage noise effects to other on-chip circuits.
May 2, 2012 4
Necessity of Fully Considering System-Level Noise
(Example – SSO Simulation)
Oversimplification=
Risk
Needed Accuracy=
Risk Avoided
Simulation assuming ideal power delivery network Simulation with partial power delivery effects
Simulation with all power delivery effects
May 2, 2012 5
Chip-Package Co-Simulation Flow
Chip/Package Co-Simulation: Enabling 2.5D IC (including silicon interposers) and 3D IC projects (including TSVs)with a focus on frequency domain power delivery network (PDN) analysis and EMI analysis.
May 2, 2012 6
Frequency Domain Chip / System Co-Simulation
(BGA / SiP / 2.5D IC / 3D IC)Chip Data:
LEF / DEF … GDS … GUI to .SPDPackage / System Data:
Layout Databases to .SPDCircuit Linkage with MCP
.SPD or models
May 2, 2012 7
Multi-Die / Package Floorplanning
Outputs forPhysical
Implementation
Pack
age
Dat
aLEFDEF
LEFDEF
Die
Dat
a
Verilog
Die pads
Verilog
Die pads
Pad-ringdata
Pad-ringdata
AIF
ASCII pin info
UPD
ASCII net list
Die1
Package
Die2
Die1
Device & Connection Planning
Feasibility(ex: Bump, RDL Wirebond)
Hierarchical data preparation with automated
net mapping
GU
I
May 2, 2012 8
IO Planning and Multi-die Floorplanning(2.5 D with Silicon Interposer)
BGA
SiliconInterposer
Die
PCB
Slice 2Slice 1
DeviceData Source
BGABGA.txt from Cadence APD
Si InterposerCreated on-the-fly
Die Slice 1LEF / OrbitIO IOview
Die Slice 2ASCII data
May 2, 2012 9
Chip-Centric Analysis(pre- & post layout-frequency & time domain)
2D/3D TransientWaveforms
S/Y/ZParameters
SPICENetlist
SPICENetlist
SPICENetlist
Power GridExtraction
Time-DomainCo-simulation
Device ParasiticExtraction
Current ProfileExtraction
Frequency-DomainCo-simulation
Power ModelExtraction(inc. TSV)
PowerPlanner
IO ModelExtraction(inc. RDL)
LEF/DEF GDS GUI
May 2, 2012 10
Frequency DomainChip / System Co-Simulation
Assessment of various decap options.
May 2, 2012 11
On-Chip Decoupling Capacitors Case Example
5nF on-chipdecap inserted No on-chip
decap5nF on-chip
decap
May 2, 2012 12
Frequency Domain EMI Analysis(Chip-Level Input for System-Level Results)
Far Field Radiation
Near Field Radiation
May 2, 2012 13
Enabling Chip/System Power Co-simulation
distributed
lumped
Chip PDN models can:
-Be at a range of abstraction levels from lumped to distributed-Vary from 2-node to N-nodes (N = number of physical pins)-Have 1 to M current sources (M can be larger than N)
board
VRM
1 N
1 M
chip
package
May 2, 2012 14
Model Connections to SupportChip / System Simulation
Interposer (or 3DIC) IO/Power SPICE Model
BGA IBIS, SPICE or S-parameter Model
PCB S-parameter or SPICE Model
Chip(s) IO/PowerSPICE Model
Chip(s) IO/PowerSPICE Model
RLCK Network andTransient Current Sources
Spatially DistributedRLCK Network
XcitePI
XtractIM& PowerSI
OptimizePI &other Sigrity
Analysis Products
inc. RDL in IO modelInc. TSV in power model
May 2, 2012 15
Open Model Connection Protocol
Intelligent and automated model connections to save time and reduce errors.
May 2, 2012 16
Thank YouThank You!!