Analysis of Path Profiling Information Generated with Performance Monitoring Hardware Alex Shye, Matt Iyer, Tipp Moseley, Dave Hodgdon Dan Fay, Vijay Janapa Reddi, Dan Connors University of Colorado at Boulder Department of Electrical and Computer Engineering DRACO Architecture Research Group
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Analysis of Path Profiling Information Generated with Performance Monitoring Hardware
Analysis of Path Profiling Information Generated with Performance Monitoring Hardware. Alex Shye, Matt Iyer, Tipp Moseley, Dave Hodgdon Dan Fay, Vijay Janapa Reddi, Dan Connors University of Colorado at Boulder Department of Electrical and Computer Engineering - PowerPoint PPT Presentation
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Analysis of Path Profiling Information Generated with
Performance Monitoring Hardware
Alex Shye, Matt Iyer, Tipp Moseley, Dave Hodgdon
Dan Fay, Vijay Janapa Reddi, Dan Connors
University of Colorado at Boulder
Department of Electrical and Computer Engineering
DRACO Architecture Research Group
Introduction
• Profile information is critical to success of optimizers
4 Function Boundaries3 Function Boundaries2 Function Boundaries1 Function Boundary0 Function Boundaries
Multiple Runs
• May be possible to use multiple runs to provide more accurate path profile data
164.gzip
0
500
1000
1500
2000
2500
3000
3500
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4500
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Number of Aggregated Runs
# Unique Paths
50K
100K
500K
1M
5M
10M
Future Work
• Region Formation– Characterize quality of our regions
• Important because no correlation between regions
– Regions stretching across function boundaries
• Noise Elimination– Crucial to removing false positives due to path
crediting
• Effects of Optimization– Find effects of superblocks, inlining, etc. on partial
paths and accuracy of path profile
Conclusion
• We introduce rationale and initial data of PMU-based path profiling
• PMU-based profiling shows promise
• At Sampling Period = 5M cycles– ~85% accurate– ~1% overhead
Questions?
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Dynamic Optimization System” PLDI 2000.[Ball92]T. Ball and J.R. Larus. “Optimally Profiling and Tracing Programs”
TOPLAS 1992.[Ball96]T. Ball and J.R. Larus. “Efficient Path Profiling” MICRO-29, 1996.[Bond05] M.D. Bond and K.S. McKinley. “Practical Path Profiling for
Dynamic Optimizers”, CGO 2005.[Bruen03]D. Bruening, R. Garnett and S. Amarasinghe. “An Infrastructure
for Adaptive Dynamic Optimization” CGO 2003.[Chen03]H. Chen, W.C. Hsu, J. Lu, P.C. Yew and D.Y. Chen. “Dynamic
Trace Selection Using Performance Monitoring Hardware Sampling” CGO 2003.
[Conte94]T.M. Conte, B.A. Patel and J.S. Cox. “Using Branch Handling Hardware to Support Profile-Driven Optimization” MICRO-27, 1994.
References (cont)[Intel04]Intel, “Intel Itanium 2 Processor Reference Manual: For Software
Development and Optimization” May 2004.[Joshi04]R. Joshi, M.D. Bond and C. Zilles. “Targeted Path Profiling:
[Kistler01]T. Kistler and M. Franz. “Continuous Program Optimization” IEEE Trans. On Computers v50 no6 June 2001.
[Lu04]J. Lu, H. Chen, P.C. Yew and W.C. Hsu. “Design and Implementation of a Lightweight Dynamic Optimization System” Journal of ILP 6, 2004
[Merten00]M.C. Merten, A.R. Trick, E.M. Nystrom, R.D. Barnes, and W.W. Hwu. “A Hardware Mechanism for Dynamic Extraction and Relayout of Program Hot Spots” ISCA 2000.