Analog Testing 02

© A 2-1

In ich test statements can be used in analog tests.

nd the purpose of the Measuring al Amplifier (MOA).

gilent Technologies 2007 Agilent Medalist ICT Systems : Analog Testing

2 Analog In-Circuit TestingRevision Date: 10/07

this chapter... ■ Introduction To Analog In-Circuit Testing, 2-2

■ System Sources and Detectors for In-Circuit Testing, 2-5

■ Basic Analog In-Circuit Measurements, 2-7

■ Special Analog In-Circuit Measurements, 2-11

■ Solving In-Circuit Measurement Problems, 2-16

■ Analog Test Blocks, 2-29

■ In-Circuit Test Statement Summary, 2-33

■ The Measuring Operational Amplifier (MOA), 2-36

Objectives

This chapter contains information to help you:

■ Understand how sources and detectors are used for analog in-circuit testing.

■ Have a general understanding of analog in-circuit measurement techniques.

■ Be able correct the following types of measurement errors: source voltage, source loading, guard offset, and current splitting.

■ Understand the process to discharge capacitors.

■ Understand the structure and purpose of analog test blocks.

■ Know whin-circuit

■ UnderstaOperation

© A 2-2

Int

InATe

e provides an example of an analog test

re for In-Circuit Tests

block diagram of the basic system to make analog in-circuit tests. This ardware consists of stimulus sources, a ational amplifier (MOA) circuit, and ors. This hardware is located on the ere must be an ASRU card in the first head module that is used. The MOA, tectors are discussed in detail at the end

ock diagram for an in-circuit test

Pin Card

Test Fixture

Device Under Test

PC Board

lusces

E DC

MeasuringOperational

AmplifierCircuit

ResponseDetectors

(A/D)AC / DC

orPhase Sync.

ard


roduction To Analog In-Circuit Testing

troduction To nalog In-Circuit sting

Analog in-circuit (unpowered) testing verifies that:

■ analog components are properly loaded on the PC board

■ component values are within specified tolerances.

Analog components that can be tested in-circuit include:

■ capacitors■ connectors■ diodes■ FETs■ fuses■ inductors■ jumpers■ potentiometers■ resistors■ switches■ transistors■ zeners

All the analog in-circuit device tests must pass before power is applied to the board under test.

The development software automatically generates individual in-circuit tests based on a board’s device characteristics and circuit topology. The software compiles the individual tests, called blocks, and places them in the analog directory of the local board directory. During test execution, each test block is executed from the analog subroutine of the testplan.

Basic Hardware for In-Circuit Tests shows a block diagram of the measurement hardware and Basic Test

Block Examplblocks.

Basic Hardwa

Figure 2-1 is ahardware used measurement hmeasuring operresponse detectASRU card. Thslot of each testsources, and deof this chapter.

Figure 2-1 Bl

ControlCard

StimuSour

I orAC or

ASRU C

© A 2-3

Int

ck Example

a basic analog test block for a resistor Example 2-1, and a fragment of the mple 2-2. This test block, written by the nt software, resides in the analog s executed from the analog subroutine in ch test statement in the Analog_Tests utes the specified analog test block. The k consists of at least: a connection r connect or connect), and a atement such as resistor or inductor. statement closes the appropriate relays, ement statement defines the type of xpected value, limits, and measurement

ne.

.



The Control Card manages each in-circuit test by closing the proper testhead relays to connect the device under test into the MOA circuit. Passive and reactive devices, such as resistors and capacitors, are connected into the input path of the MOA. Active devices, such as diodes and transistors, are connected into the feedback loop of the MOA. A test for each type of device is shown in detail in Chapter 3, Analog Tests: Reference.

The stimulus sources and response detectors, selected by the test program, are also connected by the Control Card. As the stimulus is applied to the MOA circuit, the response detector measures the output of the MOA and sends the results to the Control Card for evaluation. Depending on the results, the Control Card sends either a pass or fail condition back to the test program.

Basic Test Blo

An example of test is shown intestplan in Exatest developmedirectory, and ithe testplan. Easubroutine execanalog test blocstatement (cleameasurement stThe connectionand the measurmeasurement, eoptions.

Example 2-1 Testplan fragment

sub Analog_Tests ! Start of Analog Tests subroutitest "analog/A24C1" ! Execute an analog test block.test "analog/A24C2"test "analog/A24L1"test "analog/A24R1"test "analog/A24R2"test "analog/A24Q1"test "analog/A24CR1"

subend ! End of Analog Tests subroutine

© A 2-4

Int



Example 2-2 Analog test block

clear connect s to "R1-1"; i to "R1-2"; g to "R3-1"resistor 10k, 10, 10, re5, wb

By default, the system writes analog in-circuit tests in the following format

disconnect allconnect s to "<node name>"connect i to "<node name>"connect g to "<node name>"resistor 10k, 10, 10, re5, wb

© A 2-5

Sy

SyanIn

ircuit Testing

e MOA must be measured to determine component being tested. This accomplished by either the AC DC voltmeter on the ASRU Card. Other e used for analog functional (powered) ined in Chapter 4, Analog Functional ting.

evelopment software generates a test for automatically selects the detector est, and the detector range. Two of the

RU card sources

se

st resistors, channel resistance of FETs, ses, jumpers, potentiometers, switches.

st capacitors and inductors. Frequencies the AC sources: 128/1024/8192 Hz. When lecting 128 Hz, always use the ed option,

hich integrated the measurement over a mplete line cycle (normal integration time

insufficient for making valid easurements).

st diodes, zeners, and npn or pnp nsistors.


stem Sources and Detectors for In-Circuit Testing

stem Sources d Detectors for -Circuit Testing

This section explains the system sources and detectors for in-circuit testing. The ASRU Card supplies all needed sources and detectors. You can, however, use external instruments by connecting them to the system through the functional ports.

Sources for In-Circuit Testing

The ASRU Card sources provide stimuli for analog in-circuit and analog functional testing. The sources used for in-circuit testing are listed in Table 2-1.

The other ASRU Card sources are used in analog functional (powered) testing. (See Chapter 4, Analog Functional and Mixed Testing.)

When the test development software generates a test for a device, it automatically selects the proper stimulus source for that test and sets up the source parameters. These parameters include:

■ the type of source (AC or DC)■ the source amplitude■ in the case of an AC source, the frequency

Detectors for In-C

The output of ththe value of themeasurement isvoltmeter or thedetectors may btesting as explaand Mixed Tes

When the test da component, itneeded for the t

Table 2-1 AS

Source U

DC voltage sources

Tefu

AC voltage sources

Teofsewcoism

DC current sources

Tetra

© A 2-6

Sy


stem Sources and Detectors for In-Circuit Testing

detectors are synchronized to the AC sine wave sources. These two detectors are used together to determine the values of reactive components. These synchronized sources and detectors form a phase synchronous detector.

© A 2-7

Ba

BInM

g (G Bus)d Operation of the MOA

trates the basic bus and relay r a simple in-circuit test.

e of an operational amplifier is ly very high, most of the input current is hrough reference feedback resistor, Rref. n output voltage, Vmoa, at the output of ortional to the values of I and Rref. From es of Rref, Vs, and Vmoa, the unknown e, Rx, can be calculated.

ation used to calculate the value of the er test, Rx, is:

To Controller

s

moa-------


sic Analog In-Circuit Measurements

asic Analog -Circuit easurements

To test analog components, the tester uses a system of measurement buses and relay matrices to connect the component under test into the MOA circuit. The following sections explain these connections:

■ The Source (S) and Input (I) Buses

■ Guardin■ Wideban

Figure 2-2 illusarrangement fo

Figure 2-2 Basic measurement circuit elements for an in-circuit test

The Source (S) and Input (I) Buses

In Figure 2-7 on page 2-15, the component under test, Rx, is connected into the input path of the MOA with testhead relays and measurement bus I. For simplification, only one set of relay contacts per bus is shown. ASRU stimulus source Vs, is connected to the other end of the component with the S bus. This connection is made through a second set of relays.

Input current, I, flows from the source, Vs, through the component under test to the input of the MOA. Ideally, the input current is limited only by the resistance (or reactance) of the component under test. Because the

input impedanccharacteristicalforced to flow tThis develops athe MOA, propthe known valucomponent valu

The system equcomponent und

S Bus Relay

V SourcesSDC AC

Rx = Rref ( )Vs-Vmoa

Rx I Bus

Rref

I Bus Relay

MOA Vmoa

ReferenceResistors

Switchable

Detector

Rx RrefV

V–-------=

© A 2-8

Ba

e parallel impedance paths cause rrors by providing current paths around under test. Zsg and Zig, in Figure 2-3, mponents forming parallel impedance e component under test, Rx. When such re formed, parallel current, Ip, flows hrough the MOA feedback path. The rough the feedback paths cause Rx to ller impedance than it actually is.



Even though the output voltage from the MOA is limited by its power supply, a wide range of Rx values can be measured. This is accomplished by switching different values of the reference resistor, Rref, into the feedback path of the MOA. Six different values of precision reference resistors are available on the ASRU card. These resistors are illustrated in Figure 2-2 on page 2-7.

By using an AC stimulus source, and an AC detector, reactive components (inductors and capacitors) can also be measured by this technique. Reactive component measurement, called Phase Synchronous Detection, is explained next.

Phase Synchronous Detection

Phase synchronous detection is used to compensate for the phase shifts that occur in combination resistive/reactive circuits. When the MOA measures a circuit containing resistive and reactive components, the MOA's output contains both a resistive and a reactive component. The real component of the MOA output is directly proportional to the resistive part of the circuit, and the imaginary component is directly proportional to the reactive part of the circuit. The phase synchronous detector is able to distinguish between the real and imaginary parts of the output. This explanation is somewhat simplified, but this is basically the way reactive measurements are made.

Guarding (G Bus)

The device under test may have one or more parallel impedance paths due to the circuit topology of the board

under test. Thesmeasurement ethe component represent the copaths around thparallel paths aaround Rx and tadded current thappear as a sma

© A 2-9

Ba

Vmoa



Figure 2-3 Parallel resistance paths cause measurement errors

The G bus is used to guard the component under test by breaking parallel impedance paths. Figure 2-4 shows where the G bus is connected in the circuit when the component under test is shunted by a parallel impedance path. By connecting the G bus as shown, the current that would flow through both Zsg and Zig becomes insignificant. When the non-inverting input to the MOA is grounded as shown in Figure 2-4, the inverting input becomes a virtual ground due to characteristics of the op amp. This also places the I bus connection at virtual ground. With the G bus also at ground potential, no difference of potential exists across Zig, and no current flows through the parallel path around Rx and through the MOA feedback path. Vs does, however, supply current to Zsg. This current does not affect the measurement as long as the Vs output impedance is very low compared to Zsg. Because there may be one or more parallel paths around the device under test, there may be one or more G bus connections.

S Bus

Vs

Zsg

RxI

ZigIp MOA

Rref

I+Ip

© A 2-10

Ba

ideband (wb) versus narrowband frequency sponses

moa

Frequency

WideBand

ow



Figure 2-4 The G Bus breaks parallel resistance paths

Wideband Operation of the MOA

There are two bandwidths, narrow and wide, which affect the gain of the MOA. If no bandwidth is specified, the system uses narrow band. However, wideband can be specified in some measurement situations. Use of wideband increases the amplification bandwidth of the MOA.

To implement the wideband feature, the wb option is added to the options field of the appropriate component test statement. For example:

clear connect s to "R1-1"; i to "R1-2"resistor 2k, 1.4, 1.4, wb

Figure 2-5 illustrates how narrowband and wideband relate to the gain and frequency response of the MOA. Note that the wideband option should not be used when the test includes both the sb option and the re1 or re2 option.

Figure 2-5 Wre

V

Rref

VirtualGround

MOA

I Bus

G Bus Relay

I

S Bus

Vs

Rx

Zsg Zig

Gain

NarrBand

© A 2-11

Sp

SpInM

ke enhancement you must specify the dition to the sa option.

s provide the system with a six-wire, rement technique. The extra buses are the measurement situation requires -6 illustrates the location of these buses

ent circuit.


ecial Analog In-Circuit Measurements

ecial Analog -Circuit easurements

Testing devices which are connected in a circuit can require special measurement techniques. The effects of other devices connected to the device under test (DUT) can cause errors in the basic measurement using the S and I buses as described above. Guarding can also introduce measurement error. The three types of errors are:

■ Source Voltage Error■ Guard Offset Error or Guard Gain Error■ Current Splitting

There are two techniques that can eliminate or reduce the effect of in-circuit measurement errors. The two techniques are:

■ Sensing■ Enhancement

Sensing

Three-wire measurements, using the S, I, and G buses, provide the basic configuration for analog in-circuit testing on the Agilent In-Circuit Test system. However, the addition of three more buses, A, B, and L, help overcome the measurement problems associated with in-circuit testing. Each of the three additional buses is paired with one of the three basic measurement buses, S, I, and G. The buses are paired as follows:

S to A I to B G to L

Sensing the source requires enhancement measurements. Enhancement is explained later in this

chapter. To invoen option in ad

The added busein-circuit measuused only whenthem. Figure 2in the measurem

© A 2-12

Sp

st block in Example 2-3 shows the the measurement options.

easurement options

structs the test to

ense the source (S bus) with the A bus. he en option must also be used when the a option is specified.

ense the detector (I bus) with the B bus.

ense the guard (G bus) with the L bus.

se enhancement. This is mandatory when ing sa.



Figure 2-6 Six-wire measurement technique

Any combination of the additional buses, A, B, and L, may be needed for a measurement. This depends on the value of the device under test, measurement accuracy desired (according to the tolerance multiplier that you specified), and circuit topology around the device under test. The basic idea is to eliminate the effects of wire and relay resistance and thermal offset of relay contacts in the measurement circuit.

Sensing requires that the appropriate wires be included in the test fixture, the appropriate connections are specified in the test block, and that the appropriate measurement options are included in the measurement statement.

The development software includes the sense bus wires in the fixture building files and reports, and adds the appropriate connections and measurement options to the test block. The measurement options are described in Table 2-2.

The example teconnections and

Rs

Vs

A Bus

Ri Rref

B Bus

L Bus

Rg

MOA

Rx

Zsg Zig

Table 2-2 M

Option In

sa STs

sb S

sl S

en Uus

© A 2-13

Sp

b to "Node_2"

uired, the sense connections can be nner or they can be made by seperate rd under test. If the remote sensing flag the development software determines

cessary, seperate sense wires will be te sensing can be performed in the erate wires are not required.

ows the differenece between the two Notice that the only difference between sing levels is in the way that the clear ent is constructed.

"Q5e"

"R1_2"; g to "Q5e"

).

."Q5e"



Example 2-3 Connections and measurement options

clear connect s to "Node_1"; a to "Node_1"; i to "Node_2", connect g to "Node_3"; l to "Node_3"resistor 10, 10, 10, sa, sb, sl, en

Sense Methods

This section describes the sense methods that can be used on the system to generate more accurate measurements for some in-circuit tests. If you turn on Remote Sensing, the development software determines the sensing needs of each test. Depending on the device under test, topology of the circuitry, and the accuracy of the test desired (according to the tolerance multiplier that you specified when entering board data), any combination of the A, B, and L buses may be required.

If sensing is reqmade in the scawires to the boais turned on andthat they are neused. If adequasanner, then sep

Example 2-4 shsense methods.the G and L senconnect statem

Example 2-4

! This test uses seperate wire S bus sensing.clear connect s to "R1_1"; a to "R1_1"; i to "R1_2"; g toresistor "R1", 10.1k, 2.5, 2.5, sa, en

! This test uses seperate wire S and I bus sensing.clear connect s to "R1_1"; a to "R1_1"; i to "R1_2"; b toresistor "R1", 10.1k, 2.5, 2.5, sa, sb, en

! This test uses testhead level L bus sensing (remote sensingclear connect s to "R1_1"; i to "R1_2"; gl to "Q5e"resistor "R1", 10.1k, 2.5, 2.5, sl

! This test uses separate wire L bus sensing (remote sensing)clear connect s to "R1_1"; i to "R1_2"; g to "Q5e"; l to resistor "R1", 10.1k, 2.5, 2.5, sl

© A 2-14

Sp

tions, you can use a measurement n as enhancement. Enhancement makes

omplex system measurement equation to :

urement errors caused by the component of the board under test.

ideal characteristics of the operational .

al offsets of bus and testhead relays.

invoked with the en option in the atement.

-2"

age 2-15 shows the measurements taken ent is used. For DC measurements, asured at the four points shown with the ro, and again with the source set to the ight extra measurements).

ements, voltages are measured at the n with the source signal at zero degrees,

ource at +90 degrees, and again with the grees (12 extra measurements).

urements of enhancement cause the quire significantly more time. If test



Depending on the sensitivity of the measurement, when a seperate sense wire is required you can either connect both the signal and sense wire to the same probe receptacle, or use separate probes. Most of the time, especially with the short wire lengths of the Express test fixtures, you need only a single probe. The development software always assumes a single probe and automatically assigns a resource and fixture wire for the sense bus. If you want to use separate probes, you must add the second probe location manually.

Note that when sensing the S bus, you must also use the en (enhancement) option, except for the diode and zener tests.

Enhancement

In difficult situatechnique knowuse of a more ccompensate for

■ The meastopology

■ The non-amplifier

■ The therm

Enhancement ismeasurement st

Example 2-5 en option example

clear connect s to "R1-1"; a to "R1-1"; i to "R1-2"; b to "R1connect g to "GND"; l to "GND"resistor 100, 2, 2, wb, sa, sb, sl, en

Note that sense a (sa) requires enhancement (en), but enhancement can be used by itself.

When enhancement is specified, voltages are measured at the device under test and the reference resistor of the MOA. These measured values, instead of the default values, are used in the formula that determines the value of the device under test. This compensates for the voltage drop across the measurement buses, for thermal offsets created by the system relays, and for DC offsets in an AC measurement.

Figure 2-7 on pwhen enhancemvoltages are mesource set to zeneeded level (e

For AC measurfour points showagain with the ssource at -90 de

The extra measdevice test to re

© A 2-15

Sp

Enhancementuses voltagemeasurementstaken atthese points.

moa



time is a concern, use enhancement only where necessary.

Figure 2-7 Enhancement

S Bus

Vs

Rx I Bus

A Bus

B Bus

Reference

MOA Out

Rref

VMOA

© A 2-16

So

SoMPr

system relays, etc. that connect the er test into the MOA circuit may also ent problems. The bus wires represent

series with the component to be tested, ays can appear as temperature- ge sources. The bimetallic contacts of a

sic thermocouple device. When these ted, either by current flow or by other

thin the system, a temperature dependent thermal offset) is generated. Figure 2-8 alent circuit, showing bus impedances sets generated by the relays.

moa

ge


lving In-Circuit Measurement Problems

lving In-Circuit easurement oblems

This section describes how to solve the in-circuit measurement problems discussed earlier.

The basic difficulty with in-circuit testing is measuring the actual value of a device on a board under test, when that device is affected by other components in the circuit. In the explanation of the basic measurement circuit, guarding with the G bus was shown to minimize the measurement problems caused by parallel impedance paths.

Guarding, however, does not correct all in-circuit measurement errors. In fact, guarding can create problems which must be considered. Additionally,

fixture wiring, component undcause measuremimpedances in and testhead reldependent voltarelay form a bacontacts are heaheat sources wioutput voltage (shows an equivand thermal off

Figure 2-8 Bus impedances and thermal offsets cause measurement errors

Three major types of measurement errors are caused by the problems illustrated in Figure 2-8. These errors are: source loading (or source voltage error), guard offset error, and current splitting. They are summarized in Table 2-3.

Rx

Zsg Zig

Device UnderTest

Vs

Rs

I+I1

I1

E

EI 2

Rg

Ri

E

Rref

I+I2

V

Too LarMOA

© A 2-17

So

ntacts, impedances of the measurement pedances on the board under test. See Offset Error and Solution on page 2-21.

us. This voltage drop appears as an offset sometimes called guard gain. See Guard

t to the MOA, and by an apparent increase s are used. MOA input impedance value reference resistor in the MOA



See also:

• Discharge Capacitors on page 2-26

Table 2-3 Measurement errors

Error Cause

Source Voltage Error

Is caused by the thermally induced offset voltages of relay cobuses, and loading of the stimulus source by small parallel imSource Voltage Error and Solution on page 2-18 and Guard

Guard Offset Error

Is caused by the voltage drop across the impedance of the G bvoltage at the input terminals of the MOA. Guard offset error isOffset Error and Solution on page 2-21.

Current Splitting Is caused by a small impedance path in parallel with the inpuin the input impedance of the MOA when AC stimulus sourceincreases as the frequency of the source is increased. A largefeedback path also contributes to current splitting.

See Current-Splitting Error and Solution on page 2-24.

© A 2-18

So

drops that prevent the full value of the e from being applied to the component re 2-8 on page 2-16 is a simplified am illustrating these impedances.

ptions sa and en are specified, the value measured at the device under test. The , instead of the default value, is used in t determines the value of the device compensates for the voltage drop across ermal offsets created by the system C offsets in an AC measurement.

moa

mall



Source Voltage Error and Solution

When measuring a component on the board under test, the stimulus voltage is applied to the component through the series resistance of relay contacts, system cabling, and fixture wiring. All of these resistances

result in voltagestimulus voltagunder test. Figuschematic diagr

Figure 2-9 Bus impedances and thermal offsets cause measurement errors

In Figure 2-9, resistors RS and RI represent the impedances of the S and the I bus, respectively. The voltage drops across these resistances subtract from VS and the remaining voltage is applied across the component under test. This smaller source voltage, Vapplied, across the device under test, results in less feedback current, i, through the feedback resistor, Rref. With less feedback current, the output voltage, Vmoa, is also smaller than expected. This causes the measured value of the component under test to be higher than its actual value.

Source voltage error can be reduced by sensing the source with the A bus. Sensing the source also requires enhancement (en). When the A bus is connected and the

measurement oof the source ismeasured valuethe formula thaunder test. Thisthe S bus, for threlays, and for D

Rs and Ri are theS and I Bus Impedances

RsRx

Ri Rref

DeviceUnder Test

VappliedVs

Source Voltage Error = Vs - Vapplied

V

Too SMOA

© A 2-19

So

e I bus in series with the reference e inverting (-) input to the MOA can no voltage drop across the I bus. To

B bus in an in-circuit test, it must be clear connect or connect statement b must be specified in the options field -circuit test statement.

R1-2"

moa



Example 2-6

clear connect s to "R1-1"; a to "R1-1"; i to "R1-2"resistor 2k, 1.4, 1.4, wb, sa, en

Note that the use of the sa option alone does not improve the accuracy of the measurement. The sa option must be accompanied by the enhancement option, en.

Source voltage error correction can also be improved by sensing the I bus with the B bus. The B bus connection, shown in Figure 2-10, moves the virtual ground of the MOA to the component under test. This places the

impedance of thresistor, Rref. Thlonger sense theincorporate theincluded in the and the option sof the analog in

Example 2-7 Option sb

clear connect s to "R1-1"; a to "R1-1"; i to "R1-2"; b to "resistor 2k, 1.4, 1.4, wb, sa, sb, en

Figure 2-10 Use of the B Bus (sb) reduces source voltage error

S Bus A Bus I Bus RrefRx

B Bus RelayB Bus

MOA

Vs

A/D1

V

© A 2-20

So

uses the output voltage of the MOA to as source voltage error in Figure 2-9 on resulting MOA output causes a larger ance value than the actual resistance mponent under test.

loading is a source voltage error, you for source loading the same way as for

error.



Source Loading and Solution

Source loading, another type of source voltage error, is illustrated in Figure 2-11. When the device under test, Rx, is a small value and is shunted by a small impedance, Zsg, the stimulus source is loaded. The voltage drop across its own internal resistance, represented by Rvs, prevents the full value of Vs from being applied to the component under test. Source

loading error cabe too low, justpage 2-18. Themeasured resistvalue for the co

Because sourcecan compensatesource voltage

Figure 2-11 Source loading causes a source voltage error

Vs

Rvs Rs

I+I1

Rx

Zsg

Ri Rref

I

Device UnderTest

RgMOA

Vmoa

Too Small

© A 2-21

So

urce voltage error. In a similar manner, connected into the measurement

an impedance. This impedance is Rg in Figure 2-12. The current through Zsg causes a voltage drop across Rg. The exhibits a thermal offset which can

easurement errors.

moa



Guard Offset Error and Solution

Use of the G bus was discussed at the beginning of this chapter as a method of breaking parallel resistance paths. Guarding, however, can create a problem of its own called guard offset error. This error is illustrated in Figure 2-12 and Figure 2-13 on page 2-22. The S and I buses have already been shown to exhibit an impedance

that causes a sothe G bus, whencircuit, exhibitsrepresented by the impedance G bus relay alsocontribute to m

Figure 2-12 The G Bus causes guard offset error

The voltage drop across Rg causes most of current I2 to flow through Zig as shown. The voltage is multiplied by the ratio of Rref to Zig and appears as an error voltage at the output of the MOA. The equivalent circuit showing how this error voltage appears to the MOA input is illustrated in Figure 2-13. The increase in current through Rref makes the measured value of Rx smaller than its actual value (Vmoa too large).

Device UnderTestRs Ri Rref

I+I1 I+I2I

Rx

Zsg Zig

I1

I 2

Verror

Vs

Vg

RgVg = Voltage Drop Across Rg

MOAV

© A 2-22

So

tement's measurement option field. strates the electrical connection of the L

ed Remote Sensing on, the software ch tests require sensing of the G bus. The nclude the extra L bus wires.

e

Vmoa



Figure 2-13 Equivalent circuit showing Verror caused by the G Bus

The L bus is used to correct for guard offset error. The L bus connects the non-inverting input of the MOA to the G bus connection. This eliminates the offset voltage (the voltage drop across the G bus) normally sensed by the non-inverting input of the MOA. The development software uses the L bus, when it is needed, with the sl

option in the staFigure 2-14 illubus. If you turndetermines whifixture reports i

Figure 2-14 The L Bus (sl) corrects for guard offset error

Vs

Rx

Zig

I

I2

Ve

Vs = Source VoltageVe = Error Voltage

Rref

I+I2

MOAVmoa

Too Larg

S Bus I Bus Rref

L Bus

G Bus

Vs

Rx

Zsg Zig

MOA

© A 2-23

So

nd B buses, you can use one probe for parate probes with the L bus. The

s assumes a single probe, and ssigns the resource and fixture wire.

s in a component test, you must include connect, or connect statement, and you option to the component test statement:

test.

R3-2"



Unlike the A and B buses, you can use testhead level sensing with the L bus. That is, connect gl to <node> connects the G and L buses together inside the testhead and there is no additional wiring required in the fixture. You can still connect the L bus to the board under test with:

"connect g to <node>; l to <node>"

The development software determines the level of sensing necessary based on device values and topology of the circuit. See the examples below.

As with the A aboth wires or sesoftware alwayautomatically a

To use the L buit in the clear must add the sl

Example 2-8

! This test uses testhead level sensing.

clear connect s to "R1-1"; i to "R1-2"; gl to "R3-2"resistor 2k, 1.4, 1.4, wb, sl

! This test uses separate wires to sense at the device under

clear connect s to "R1-1"; i to "R1-2"; g to "R3-2"; l to "resistor 2k, 1.4, 1.4, wb, sl

© A 2-24

So

g also increases when the frequency of rce increases. Because the input

n operational amplifier increases as ases, more current is shunted by a small s increasing the measurement error.

al methods of reducing or eliminating error. The first of these is to move o the component under test via the B n Figure 2-16. This connection places of the I bus in series with reference d prevents the MOA from sensing the ross the I bus. You can use the B bus by he connect statement and specifying b in the component test statement, as ple 2-9.



Current-Splitting Error and Solution

Current splitting is another measurement error associated with in-circuit testing. Current splitting is caused when the impedance from the I bus to the G bus, Zig (Figure 2-15) is small compared to the impedance of the I bus and the input of the MOA, Zin. When Zig is small, some of the current that should flow through the feedback resistor, Rref, flows through Zig. The shunted current through Zig causes the MOA output to be too low, causing the measured value of the component under test to be larger than its true value. The reference element, Rref, can contribute to current splitting as well. When a large reference element is used, this increases the resistance of the MOA feedback path. The increase in resistance in the feedback path can cause more current to be shunted through Zig and cause a measurement error.

Current splittinthe stimulus souimpedance of afrequency increvalue of Zig, thu

There are severcurrent splittingvirtual ground tbus, as shown ithe impedance resistor Rref, anvoltage drop acincluding it in ttesting option sshown in Exam

Figure 2-15 Current splitting error

Vs

Device UnderTestRs Ri RrefRx

Rg

Zig

I 2I I+I2

MOAVmoa

© A 2-25

So

R1-2"

the circuit impedance between them is ible. Figure 2-16 illustrates the B bus well as the parallel impedance, Zig.

reduces current splitting

he gain of the MOA by changing the h. frequency of the AC source.

Vmoa



Example 2-9 Example of the sb option

clear connect s to "R1-1"; a to "R1-1"; i to "R1-2"; b to "resistor 2k, 1.4, 1.4, wb, sa, sb, en

Another method of minimizing current splitting is to maximize the MOA input-to-ground impedance. This impedance is represented in Figure 2-16 as Zig. You can modify the connect statement to place the I and G

buses such thatas large as posssense point, as

Figure 2-16 The B Bus (sb) and maximum moa input-to-ground impedance (Zig)

Other steps that you can take to reduce current splitting error are: use an AC source, lower the frequency of the source, and change the bandwidth of the MOA.

In summary, refer to Figure 2-17. To reduce the effects of current splitting:

■ minimize Ierr by placing the S and I buses such that maximum circuit impedance is between the I and G buses.

■ minimize the voltage drop across the I bus by using the B bus.

■ increase tbandwidt

■ lower the

S Bus

Vs

Rx

Zig

Maximize Zig

I

G Bus

I Bus

B Bus

Rref

MOA

© A 2-26

So

scharge status

harge needed

rge successful

too high to discharge (> 100 volts)

not decreasing

decreasing but did not reach the exit level

to make measurement: hardware problem

rge not executed: over-voltage error



Figure 2-17 Current splitting solution

Discharge Capacitors

The discharge capacitors feature lets you discharge capacitors that can affect analog in-circuit tests. Capacitors may already be charged when the board is placed on the fixture, or they may charge as a result of applying sources during in-circuit tests, or applying the DUT power supplies during powered testing.

The test development software determines which capacitors need discharging and writes an analog test block that discharges them with the S and G buses. The discharge algorithm attempts to discharge the board to 0.1 volt or less. The maximum voltage that can be discharged is 100 volts.

The discharge algorithm returns a variable to indicate its status as shown in Table 2-4.

Vs

Rx

Ierr

I I’

R I Bus

RrefA+1

Table 2-4 Di

Value Status

0 No disc

1 Discha

2 Voltage

3 Charge

4 Charge

5 Unable

6 Discha

© A 2-27

So

nds on the number of nodes that need RC time constant of the discharge level of the charge on the board.

ped for multiple-board panels, all boards panel are discharged as one board.

charge blocks for problem areas. The is very similar to an analog test block. It he test (BT-BASIC) statement in the

g/discharge_C1"; Return

ample 2-10, the discharge block r connect statement to connect the S

ross the capacitor to be discharged, and statement. The discharge statement ional name, an entry voltage level, an el, and an optional return variable.

typical discharge block

Returnct s to "C1-1"; g to "C1-2"C1", entry 0.1, exit 0.1, Return

ock name must be unique and that if you e the result of the discharge test, you return variable. To pass the return e discharge block to the testplan, you licit block. An explicit block is

e test analog and end test



The discharge algorithm is executed up to four times by these statements:

■ unpowered

■ All statements that turn on vacuum, such as faon, fbon, and fabon, when executed in the unpowered mode.

The dps statement executes the discharge algorithm once to remove excess trapped charge from the board. The board might not be discharged all the way to 0.1 volt.

These statements execute a dps which includes a single discharge:

■ All statements that turn on vacuum, such as faon, fbon, and fabon, when executed in the unpowered mode.

■ scratch board and load board

■ fixture lock and fixture unlock

■ cps and dps

■ powered and unpowered

■ autoadjust, confirm, and learn fixture timing

■ Any statement during which an overvoltage error occurs.

■ testhead is, testhead power on, and testhead power off

The discharge requires 0.1 to 0.5 seconds if no discharge is necessary. The time required if a discharge is

necessary depedischarging, thecircuit, and the

For tests develoof one type on a

You can add disdischarge blockis executed by ttestplan:

test "analo

As shown in Excontains a cleaand G buses acthe discharge includes an optexit voltage lev

Example 2-10 A

test analog; clear connedischarge "

end test

Note that the blwant to evaluatmust include a variable from thmust use an expdelimited by thstatements.

© A 2-28

So



The entry voltage level specifies the voltage above which to start discharging (.1 minimum). If the voltage detected on the capacitor is not above this level, no discharging takes place. The exit voltage level specifies the voltage below which to stop discharging (0.005 minimum). If you do not specify the entry and exit voltage levels, the system uses an entry level of 0.1 volt and an exit level of 0.05 volt.

A capacitor may discharge, and then, due to dielectric absorption or the circuitry around the capacitor, become charged again. To make sure the capacitor is discharged, you can loop the discharge block until the return variable of the discharge statement is less than or equal to 1:

looptest "analog/discharge_C1"; Returnexit if Return <= 1

end loop

To be sure this does not cause an infinite loop, limit the number of times the loop can be executed. If the discharge is still not successful after the maximum number of loops, stop the test:

Count = 1loop

test "analog/discharge_C1"; Returnexit if Return <= 1exit if Count > 10Count = Count + 1

end loopif Count > 10 then goto Cleanup

Note that the entry voltage level must be greater than or equal to the exit voltage level.

© A 2-29

An

A xplicit test block

nnect s to "R1-1"; i to "R1-2" 10K, 1.4, 1.4, re5, wb

mplicit test block

ct s to "R1-1"; i to "R1-2"K, 1.4, 1.4, re5, wb

pment software writes only implicit test

meters

cit test blocks can only use local u want to pass parameters either into, or lock you must use an explicit test block.

t to pass a parameter into a test block to lly control some of the measurement a parameter from the test block to the uate the result of a measurement. See


alog Test Blocks

nalog Test Blocks The analog test blocks contain the statements used to connect the device under test into the MOA circuit and execute the measurement. They may also contain an on failure loop to report a failure message, and possibly exit the test. These test blocks reside in the analog directory under the local board directory. For example:

/test_board/analog/r1

Every test block contains at least a clear connect statement and a measure statement such as resistor or capacitor. Additional statements may be:

■ test analog ■ end test ■ on failure ■ end on failure ■ report ■ print ■ exit test

This section describes:

• Explicit and Implicit Test Blocks• Passing Parameters• Multiple Measurement Test Blocks• Failure and Parallel-Device Reporting

Explicit and Implicit Test Blocks

There are two types of test blocks: explicit and implicit. The explicit blocks are delimited by the test analog and end test statements; the implicit blocks are not delimited.

Example 2-11 E

test analogclear coresistor

end test

Example 2-12 I

clear conneresistor 10

The test develoblocks.

Passing Para

Note that implivariables. If yoout of, the test bYou might wanprogrammaticaoptions, or passtestplan to evalExample 2-13.

© A 2-30

An

asurement must have a unique

st Block

ple of an analog test block for a he 10K ohm potentiometer is measured

measurement checks the resistance from iper using the ad (adjust) option to allow center the wiper. The second hecks the resistance from the other leg to ut the ad option. The result of both re compared to half the nominal value.

asurement wider tolerances to ny inaccuracy in the adjustment.

otentiometer test block

s to "Pin_1"; i to "Wiper" "Leg_1", 5k, 13.2, 12.5, wb, ad s to "Wiper"; i to "Pin_3" "Leg_2", 5k, 26.3, 24.4, wb, ed

measurement has a unique

ple of a switch test for a dual ble-throw switch. One side of each red for less than 5 ohms with the ad

the operator to set the switch. The other itch is measured to be greater than 100K


alog Test Blocks

Example 2-13 Passing a parameter to the test block

Testplan:

Ed_Flag = 0test "analog/R1"; Ed_Flag

Test Block:

test analog; Ed_Flagclear connect s to "R1-1"; i to "R1-2"resistor 10K, 1.4, 1.4, re5, wb, ed Ed_Flag

end test

Passing a parameter to the testplan:

Testplan:

test "analog/R1"; Rif R < 7000 then print "R1 Failed"

Test Block:

test analog; Returnclear connect s to "R1-1"; i to "R1-2"resistor 10K, 1.4, 1.4, re5, wb, Return

end test

Multiple Measurement Test Blocks

The test development software writes implicit test blocks containing one measurement per block. This is the way all analog in-circuit test blocks should be written, including blocks for elements of a package, such as a resistor pack. The only exception is a test that requires more than one measurement, where one measurement depends on the results of one prior to it. Such is the case for a potentiometer or switch test. In this case, all measurements are included in one test

block. Each mesub-designator.

Potentiometer Te

This is an exampotentiometer. Ttwice. The firstone leg to the wthe operator to measurement cthe wiper withomeasurements aThe second meaccommodate a

Example 2-14 P

clear connectpotentiometerclear connectpotentiometer

Notice that eachsub-designator.

Switch Test Block

This is an examsingle-pole-douswitch is measuoption to allowside of each swohms.

© A 2-31

An

failure report:

port "PART ;LOCATION:L2" s to "R1-1"; i to "R1-2" 1.4, 1.4, re5, wb

failure and parallel devices report:

T NUM: 1145-0916; LOCATION: L2"llel devicese s to "R1-1"; i to "R1-2" 1.4, 1.4, re5, wb

one-line on failure statement does not failure statement. You can have one and report statements, each one cancels e. This is also true for on failure

n a Failure

st block contains more than one nd each one depends on the results of the this case, if the first measurement fails, easurements also fail. You can use the ement to exit the test block after the first at fails. This avoids executing all urements. Consider Example 2-17.


alog Test Blocks

Example 2-15 Switch test block

clear connect s to "Node_A"; i to "Node_B"switch "Pos_A", 5, ad1clear connect s to "Node_A"; i to "Node_C"switch "Pos_B", 100K, opclear connect s to "Node_D"; i to "Node_E"switch "Pos_C", 5, ad1clear connect s to "Node_D"; i to "Node_F"switch "Pos_D", 100K, op

Notice that each measurement has a unique sub-designator.

Failure and Parallel-Device Reporting

You can specify a failure message from within the test block with the on failure loop. If your on failure statement is on one line, you do not need the end on failure; if your on failure statement requires more than one line, you must use the end on failure statement. The test development software places the contents of the failure message field into a report statement in the analog test block. The software also adds a parallel devices report, if the device under test has devices in parallel.

Example 2-16

Test block with

on failure reNUM:1145-0916clear connectresistor 10K,

Test block with

on failurereport "PARreport para

end on failurclear connectresistor 10K,

Notice that the use the end onor more print the previous onloops.

Exiting the Test o

Sometimes a temeasurement, aone before it. Inall following mexit test statmeasurement thfollowing meas

© A 2-32

An


alog Test Blocks

Example 2-17

on failurereport "Device failed."exit test

end on failureclear connect s to "Node_1"; i to "Node_2"resistor "Div_1", 5k, 13.2, 12.5, wb, Rclear connect s to "Node_2"; i to "Node_3"resistor "Div_2", 10k-R, 26.3, 24.4, wb, ed

The second measurement uses the value of R from the first measurement. If the first measurement fails, the second one also fails. In this example the test exits after the first failure. Use the off failure statement to disable an on failure loop.

© A 2-33

In-

InStSu

s to nodes or brc's.

e loop.

ides with the BT-BASIC gpconnect ments for details.

ides with the BT-BASIC gpdisconnect ments for details.


Circuit Test Statement Summary

-Circuit Test atement mmary

Table 2-5 and Table 2-6 on page 2-34 list the statements commonly used with in-circuit tests. These are not meant to be exhaustive lists.

Table 2-5 Analog mode

Command Result

capacitor Measures fixed or variable capacitors.

connect-unpowered Connects specified buses to nodes or brc's.

clear connect-unpowered Disconnects all buses then connects specified buse

disconnect-unpowered Disconnects specified nodes or brc's.

discharge Discharges capacitors.

diode Measures forward bias diode or zener voltage.

end on failure Marks the end of an on failure loop.

end test Delimits the end of a test block.

exit test Exits a test block. Usually used with an on failur

fuse Verifies the presence of fuses.

gpconnect Closes the specified GP relay. This statement coincstatement. See the syntax descriptions of both state

gpdisconnect Opens the specified GP relay. This statement coincstatement. See the syntax descriptions of both state

inductor Measures fixed or variable inductors.

jumper Verifies the presence of jumpers.

nfetr/pfetr Measures Ron of N-channel and P-channel FETs.

© A 2-34

In-

easuring two values of DC base current.



npn/pnp Calculates the gain of npn and pnp transistors by m

off failure Turns off an active on failure statement.

on failure Marks the start of an on failure loop.

potentiometer Measures potentiometer resistance.

print Outputs a message to the printer is device.

report Outputs a message to the report is device.

resistor Measures fixed or variable resistors.

switch Verifies the contact position of a switch.

test analog Delimits the start of a test block.

zener Measures zener reverse breakdown voltage.

Table 2-5 Analog mode (continued)

Command Result

Table 2-6 BT-BASIC

Command Result

analog Invokes the analog mode.

gpconnect Closes specified general purpose relays.

gpdisconnect Opens specified general purpose relays.

learn capacitance off Turns off the capacitance learning.

© A 2-35

In-

ompensation is activated for the tests that t and the following learn capacitance off

a stimulus and taking a reading for all

tatements. The tolerance margin st limits. If no value is specified, the value

nts, and executes the capacitor discharge



learn capacitance on Turns on the capacitance learning. The capacitance care executed from the testplan between this statemenstatement.

minimum wait Specifies a wait interval, in seconds, between applyinganalog in-circuit tests.

printer is Specifies the printer device.

report is Specifies the report device.

test Executes the specified test block.

test cont Continues a test after a pause.

tolerance margin Changes the test limits specified in the in-circuit test sstatement can be used to increase or decrease the teused is 0.

unpowered Initializes the system to execute in-circuit test statemeblock.

Table 2-6 BT-BASIC (continued)

Command Result

© A 2-36

Th

ThOA

hardware configuration for performing cuit test.

s, see the following topics:

ing the Operational Amplifiermp Equations

etector


e Measuring Operational Amplifier (MOA)

e Measuring perational mplifier (MOA)

The ASRU Card contains the sources, detectors, and the MOA circuit used for in-circuit testing. Figure 2-18

shows the basican analog in-cir

Figure 2-18 Analog in-circuit test configuration

The component under test is represented by resistor Rx. Under control of the test program, Pin Card and ASRU Card relays switch the component to be tested into the MOA circuit. When stimulus source voltage, Vs, is applied, the MOA output is measured by a detector to determine the value of the component, Rx.

For more detail

• Understand• Basic Op-A

ControlCard

PinCard

Test Fixture

Rx

TestheadRelays

PC Board

ASRU Relay

SourceVs

Rref

ASRU Relay

MOA

MOA Circuit on the ASRU Card

D

© A 2-37

Th

characteristics for the op-amp, the ormula for an op-amp is:

e output voltage of the op-amp, Vs is the voltage, Rx is the component under test, eedback resistor.

oltage gain equation does not take into f the non-ideal circuit conditions. strates a basic op-amp circuit, and some

it conditions in terms of currents and

Rref)

x----------



Understanding the Operational Amplifier

To understand how the MOA on the ASRU Card is used to test analog components, an understanding of the operational amplifier (op-amp) circuit is necessary. Understanding the op-amp and how it is used as a measurement tool by the Agilent In-Circuit Test System is useful when you are verifying and editing component tests. It also helps you identify possible measurement problems caused by circuit topology on the board under test.

The electrical characteristics of the operational amplifier make it ideal for testing analog components. An ideal op-amp exhibits the following:

■ Infinite gain.■ Infinite bandwidth.■ Infinite input impedance.■ Zero input current.■ Amplifier parameters (gain, bandwidth, etc.) are

stable at all temperatures.

These characteristics are the reason the operational amplifier is selected to perform measurements rather than a voltmeter or an ohmmeter. Those instruments can give erroneous results when doing in-circuit measurements because they cannot compensate for components in parallel with the component under test. In comparison to these instruments, the op-amp can use small stimulus voltages when performing tests. The DC stimulus voltage for an in-circuit test is 0.1 volt. Using such a small stimulus prevents any PN junctions in surrounding devices from being turned on.

Assuming idealtextbook gain f

where Vmoa is thinput (stimulus)and Rref is the f

However, the vaccount some oFigure 2-19 illunon-ideal circuvoltages.

VmoaVs(

R---------–=

© A 2-38

Th

Equations

ations can be derived from the current es in the op-amp circuit. From Kirchoff's sum of currents entering and leaving a o. Therefore, referring to Figure 2-19:

nd (4) are derivations of Ohm's Law ion (2) can be rewritten using equations ubstituting values for I and (I - Ib).

ming node N = 0

I Ib–( )+

in)------- I=

moa)

f------------- I Ib–( )=



Figure 2-19 Currents and voltages in a basic op amp circuit

The basic circuit components consist of the op-amp, an input resistor, Rx, and a feedback resistor, Rref. If a source voltage, Vs, is applied at the circuit input, current I flows through Rx. This current also flows into the summing node, N. If the op-amp exhibits the ideal characteristic of an infinite input impedance, all of the current, I, also flows through the feedback resistor, Rref. However, because no op-amp is perfect, a very small bias current, Ib, flows into the inverting input. Ib is considered an error current because ideally, all of the current should flow through the feedback resistor. The remaining current, (I -Ib), flows through the feedback resistor, Rref.

Figure 2-19 also illustrates the voltages in the op-amp circuit. The voltage drop Vin is an error voltage across the inputs of the op-amp caused by the error current Ib. Vmoa is the output voltage of the op-amp.

Basic Op-Amp

Some basic equflow and voltagcurrent law, thenode equals zer

Equations (3) a(I = E/R). Equat(3) and (4) by s

SummingNode

NRx

I

Vs SourceVoltage

Vin

Ib

I-IbRref

MOAVmoa

I at sum

I Ib=

Vs V–(Rx

----------------

Vin V–(Rre

----------------

(1)

(2)

(3)

(4)

© A 2-39

Th

owever, does not always work for all rements. The component topology of test can sometimes exaggerate the cteristics of the op-amp, and the MOA al. When the system encounters a rement situation, an expanded equation uation (7) is used. Use of the expanded

quation is referred to as Enhancement.



If both sides of equation (5) are divided by (Vs - Vin), the new equation is:

The value of Rx can be found by inverting both sides of equation (6) which gives the equation:

To further simplify equation (7), some assumptions can be made concerning the MOA circuit. The first of these assumptions is that the error current Ib is so small that it is insignificant, and this value in the equations can be set to zero. If Ib is small, then the voltage drop it causes, Vin, is also small enough to be insignificant, so it too can be set to zero. These assumptions are shown in equation (8).

Equation (8) is the one most often used by the system to calculate the value of Rx, and is merely a transposed version of the op-amp voltage gain equation:

Equation (9), hin-circuit measuthe board undernon-ideal characircuit in generdifficult measuequivalent to eqmeasurement e

Vs Vin–( )Rx

----------------------- IbVin Vmoa–( )

Rref-----------------------------+=(5)

(6)1

Rx-----

Ib Vin Vmoa–( )+

Vs Vin–( )Rref

---------------------------------------=

(7) Rx

Vs Vin–( )Rref

Ib Vin Vmoa–( )+---------------------------------------=

(8) RxVsRref( )

Vmoa–-------------------=

(9) VmoaVsRref–( )

Rx-----------------------=