-
An
Ana
log
DFE
for D
isk
Driv
esUs
ing
a M
ixed
-Sig
nal I
nteg
rato
rM
icha
el Q
. Le,
Pau
l J. H
urst,
and
Ken
neth
C. D
yer
Solid
-Sta
te C
ircui
ts R
esea
rch
Labo
rato
ryD
ept.
of E
lect
rical
and
Com
pute
r Eng
inee
ring
Unive
rsity
of C
alifo
rnia
, Dav
is
-
DFE
Bac
kgro
und
Mea
sure
d Re
sults
Circ
uits
Mix
ed-S
igna
l Int
egra
tor
Out
line
-
Rea
d Si
gnal
Lore
ntzi
an m
odel
s iso
late
d tra
nsitio
n:
Bina
ry D
ata:
Mag
netiz
atio
n:
Rea
d Vo
ltage
:
01
01
11
00
0T
2T-T
-2T
Prec
urso
r ISI
Post
curs
or IS
I
-3T
3T
Curs
or
L(t ) =
1
1 +
( )
2tPW
50
2
Rec
eive
d sig
nal is
a s
uper
posit
ion
of L
(t )
-
Bloc
k D
iagr
am o
f DFE
Rea
d Ch
anne
l
LPF
Forw
ard
Equa
lizer
Feed
back
Equa
lizer
Prea
mp
& AG
C
DFE
Equa
lizer
s re
mov
e in
ters
ymbo
l inte
rfere
nce
(ISI)
Anal
og e
qual
izers
sav
e ar
ea a
nd p
ower
ove
r dig
italOu
tR
ead
Hea
d
-
Mix
ed-S
igna
l DFE
Arc
hite
ctur
e
Inpu
t(fr
om FE
)Qu
antiz
er
+_
1
e[n]
= err
or
[n] =
decis
ion
Inte
grat
or
cc
c c
c1
23
40
c
1x
-1
z-1
z-1
z-1
z
[n] =
sign
(erro
r)
11
xx
xx
1/10
00
x
-
Dis
cret
e-Ti
me
Inte
grat
ors
10-b
it U/
DCo
unte
r Ana
log
Inte
grat
or
[n][
n-k
]
[n][
n-k
]6-
bit U
/DCo
unte
rCa
rry
Borro
w6-
bit
DAC
6-bi
tD
AC
[n][
n-k
]4-
bit P
reCo
unte
ru
p down
ck
ck
ck
Carry
Borro
w
4-bi
t Pre
Coun
ter
-
Mix
ed-S
igna
l Int
egra
tor
4-b
Pre-
coun
ter
Char
ge P
ump
Carry
Borro
wre
set
OR
[n][
n-k]
U D
4-b
U/D
Coun
ter
I 1 I 2
c k
C H
c [n
+1]
= c
[n] +
(U-D
)
+ (U
+D)
kk
I
tC HI
tH
2Coff
Pre-
coun
ter D
C ga
in =
1 7I o
ff2I
1 7O
ffset
@ d
igita
l inpu
t
I off
2I(fr
eq U
=1
or D
=1)
(coun
ter D
C ga
in)
-
Anal
og D
FE A
rchi
tect
ure
(from
FE)
2-bi
t Fla
sh A
DC
1-1
VRH
VRL
I2V
++
[n]
= err
or
[n]
= de
cisio
n
1
Mix
ed-S
igna
l Int
egra
tor
cc
c
c
c1
23
40
c
1
-1
z-1
z-1
z-1
z
+
I fb
I in
_ _ _
xx
xx
x x
-
Char
ge P
ump
UD
N
UBD
BN
B
+C
-C
VGG
I 2I 1
Com
mon
-mod
e fe
edba
ck c
ontro
ls I
Use
gate
-cha
nnel
cap
acita
nce
of P
MO
S tra
nsist
ors
Curre
nt s
ourc
es h
eld
in s
atur
atio
n by
N/N
B
2
kk
-
Curre
nt to
Vol
tage
Con
verte
r (I2V
)
Tran
sres
ista
nce
of 6
00
se
t by
load
resis
tors
Neg
ative
feed
back
redu
ces
inpu
t im
peda
nce
A+
-+-
Vdd
In+
In-
Bias
Bias
600
60
0
M1
M2
Out
+O
ut-
-
Test
Set
up
Ran
dom
Bina
ry D
ata
1 - z-1
Lore
ntzi
anPW
=
2T
50Fo
rwar
dEq
ualiz
er
AWG
Band
limite
dN
oise
Anal
ogD
FELo
gic
Anal
yzer
Cloc
k G
ener
ator
-
Equa
lized
Slic
er In
put a
t 10M
b/s
050
010
0015
00
1.5
1
0.
50
0.51
1.5
Sam
ple
Normalized Input
-
BER
Per
form
ance
Bit-Error Rate
SNR
at D
FE In
put (d
B)10
1112
1314
1516
171e
-12
1e-1
1
1e-1
0
1e-0
9
1e-0
8
1e-0
7
1e-0
6
1e-0
5
1e-0
4
1e-0
3
Idea
l Slic
er w
ith n
o IS
IM
easu
red
at 1
00 M
b/s,
PW
50 =
2T
Mea
sure
d at
150
Mb/
s, P
W50
= 2
T
-
differential voltage (V)
time
(s)
00.
51
1.5
2
1
0.
50
c 1cccc 3 240
differential voltage (V)
time
(s)
00.
51
1.5
2
1
0.
50
c 1cccc 3 24 0
Coef
ficie
nts
with
Pre
-cou
nter
s @
150
Mb/
s
Coef
ficie
nts
with
out P
re-c
ount
ers
@ 1
50 M
b/s
-
Conv
erge
nce
with
out P
re-c
ount
ers
@ 1
50 M
b/s
00.
51
1.5
2
1
0.
50 02
46
810
12
1
0.
50
differential voltage (V)differential voltage (V)
Conv
erge
nce
with
Pre
-cou
nter
s @
150
Mb/
stim
e (s
)
time
(s)
~18
0T
~12
00T
c 1ccc 3 24c1
ccc3 24
-
Tech
nolo
gy
Core
Are
a
Pow
er D
issi
patio
n22
0 m
W @
150
Mb/
s
Num
ber o
f Tap
s4
ISI +
1 D
C of
fset
SNR
requ
ired
for
-8
BER
= 1
x 1
0 15
.3 d
B @
100
Mb/
s16
.0 d
B @
150
Mb/
s
1 m
CM
OS
1.8
mm
2
Perfo
rman
ce S
umm
ary
(5V, 2
5 C,
PW
= 2
T)o
50
