AN1452 - Using the MCP19035 Synchronous Buck …ww1.microchip.com/downloads/en/AppNotes/01452A.pdf · · 2012-11-09Using the MCP19035 Synchronous Buck Converter Design Tool. ...

AN1452Using the MCP19035 Synchronous Buck Converter Design Tool

INTRODUCTIONThe MCP19035 is a high-performance, highlyintegrated, synchronous buck controller IC, packagedin a space-saving, 10-pin 3x3mm DFN package.Integrated features include high- and low-sideMOSFET drivers, fixed-frequency voltage-modecontrol, internal oscillator, reference voltage generator,overcurrent protection circuit for both the high- andlow-side switches, Power Good indicator andovertemperature protection. The development of acomplete, high-performance synchronous buckconverter requires a minimum number of externalcomponents. Some design effort is still necessary tocalculate all the external component’s (inductor,MOSFETs, capacitors, compensation network) valuesand parameters.

This application note familiarizes the designer withMicrochip's MCP19035 Synchronous Buck ConverterDesign Tool. Microchip Technology Inc. provides thisdesign tool to minimize design effort and to help thedesigner estimate the static (i.e., the efficiency) anddynamic (load step response) performance, and thebehavior of the step-down voltage regulatorimplemented with the MCP19035 controller.

BACKGROUND

The Synchronous Buck ConverterThe synchronous buck converter is an improvedversion of the classic, non-synchronous buck (step-down) converter. This topology improves the lowefficiency of the classic buck converter at high currentsand low-output voltages. Figures 1 and 2 illustrate thepower trains for the classic buck, and synchronousbuck converter.

FIGURE 1: Classic Buck Converter Power Train.

FIGURE 2: Synchronous Buck Converter Power Train.

Author: Sergiu OpreaMicrochip Technology Inc.

VIN COUT

L

Q

RLD+-

VIN COUT

L

RLD

Q1

Q2+-

2012 Microchip Technology Inc. DS01452A-page 1

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The freewheeling diode of the classic buck converter isreplaced with a MOS transistor in the synchronousbuck converter. This greatly reduces the conductionlosses when the converter operates at high-currentswith low-output voltages.

Since the synchronous buck converter is developed todeliver high output currents, it will mainly operate in theContinuous Current Mode (CCM). This application noteassumes that the synchronous buck converter onlyoperates in the CCM mode.

The design process for a synchronous buck voltageregulator is split into two phases. In the first phase, theelectrical parameters of the power train components(inductor, MOSFETs and capacitors) are calculatedbased on the target application needs provided by thepower supply designer. Further, this design tool canestimate the power components’ losses based on theparameters provided by the designer.

In the second phase, the design tool analyzes the AC(small signal) frequency response of the system andproposes a set of component values for the compensa-tion network. The designer has the option to adjust thevalue of these components, if the frequency responseof the compensated system does not meet the designtargets.

The MCP19035 synchronous buck controllerimplements the voltage-mode PWM control. For thiskind of control strategy, a Type-III Compensationsystem is recommended.

Based on these input parameters, the Design Toolcalculates the system parameters and the power traincomponent values (inductor, input and outputcapacitors values).

FIGURE 3: Type-III Compensation Network.

Appendix A: “List of the Design Tool Formulas”lists the equations used by this design tool.“Fundamentals of Power Electronics” [1] provides allthe theoretical background for the synchronous buckconverter operation.

THE MCP19035 SYNCHRONOUS BUCK CONVERTER DESIGN TOOL

Design Tool Input

In the first tab of the Design Tool, the designer providesthe system input parameters, including the input andoutput voltages, maximum output current, switchingfrequency, input voltage ripple and the referencevoltage. Also, the step load parameters must beprovided here. An example of the input parameters aresummarized in Figure 4.

FIGURE 4: Input Parameters Table.

C1 R3

C3

R1R2

C2R4

+

-EAVIN

COMP

VREF

Parameter Designator Units Notes

Input Voltage VIN 14 V 5V ≤ VIN ≤ 30VOutput Voltage VOUT 1.8 VOutput Current IOUT 10 A

Switching Frequency Fs 600000 Hz Fs = 300 kHz or 600 kHzInput Voltage Ripple VRIN 0.2 VReference Voltage VREF 0.6 V

Step Load ParametersIOH IOH 7.5 AIOL IOL 2.5 A

Output Voltage Overshoot 0.1 V

Input Parameters for Design

DS01452A-page 2 2012 Microchip Technology Inc.

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The second tab of the Design Tool summarizes thesystem parameters. The Power Train Componentstable contains two color-marked columns:

• Suggested Values (green highlight) – shows the values calculated by the Design Tool

• Standard Values (yellow highlight) – the designer

completes these fields with the available standard component values

To minimize error and ensure the best possiblerepresentation of the system's performance, all furthercalculations are done based on the user-input standardvalues of the power train components.

FIGURE 5: The Power Train Components Values Table.

The Design Tool calculates the RMS currents for theinductor, high- and low-side MOSFETs, and both inputand output capacitors. Using these RMS currents thedesigner determines the power train component’sparameters (MOSFETs, inductor and capacitors)following the recommendations from the MCP19035data sheet. Components’ parameters are thenmanually entered into the Power Train ComponentsParameter table (Figure 6). Based on theseparameters, the Design Tool estimates the losses andthe expected efficiency of the converter (Figure 7).

The RDSON, total gate charge and reverse recoverycharge of the body diode parameters are available inthe MOSFET’s data sheet. Refer to the MCP19035Data Sheet for further details on MOSFETs’ selection.

The total conduction time for the body diode will varybetween 20 ns (set by the internal logic of theMCP19035) and a maximum value that depends on theMOSFET’s type for the MCP19035 version withadaptive Dead Time option. The total conduction timefor the body diode cannot be accurately determinedfrom the beginning of the design. The designer caninitially use the 40 ns value. For the fixed Dead Timeoption of MCP19035, optimized to drive Microchip'sMOSFETs, this value is fixed to 12 ns.

The DC resistance of the inductor and the equivalentseries resistance (ESR) of the capacitors are alsoavailable in each component data sheet.

FIGURE 6: Power Train Components Parameters Table.

Suggested Values Standard Values (**) Units

0.87 1 μH135.1 200 μF

10 20 μF0.276 0.33 μF

* COUT is calculated based on standard value for inductor and not for suggested value** Must be filled by the designer

Power Train Components Values (calculated)Component

Inductor ValueCOUT(*)

CIN

CBOOT

Component Parameter Designator Units

High side MOSFETRDS(ON) RDS(ON)HS 6 m

Total gate charge QGATEHS 13.8 nC

Low side MOSFETRDS(ON) RDS(ON)LS 2.5 m

Total gate charge QGATELS 31 nCTotal Conduction Time for the Body Diode tBD 12 ns

Reverse Recovery Charge of the Body Diode QRR 35 nC

Inductor DC Resistance LDCR 2 mCIN ESR 10 m

COUT ESR 5 m

Power Train Components Parameters


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The Design Tool estimates the losses and the finalefficiency of the converter (see the table in Figure 7).The designer can modify several parameters of thepower train components in an effort to optimize theefficiency of the converter. The estimated efficiency willdepend on the accuracy of the parameters. Some

difference between the predicted value and themeasured value should be expected. Certain types oflosses (for example, hysteresis losses of the inductor)are not calculated by the Design Tool. Refer to theinductor data sheet for details regarding these types oflosses.

FIGURE 7: Losses and Expected Efficiency Table.

Loop Compensation

The next step in the design is to stabilize the controlloop. On the third tab, the Design Tool calculates thevalues of the compensation network componentsaccording with the design procedure described in theMCP19035 data sheet. The designer can also analyzethe stability and the dynamic performance of theconverter using the Frequency Domain Analysis tab inthe Design Tool.

Bode Plots

The Bode plots method is an important engineering toolthat can be used for frequency domain analysis of theclosed loop systems. Stability and dynamicperformance of closed-loop systems can also beestimated using these plots. A Bode plot is the graphrepresenting the magnitude and/or phase of a transferfunction, or other complex-domain quantity versusfrequency. The magnitude, expressed in decibels, andthe phase, expressed in degrees, are plotted on alogarithmic frequency scale.

If H(s) is the transfer function of a linear, time-invariantsystem, the magnitude and phase are shown in thefollowing equations:

EQUATION 1: GAIN

EQUATION 2: PHASE

The gain and phase can now be plotted on alogarithmic frequency scale. These are the Bode plotsof the given transfer function.

Similarly, if the converter closed-loop transfer functionis known, the Bode plots can be used to analyze thestability and dynamic performance of the system.

The Design Tool uses the Average Model of the buckconverter developed in “Fundamentals of PowerElectronics”[1]. The frequency response of thecompensated system is obtained by multiplying thefrequency response of the power train with thefrequency response of the compensator (seeEquation 3).

High side MOSFET lossesConduction losses 0.08 WSwitching losses 1.1592 W

Total losses 1.2392 WLow Side MOSFET losses

Conduction losses 0.2 WBody diode conduction losses 0.0504 W

Body diode reverse recovery losses 0.147 WTotal losses 0.3974 W

Controller losses 0.4 WInductor conduction losses 0.2 W

COUT losses 0.015 WCIN losses 0.05 W

Total losses 2.3016 WEstimated Efficiency at Full Load 88.7 %

Estimated System Losses

G dB 20 H s log=

Phase H s Im H s Re H s -----------------------atan=


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FIGURE 8: The Synchronous Buck Regulator System.

EQUATION 3: FREQUENCY RESPONSE OF THE COMPENSATED SYSTEM

The Design Tool plots the Bode plots for power train,compensation circuit and compensated converter.

FIGURE 9: Bode Plots of the Power Train.

FIGURE 10: Bode Plots of the Compensation Circuit.

FIGURE 11: Bode Plots of the Compensated System.

The designer can now estimate the stability anddynamic performance of the system by inspecting theBode plots.

The first parameter of interest is the system’s crossoverfrequency. The crossover frequency is the point wherethe gain of the system becomes 0 dB. A highercrossover frequency means a better dynamicperformance of the system (better transient response).However, due to the stability criteria, this crossoverfrequency cannot be set infinitely high.

Phase margin is the second parameter of interest, anddirectly related to the stability of the closed loopsystem. In a closed loop system that uses negativefeedback, the phase margin is defined as the differencebetween the phase at the crossover frequency and 0°.

The third parameter is the gain margin. This parameteris also related to the system stability and will indicatehow far the system is from the instability point (0 dB).The gain margin is defined as the amount of gain thatmust be added to the system gain to reach the 0 dBpoint, calculated at the point where the phasereaches 0°.

The Design Tool automates the calculation of thesethree parameters and plots the results. The designercan use these parameters to evaluate the stability ofthe closed loop system.

FIGURE 12: Closed Loop System Parameters.

+-

VIN

VOUT

Power TrainHP(S)

PWMModulator

HM(S)

CompensatorC(S)H

HS s HP s HM s HC s =

-200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20

-60 -50 -40 -30 -20 -10

0 10 20 30 40 50 60

10 1000 100000

PHA

SE (D

egre

es)

GA

IN (d

B)

FREQUENCY (Hz)

Bode Plots of the Power Train

Gain Phase

-100 -80 -60 -40 -20 0 20 40 60 80 100

-20 -10

0 10 20 30 40 50 60 70 80

1 100 10000 1000000

PHA

SE (D

egre

es)

GA

IN (d

B)

FREQUENCY (Hz)

Bode Plots of the Compensator

Gain Phase

-80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

-90 -70 -50 -30 -10 10 30 50 70 90

1 100 10000 1000000

PHA

SE (D

egre

es)

GA

IN (d

B)

FREQUENCY (Hz)

Bode Plots of the Compensated System

Gain Phase

Fcrossover 63000 HzPhase Margin 62 1 Degrees

y

Phase Margin 62.1 DegreesGain Margin 22.9 dB


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FIGURE 13: Phase Margin.

FIGURE 14: Gain Margin.

Stability Criterion

The designer can estimate if the closed loop system isstable by verifying if the phase and gain margin fulfillsthe Nyquist stability criterion. The criterion states that aclosed loop system is asymptotically stable if:

• Phase margin is greater than 0°

• Gain margin is greater than 0 dB

However, for a real system where noise and high-ordereffects are present, these limits must be modifiedaccording to the following rules:

• Phase margin must be greater than 45°

• Gain margin must be greater than 6 dB

The larger the values, the better stability. At the sametime, the system becomes slower, with poor dynamicresponse to an external perturbation. A system withlower phase and gain margins offer a faster transientresponse, but is more sensitive to noise and canbecome unstable.

Noise, Compensation And Stability in Practical Systems

The Design Tool uses an ideal, linearized model that isnot able to include and analyze all phenomena presentwithin a real-world, step-down PWM converterapplication. Some effects, such as the delaysintroduced by the PWM modulator, Error Amplifierbandwidth and switching elements (MOSFETs), canproduce additional phase lag, decreasing the phasemargin of the compensated system. A safe way toavoid these effects is to design the regulator with aphase margin greater than 50° using the Design Tool.

The power train passive components (inductor, inputand output filter capacitors) may have large tolerances.The values are also affected by the operatingconditions: inductor’s inductance varies with thecurrent, and the capacitance of the ceramic capacitorsvaries with the operating voltage. It is highlyrecommended to check the stability of the system for alllimits of components tolerances. In general, theinductance of the inductor drops when the currentincreases. This variation also depends on the magneticmaterial that is used for the core. The capacitance ofthe ceramic capacitor decreases if the voltage acrossthe terminals increases. All the variation curves areprovided in the component’s data sheet and must beverified by the designer.

As previously mentioned, setting the crossoverfrequency high results in faster transient response. Ifthe crossover frequency is too high, the system controlloop can become sensitive to noise even if it is stillstable (i.e., the phase margin exceeds 45°). The noisethat passes through the loop will adversely affect thePWM modulator, producing a jitter on the high and low-side driver's signals and impact the output voltageripple.

Figure 15 captures this noisy behavior. The low andhigh-side driver's signals have jitter, and the outputvoltage ripple is higher than in normal operation. Thisbehavior can also occur at high input voltages becausethe gain of the PWM modulator increases with the inputvoltage. The designer must reduce the crossoverfrequency of this system to avoid this behavior at highinput voltages. Notice that this noisy behavior may alsooccur when the system runs near the CriticalConduction Mode, where the current in the inductorreaches zero. In this case, the power train becomes afirst-order system (versus a second-order system,typical for voltage-mode control PWM buck regulators)resulting in an overly-aggressive gain profile of theType-III compensator, which introduces noisy behavior.In practice, however, this instability will not affect theperformance of the system, and can be safely ignored.

-80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

-90 -75 -60 -45 -30 -15

0 15 30 45 60 75 90

1 100 10000 1000000

PHA

SE (D

egre

es)

GA

IN (d

B)

FREQUENCY (Hz)

Gain Phase

FCrossover

Phase Margin

-80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

-90 -75 -60 -45 -30 -15

0 15 30 45 60 75 90

1 100 10000 1000000

PHA

SE (D

egre

es)

GA

IN (d

B)

FREQUENCY (Hz)

Gain Phase

FCrossover

Gain Margin


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FIGURE 15: The Noisy System.

The designer must verify that the converter is stableover the entire input voltage range. Figure 16 shows anunstable system. A sinusoidal oscillation issuperimposed over the output voltage. This sinusoidaloscillation has a frequency equal to the systemcrossover frequency. The amplitude of this sinusoidaloscillation will vary with the input voltage and outputcurrent. This kind of instability is always related to thecompensation loop, and is mostly produced by lowphase and gain margins.

FIGURE 16: The Unstable System.

Design Summary

The fourth tab of the Design Tool provides the designsummary. This page lists all the values for the powertrain and compensation network components, together

with a typical application schematic. The frequencyanalyses results and the estimated, full-load efficiencyare also plotted.

FIGURE 17: The Design Summary.

+VIN

ON

OFF

C2

C3R4

R2 C1

R3

R1

CVCC

+VOUT

COUT

INC

Q1

Q2

CBOOT

BOOT

HDRV

PHASE

LDRV

+VCCFB

COMP

PWRGD

VIN

SHDN

MCP19035

L 1 µHCIN 20 µF

COUT 200 µFCBOOT 0.33 µF

R1 20 k�R2 10 k�R3 0.75 k�R4 8.2 k�C1 0.68 nFC2 3.9 nFC3 0.033 nF

63000 Hz62.1 Degrees22.9 dB

88.7 %

FCROSSOVER

Phase MarginGain Margin

Estimated Efficiency at Full Load


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STEP-BY-STEP DESIGN EXAMPLE

This section presents a practical design example usingthe MCP19035 Synchronous Buck Converter DesignTool.

The project implies the design of a step-down,synchronous buck converter using the MCP19035. Thesystem has the following input parameters:

For the input voltage, enter the maximum value. Thiswill ensure that the current ripple in the inductor will bemaintained at 30% of the maximum output current athigh-input voltages.

Due to the space constraints of the final application, theconverter must be compact, while maintaining highefficiency. The load that must be powered from thisconverter will produce a step load between 2.5A and7.5A. The maximum output voltage overshoot duringstep load must be lower than 100 mV.

For this application, the designer may choose the600 kHz switching frequency version with optimizeddead time. The higher switching frequency will helpminimize the power train component’s size, while theoptimized dead time option will increase the system’sefficiency.

Step 1: Introducing the Parameters

Start the MCP19035 Synchronous Buck ConverterDesign Tool. All the input parameters of the converterare introduced in the table on the first tab of the DesignTool.

TABLE 1: CONVERTER PARAMETERS

Parameter Value Unit

Input Voltage Range 8 – 14 V

Output Voltage 1.8 V

Maximum Output Current 10 A

Input Voltage Ripple 0.2 V

IOH (Step Load High Value) 7.5 A

IOL (Step Load Low Value) 2.5 A


TABLE 2: INPUT PARAMETERS FOR DESIGN

Parameter Designator Value(1) Unit Notes

Input Voltage VIN 14 V 5V = VIN = 30V

Output Voltage VOUT 1.8 V

Output Current IOUT 10 A

Switching Frequency Fs 600000 Hz Fs = 300 kHz or 600 kHz

Input Voltage Ripple VRIN 0.2 V

Reference Voltage VREF 0.6 V

Step Load Parameters

Step Load High IOH 7.5 A

Step Load Low IOL 2.5 A


Note 1: The values in this column must be filled in by the designer.


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Step 2: Calculate the Values

The second page of the Design Tool shows thecalculated values for various system parameters, suchas RMS currents for low- and high-side MOSFETs, theinductor and the input and output filtering capacitors(Table 3).

Fill in the standard values of the power train accordingto the recommendations provided by MCP19035’s datasheet. For example, the Design Tool calculates aninductor value of 0.87 µH and, based on therecommendations, the next standard value is 1 µH. Forthe capacitor, it is generally advisable to choose ahigher value, because ceramic capacitors have largetolerances and exhibit a negative capacitance variationwith voltage across the terminals.

To calculate the value of the bootstrap capacitor(CBOOT), the high-side MOSFET’s parameters must beintroduced in the Power Train Components Parameterstable (Table 4).

Choose the MOSFETs, inductor and filtering capaci-tor’s parameters, based on the RMS currents calcu-lated by the Design Tool and following therecommendations from the MCP19035 data sheet.These parameters must be entered in Table 4 (PowerTrain Components Parameters table).

Since this application requires high efficiency, Micro-chip's MCP87050 and MCP87022 MOSFETs will beused. The requested parameters are available in thecomponents’ data sheet. These MOSFETs are suitablefor use with the optimized dead time version of theMCP19035. In this case, the "Total Conduction Time forthe Body Diode" parameter is fixed, and equals 12 ns.

The DC resistance of the inductor and ESRs of theinput and output capacitors are entered in the sametable. All these parameters will affect the performanceof the converter and the designer must carefully selectthem, in concordance with the MCP19035 data sheet’srecommendations.

Based on the parameters of the power traincomponents, the Design Tool will estimate the systemlosses and the efficiency at full load. Note that thelosses are affected by the input voltage; the worst caseis at maximum input voltage, 14V in this case.

TABLE 3: POWER TRAIN COMPONENTS VALUES (CALCULATED)

ComponentSuggested

ValueStandard Value(2) Unit

Inductor Value 0.87 1 µH

COUT(1) 135.1 200 µF

CIN 10 20 µF

CBOOT 0.276 0.33 µF

Note 1: COUT is calculated based on the standard value for inductor and not for suggested value.

2: The values in this column must be filled in by the designer

TABLE 4: POWER TRAIN COMPONENTS PARAMETERS

Parameter Designator Value(1) Unit

High side MOSFET

RDS(ON) RDS(ON)HS 6 m

Total gate charge QGATEHS 13.8 nC

Low side MOSFET

RDS(ON) RDS(ON)LS 2.5 m

Total gate charge QGATELS 31 nC

Total Conduction Time for the Body Diode

tBD 12 ns

Reverse Recovery Charge of the Body Diode

QRR 35 nC

Inductor DC Resistance LDCR 2 m

CIN ESR 10 m

COUT ESR 5 m

Note 1: The values in this column must be filled in by the designer.


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Step 3: Frequency Domain AnalysisThe next step of the design is the frequency domainanalysis. This analysis can be performed on the thirdtab of the Design Tool. The Design Tool calculates thevalues of the compensation network componentsaccording to the procedures described in theMCP19035 data sheet (Table 6).

Enter the calculated values in the CompensationNetwork Components table (Table 7).

Based on these values, the Design Tool will plot theBode plots and calculate the crossover frequency,phase and gain margin of the compensated system.Adjust the values of the compensation networkcomponents to modify the frequency response of thesystem. Note that the frequency response of thesystem is affected by the value of the input voltage. It isadvisable to perform the frequency analyses for theentire range of the input voltage. The worst case occursagain at high input voltages because the PWMmodulator gain increases with the input voltage.

Step 4: Design Summary

The last tab of the Design Tool shows the summary ofthe design and the typical application schematic for thesynchronous buck regulator, based on the MCP19035device. The designer can generate the final schematicfor the step down regulator with these component’svalues.

TABLE 5: ESTIMATED SYSTEM LOSSES


High-Side MOSFET losses

Conduction losses 0.08 W

Switching losses 1.1592 W

Total losses 1.2392 W

Low-Side MOSFET losses

Conduction losses 0.2 W

Body diode conduction losses 0.0504 W

Body diode reverse recovery losses

0.147 W


Controller losses 0.4 W

Inductor conduction losses 0.2 W

COUT losses 0.015 W

CIN losses 0.05 W


Estimated Efficiency at Full Load 88.7 %

TABLE 6: COMPENSATION NETWORK CALCULATED VALUES

Calculated Values for the Compensation Network (1) Units

R1 20 k

R2 10 k

R3 0.75 k

R4 7.62 k

C1 0.71 nF

C2 3.71 nF

C3 0.035 nF

Note 1: The values with yellow background must be filled in by the designer. The ones with green background are calculated by the tool.

TABLE 7: COMPENSATION NETWORK COMPONENTS

Compensation Network Components (1) Units

R1 20 k

R3 0.75 k

R4 8.2 k

C1 0.68 nF

C2 3.9 nF

C3 3.30E-02 nF

Note 1: These values must be filled in by the designer.

TABLE 8: SYSTEM PARAMETERS


FCrossover 63000 Hz

Phase Margin 62.1 Degrees

Gain Margin 22.9 dB


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FIGURE 18: The Design Summary.

REFERENCES

1. Erikson, Robert W. and Maksimovic, Dragan –"Fundamentals of Power Electronics (SecondEdition)", ©2001, Springer Science andBusiness Media, Inc.

+VIN

ON

OFF

C2

C3R4

R2C1 R3

R1

CVCC

+VOUT

COUT

INC

Q1

Q2

CBOOT

BOOT

HDRV

PHASE

LDRV

+VCCFB

COMP

PWRGD

VIN

SHDN

MCP19035

L 1 µHCIN 20 µF

COUT 200 µFCBOOT 0.33 µF

R1 20 k�R2 10 k�R3 0.75 k�R4 8.2 k�C1 0.68 nFC2 3.9 nFC3 0.033 nF

63000 Hz62.1 Degrees22.9 dB

88.7 %

FCROSSOVER

Phase MarginGain Margin

Estimated Efficiency at Full Load


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APPENDIX A: LIST OF THE DESIGN TOOL FORMULAS

Parameter Name Equation

Inductor Value (H)(for 30% current ripple)

Inductor Peak Current (A)(for 30% current ripple)

Inductor RMS Current (A)

Minimum Capacitance for Input Capacitor (F)

RMS Current in the Input Capacitor (A)

Output Voltage Ripple (V)

Output Capacitor Minimum Value (F)

RMS Value for High-side Current (A)

Conduction Losses for High-side MOSFET (W)

Switching Losses for High-side MOSFET (W)

Total Power Losses for High-side MOSFET (W)

RMS Current for Low-side MOSFET (W)

Conduction Losses for Low-side MOSFET (W)

Body Diode Conduction Losses (W)

Body Diode Reverse Recovery Losses (W)

L VINMAX VOUT– VOUT

VINMAX------------------- 1

fSW-------- 1

0.3 IOUTMAX------------------------------------=

ILPEAK IOUTMAX

0.3 IOUTMAX2

------------------------------------+=

ILRMS IOUT2 IRipple

2

3----------------+=

CINMIN

IOUT D 1 D– fSW VRipple D IOUT ESR – ----------------------------------------------------------------------------------------=

IRMS CIN IOUT

IRipple

12----------------+

DVOUT IOUT

VIN--------------------------------–=

VRipple IRipple ESR1

8 COUT fSW--------------------------------------+

=

COUT

L IOH2 IOL

2–

Vf2

VOUT2–

------------------------------------=

IRMS High-Side D I OUT2

IRipple2

12----------------

+=

PCOND High-Side IRMS High-Side2 RDS on HS max =

PSW High_Side

VIN IOUT2

--------------------------- ts HL ts LH fSW+=

PLoss High-Side PCOND High-Side PSW High-Side+=

IRMS Low-Side 1 D– I OUT2

IRipple2

12----------------

+=

PCOND Low-Side IRMS Low-Side2 RDS on LS max =

PLoss BD IOUT VF tBD fSW=

PRR

QRR VIN fSW2----------------------------------------=


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Total Power Losses for Low-side MOSFET (W)

Controller Losses (W)(considering that the internal circuitry losses are 0.005W)

Inductor Losses (W)

Output Capacitor Losses (W)(for 30% current ripple)

Input Capacitor losses (W)

Bootstrap Capacitor (F)

Resonant Frequency of the LC Circuit (Hz)

PWM Modulator Gain

Quality Factor

Angular Corner Frequency

Transfer Function of the Power Train

Transfer Function of the Type III Compensation Network

Feedback resistor divider ()

APPENDIX A: LIST OF THE DESIGN TOOL FORMULAS (CONTINUED)


PLoss PCOND Low Side– PLoss BD PRR+ +=

PLoss VIN 0.005 FS QGate,low QGate,high+ + =

PLoss DCRL IL RMS2=

PLoss ESRCOUT

0.3 IOUT3--------------------------=

PLoss ESRCIN IRMS High

VOUT IOUTVIN

--------------------------------–

2=

CBOOT

QG Total VDROOP-------------------------=

fLC1

2 L COUT-----------------------------------------=

AMOD 20VIN

VRAMP---------------------log 20 VINlog= =

QVOUT

IOUT-------------

COUT

L--------------=

01

L C OUT

----------------------------=

GVG s G01

1s

Q0-----------

s0------ 2

+ +-------------------------------------------=

G s A0

R1 R3+

R1 R3 C1-------------------------------

s1

R4 C2-------------------+

s1

R1 R3+ C1-------------------------------------+

s sC2 C3+

R4 C2 C3-------------------------------+

s1

R3 C1-------------------+

------------------------------------------------------------------------------------------------–=

R2

VREF R1VOUT VREF–---------------------------------

0.6 R1VOUT 0.6–---------------------------= =


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Capacitor C1 (F)

Resistor R4 ()

Capacitor C2 (F)

Capacitor C3 (F)

Resistor R3 ()

Input Power (W)

Total converter losses (W)

Maximum RDS(on) ()

APPENDIX A: LIST OF THE DESIGN TOOL FORMULAS (CONTINUED)


C1

L COUTR1

----------------------------=

R4

fCO

fLC--------

1VIN-------- R1=

C2

2 L COUTR4

-------------------------------------=

C31

2 R4 fSW---------------------------------=

R31

C1 fSW------------------------------=

PIN

UOUT IOUTmaxEff

------------------------------------------=

PLoss PIN POUT–=

RDS on PLoss High Side–

IRMS High Side–2

--------------------------------------- 0.4=


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• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

2012 Microchip Technology Inc.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISO/TS 16949 ==

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-62076-661-3

Microchip received ISO/TS-16949:2009 certification for its worldwide

DS01452A-page 15

headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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10/26/12

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AN1452 - Using the MCP19035 Synchronous Buck …ww1.microchip.com/downloads/en/AppNotes/01452A.pdf · · 2012-11-09Using the MCP19035 Synchronous Buck Converter Design Tool. ...

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