Application Note 126 AN126-1 an126fa October 2010 2-Wire Virtual Remote Sensing for Voltage Regulators Clairvoyance Marries Remote Sensing Jim Williams, Jesus Rosales, Kurk Mathews, Tom Hack L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Virtual Remote Sense is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Introduction Wires and connectors have resistance. This simple, un- avoidable truth dictates that a power source’s remote load voltage will be less than the source’s output voltage. Figure 1 shows this, and implies that intended load voltage can be maintained by raising regulator output. Unfortunately, line resistance and load variations introduce uncertainties, limiting achievable performance. Figure 2 illustrates one compensatory approach. Locally positioned regulation stabilizes load voltage against line drops but is inefficient due to regulator losses. Figure 3, the classical approach, utilizes “4-wire” remote sensing to eliminate line drop effects. The power supply sense inputs are fed from load referred sense wires. The sense inputs are high impedance, negating sense line resistance effects. This scheme works well, but requires dedicated sense wires, a significant disadvantage in many applications. “Virtual” Remote Sensing Figure 4 retains the advantages of classical 4-wire re- mote sensing while eliminating the sense leads. Here, the LT4180 Virtual Remote Sense™ (VRS) IC alternates output current between 95% and 105% of the nominal required output current. The LT4180 forces the power supply to provide a DC current plus a small square wave current with peak-to-peak amplitude equal to 10% of the DC current. Decoupling capacitor C LOAD , normally required for low impedance under transient conditions in non-VRS systems, takes an additional role by filtering out the VRS square wave excursions. AN125 F01 POWER SUPPLY LOAD WIRING DROPS WIRING DROPS AN125 F02 POWER SUPPLY LOAD VOLTAGE REGULATOR LOAD Figure 1. Unavoidable Wiring Drops Cause Low Load Voltage. Line and Load Resistance Variations Introduce Additional Load Voltage Uncertainty, Mitigating Against Compensation by Raising Supply Voltage Figure 2. Local Regulation Stabilizes Load Voltage But is Inefficient AN125 F03 POWER SUPPLY LOAD V OUT + SENSE + SENSE – V OUT – VOLTAGE DROP R WIRE VOLTAGE DROP R WIRE Figure 3. Classical “4-Wire” Remote Sensing. V OUT Line Voltage Drops Are Compensated by Regulator Sensing at Load. High Impedance Sense Inputs Negate Sense Wire Resistance. Approach Requires Four Wires AN125 F04 POWER SUPPLY CONTROL PIN V OUT V L I L C LOAD V OUT = DC + SQUAREWAVE FROM WIRING VOLTAGE DROP C LOAD REMOVES SQUAREWAVE, SO V L CONTAINS ONLY DC. I L = DC + SQUAREWAVE R WIRE /2 I SENSE R WIRE /2 + – LOAD + – LT4180 Figure 4. LT4180 2-Wire Virtual Remote Sense Estimates Wiring Voltage Drops, Compensates by Adjusting Supply Output Voltage. Wiring Loss Is Determined by Measuring Small Signal Square Wave Carrier Induced Voltage Drop. Load Capacitor Absorbs Square Wave; Load Is at DC
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Application Note 126
AN126-1
an126fa
October 2010
2-Wire Virtual Remote Sensing for Voltage RegulatorsClairvoyance Marries Remote Sensing
Jim Williams, Jesus Rosales, Kurk Mathews, Tom Hack
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Virtual Remote Sense is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Introduction
Wires and connectors have resistance. This simple, un-avoidable truth dictates that a power source’s remote load voltage will be less than the source’s output voltage. Figure 1 shows this, and implies that intended load voltage can be maintained by raising regulator output. Unfortunately, line resistance and load variations introduce uncertainties, limiting achievable performance.
Figure 2 illustrates one compensatory approach. Locally positioned regulation stabilizes load voltage against line drops but is ineffi cient due to regulator losses. Figure 3, the classical approach, utilizes “4-wire” remote sensing to eliminate line drop effects. The power supply sense inputs are fed from load referred sense wires. The sense inputs are high impedance, negating sense line resistance effects. This scheme works well, but requires dedicated sense wires, a signifi cant disadvantage in many applications.
“Virtual” Remote Sensing
Figure 4 retains the advantages of classical 4-wire re-mote sensing while eliminating the sense leads. Here, the LT4180 Virtual Remote Sense™ (VRS) IC alternates output current between 95% and 105% of the nominal required output current. The LT4180 forces the power supply to provide a DC current plus a small square wave current with peak-to-peak amplitude equal to 10% of the DC current. Decoupling capacitor CLOAD, normally required for low impedance under transient conditions in non-VRS systems, takes an additional role by fi ltering out the VRS square wave excursions.
AN125 F01
POWERSUPPLY LOAD
WIRING DROPS
WIRING DROPS
AN125 F02
POWERSUPPLY
LOADVOLTAGE
REGULATORLOAD
Figure 1. Unavoidable Wiring Drops Cause Low Load Voltage. Line and Load Resistance Variations Introduce Additional Load Voltage Uncertainty, Mitigating Against Compensation by Raising Supply Voltage
Figure 2. Local Regulation Stabilizes Load Voltage But is Ineffi cient
AN125 F03
POWERSUPPLY LOAD
VOUT+
SENSE+
SENSE–
VOUT–
VOLTAGE DROP RWIRE
VOLTAGE DROP RWIRE
Figure 3. Classical “4-Wire” Remote Sensing. VOUT Line Voltage Drops Are Compensated by Regulator Sensing at Load. High Impedance Sense Inputs Negate Sense Wire Resistance. Approach Requires Four Wires
AN125 F04
POWER SUPPLY
CONTROL PIN
VOUT VL
IL
CLOAD
VOUT = DC + SQUAREWAVE FROM WIRING VOLTAGE DROPCLOAD REMOVES SQUAREWAVE, SO VL CONTAINS ONLY DC.IL = DC + SQUAREWAVE
RWIRE/2ISENSE
RWIRE/2
+
–LOAD
+
–
LT4180
Figure 4. LT4180 2-Wire Virtual Remote Sense Estimates Wiring Voltage Drops, Compensates by Adjusting Supply Output Voltage. Wiring Loss Is Determined by Measuring Small Signal Square Wave Carrier Induced Voltage Drop. Load Capacitor Absorbs Square Wave; Load Is at DC
Application Note 126
AN126-2
an126fa
Because C is sized to produce an “AC short” at the square wave frequency, a square wave voltage is produced at the power supply equal to VOUTAC = 0.1 • IDC • RWIREVP-P. The square wave voltage at the power supply has a peak-to-peak amplitude equal to one tenth the DC wiring drop. This is a direct measurement of wiring drop, not an estimate, accurate over all load currents. Signal processing produces a DC voltage from this AC signal which is introduced into the supply feedback loop to provide accurate load regula-tion1. Note that the “power supply” may be an IC linear or switching regulator, a module or any other power source capable of variable output. Power supplies can be syn-chronized to the LT4180 and VRS operating frequency is adjustable over more than three decades. Optional spread spectrum operation provides partial immunity from single-tone interference and a 3V to 50V input range simplifi es design. Because this technique is based on an estimate of load voltage, not a direct measurement, the resultant correction is an approximation, but a very good one.
Typical LT4180 load regulation is plotted in Figure 5. In this example, load current increases from zero until it produces a 2.5V wiring drop. Load voltage drops only 73mV at maximum current. A voltage drop equivalent to 50% of load voltage results in only a 1.5% shift in load voltage value. Smaller wiring drops produce even better results.
Applications
The following applications are all VRS augmented voltage regulators of various descriptions. The power regulation stages employed are, with one exception, generic LTC designs and are spared exhaustive commentary, permit-ting emphasis on the LT4180 VRS role. Additionally, the similarity of the VRS associated circuitry across the broad array of applications shown should be noted, and is indica-tive of the relative ease of implementation. Surprisingly little change is needed to use the VRS in the different situations presented.
VRS Linear Regulators
Figure 6 adds a simple stage to the LT4180 to implement a complete VRS aided linear regulator. The LT4180 senses current via the 0.2Ω shunt and feedback controls Q1 with Q2, completing a control loop. Cascoded Q2 permits the ICs 5V capable open drain output to control a high voltage at Q1’s gate. Components at the compensation pin furnish loop stability, promoting good transient response2. Figure 7 shows Figure 6’s load step waveforms. They include VSENSE (trace A), VLOAD (B) and ILOAD (C). Transient response is determined by loop compensation, load capacitance and remote sense sample rate. Figure 8 shows response with CLOAD increased to 1100μF. Load voltage transient excur-sion reduces and duration increases.
Figure 9, employing a monolithic regulator, adds current limiting and simplifi es loop compensation. Transient re-sponse approximates Figure 6’s. As before, the LT4180’s low voltage drain pin requires a cascode transistor to control the high voltage at the LT3080 set pin.
VWIRING (V)0
V LOA
D (V
)
4.97
4.98
4.99
4.96
4.95
0.5 1.51 2 2.5 3
4.92
4.91
4.94
5.00
4.93
AN126 F05
Figure 5. Typical LT4180 Virtual Remote Sense Performance Shows 1.6% Regulation vs 0V → 2.5V Wiring Drop
Note 1. Readers fi nding their intellectual prowess unsatiated by this admittedly cursory description will fi nd more studious coverage in Appendix A, “A Primer on LT4180 VRS Operation.”
Note 2. Value selection procedure for LT1480 VRS circuits is detailed in Appendix B, “Design Guidelines for LT4180 VRS Circuits.”
Application Note 126
AN126-3
an126fa
200k
OV
FB
DIV0DIV1VIN INTVCC
INTVCC
VPP
COMP GNDDRAIN
DIV2
CHOLD1 CHOLD2 CHOLD3 CHOLD4
33nF
AN126 F06
RUN
ROSCCOSC
2.2k1%
SENSE
SPREAD
LT4180
470pF470pF470pF47nF
Q1IRLZ44
1μF
41.2k1%
3.74k1%
63.4k1%
1μF
0.2Ω1% WIRING DROP
VIN20V
LOAD VOLTAGE12V, 500mA8Ω TOTAL WIRING DROP
LOADRETURN
27k
10μF25V
4.7μF 100μFLOAD RETURNWIRING DROP
5.36k1%
Q2INTVCC
330pFVN2222
10k
GUARD PINS NOT SHOWN
Figure 6. Virtual Remote Sense Controls Discrete Linear Regulator. Q2 Cascodes Drain Output, Buffering High Voltage Q1 Gate Drive. COMP Pin Associated Components Stabilize Loop
Figure 7. Figure 6’s Load Step Waveforms with 100μF Load Capacitor Include VSENSE (Trace A), VLOAD (B) and ILOAD (C). Transient Response is Determined by Loop Compensation, Load Capacitance and Remote Sense Sample Rate
Figure 8. Same Conditions as Figure 7 with CLOAD Increased to 1100μF. VLOAD Transient Excursion Reduces, Duration Extends
5ms/DIV
A = 2V/DIV
B = 2V/DIVAC COUPLED
C = 0.2A/DIV ON 0.2A
DC LEVEL
AN126 F07 5ms/DIV
A = 2V/DIV
B = 2V/DIVAC COUPLED
C = 0.2A/DIV ON 0.2A
DC LEVEL
AN126 F08
Application Note 126
AN126-4
an126fa
OV
FB
DIV0DIV1VIN INTVCC
INTVCC
VPP
COMP GNDDRAIN
DIV2
CHOLD1 CHOLD2 CHOLD3 CHOLD4
47nF
AN126 F06
RUN
ROSCCOSC
1.78k1%
SENSE
SPREAD
LT4180
330pF470pF470pF47nF
1μF
22.1k1%
3.57k1%
10k
60.4k1%
1μF
0.2Ω1% WIRING DROP
VIN18V
GUARD PINS NOT SHOWN
LOAD VOLTAGE12V, 500mA4Ω TOTALWIRING DROP
LOADRETURN
10μF25V
4.7μF LOAD RETURNWIRING DROP
470μF
5.36k1%
INTVCC
51k1500pF
VN2222
100k
IN OUT
SET
LT3080
VRS Equipped Switching Regulators
VRS based switching regulators are readily constructed. Figure 10’s fl yback voltage boost confi guration has similar architecture to the linear examples although output voltage is above the input. In this case, the LT4180 open drain output is directly compatible with the LT3581 boost regulator low voltage VC pin––no cascode stage is necessary.
Step down (“Buck”) VRS equipped switching regulators are similarly easily achieved. Figure 11’s scheme, reminiscent of the previously described linear regulators, substitutes an LT3685 step down regulator which is directly controlled from the LT4180 open drain output. A single pole roll-off stabilizes the loop and a 12V, 1.5A output is maintained from a 22V to 36V input despite a 0Ω to 2.5Ω wiring drop loss. Figure 11A is similar, except that it provides a 5V, 3A output from a 12V to 36V input.
Figure 9. Figure 6’s Approach Utilizing IC Regulator Adds Current Limiting, Simplifi es Loop Compensation. Transient Response Approximates Figure 6’s
VRS Based Isolated Switching Supplies
The VRS approach is adaptable to isolated output supplies. Figure 12’s 24V output converter utilizes an approach similar to the previous examples except that it supplies a fully isolated output. The virtual remote sense feature accommodates a 10Ω wire resistance. The LT3825 and T1 form a transformer coupled power stage. Opto-coupled feedback maintains output isolation.
Figure 13’s 48V → 3.3V, 3A design also has a fully isolated output, facilitated by power delivery through a transformer and optically coupled feedback loop closure. The LT3758 drives T1 via Q1. T1’s rectifi ed and fi ltered secondary supplies output power which is corrected for line drops by the LT4180. Isolation is maintained by transmitting the feedback signal with an opto-isolator. The opto-isolators output collector ties back to the LT3578 VC pin, closing the control loop.
Application Note 126
AN126-5
an126fa
OVFB
DIV0
DIV1
V IN
INTV
CC
INTV
CC
V PP
COM
PGN
DDR
AIN
DIV2
CHOL
D1CH
OLD2
CHOL
D3CH
OLD4 47
nF
AN12
6 F1
0
RUN
R OSC
C OSC
40.2
Ω1%
SENS
E
SPRE
AD
LT41
80
470p
F47
0pF
470p
F47
nF
10nF
1μF
41.7
k1%
73.2
Ω1%1.
24k
1%
24.3
k
1μF
0.2Ω 1%
WIR
ING
DROP
V IN
5V
LOAD
VOL
TAGE
12V,
500
mA
(100
mA
MIN
.)6Ω
TOT
AL W
IRIN
G DR
OP
LOAD
RETU
RN
10μF
25V
4.7μ
F16
V
L14.
7μH
DFLS
220
LOAD
RET
URN
WIR
ING
DROP
100μ
F
191k
100k
10k
107Ω
1%
47pF 15k
LT35
81
SW2
SW2
SW2
SW1
SW1
SW1
GATE
RTSS
SYNC
GND
V CC
SHDN
FAULT
FB VC
84.5
k0.
1μF
L1 =
VIS
HAY
IHLP
I525
CZ-1
1GU
ARD
PINS
NOT
SHO
WN
+ –
Figu
re 1
0. V
irtua
l Rem
ote
Sens
ed V
olta
ge B
oost
Con
fi gur
atio
n.
LT41
80 D
rain
Out
put C
ontro
ls F
lyba
ck R
egul
ator
via
LT35
81 V
C Pi
n
Application Note 126
AN126-6
an126fa
OVFB
DIV0
DIV1
V IN
INTV
CC
INTV
CC
V PP
COM
PGN
DDR
AIN
DIV2
CHOL
D1CH
OLD2
CHOL
D3CH
OLD4 47
nF
AN12
6 F1
1
RUN
R OSC
C OSC
2k 1%
SENS
E
SPRE
AD
LT41
80
330p
F47
0pF
470p
F47
nF
3.3n
F1μF
22.1
k1%
3.65
k1%61
.9k
1%
1μF
0.06
7ΩW
IRIN
G DR
OP
V IN
22V
TO 3
6V
12V,
1.5
A2.
5Ω T
OTAL
WIR
ING
DROP
LOAD
RETU
RN
22μF
25V
DFLS
240
INTV
CC
0.47
μF
1μF
50V
22μF
50V
0.1μ
F50
V
L1 -
VISH
AY IH
LP20
20CZ
-11
GUAR
D PI
NS N
OT S
HOW
N
LOAD
RET
URN
WIR
ING
DROP
470μ
F
5.36
k1%
47pF
28k
LT36
85
GND
10μH
1kCM
DSH-
3
SW
BOOS
T
VC
FB RT SYNC
RUN/
SD
V IN
INTV
CCBD
68.1
k1%
10k
30.1
k
100k
+
Figu
re 1
1. R
emot
e Se
nse
Corr
ecte
d 22
V IN
to 3
6VIN
Ste
p-Do
wn
Regu
lato
r Mai
ntai
ns 1
2V O
utpu
t Des
pite
Wiri
ng L
osse
s
Application Note 126
AN126-7
an126fa
Figu
re 1
1A. 1
2VIN
→ 3
6VIN
to 5
V OUT
Ste
p-Do
wn
Rem
ote
Sens
ed R
egul
ator
Has
Sim
ilar A
rchi
tect
ure
to F
igur
e 11
OVFB
DIV0
DIV1
V IN0.
033Ω
1%
INTV
CC
INTV
CC
V PP
COM
PGN
DDR
AIN
DIV2
CHOL
D1CH
OLD2
CHOL
D3CH
OLD4 47
nF
AN12
6 F1
1A
RUN
R OSC
C OSC
2.15
k1%
SENS
E
SPRE
AD
LT41
80
330p
F47
0pF
470p
F47
nF
4.7n
F
1μF
22.1
k1%
1.87
k1%21
.5k
1%
1μF
WIR
ING
DROP
V IN
8V T
O 36
VV O
UT5V
, 3A
0.4Ω
TOT
ALW
IRIN
G DR
OP
LOAD
RETU
RN
47μF
10V
47μF
10V
MBR
A340
T3G
INTV
CC
0.47
μF
4.7μ
F50
V22
μF50
V 0.1μ
F
GUAR
D PI
NS N
OT S
HOW
NC1
= C
2 =
AVXT
PSE4
77M
010R
0050
LOAD
RET
URN
WIR
ING
DROP
C2 470μ
F10
V
C1 470μ
F10
V
5.36
k1%
47pF
23.2
k
LT36
93ED
D
GND
6.8μ
H 1kCMDS
H-3
SW
BOOS
T
VC
FB RT SYNC
RUN/
SD
V IN
INTV
CC
BD
68.1
k1%
10k
1%30.1
k1%
100k
++
+ –
Application Note 126
AN126-8
an126fa
OV
FB
DIV0DIV1VIN
–VOUT
–VOUT
INTVCC
INTVCC
VPP
COMP GND
DRAIN
DIV2
CHOLD1 CHOLD2 CHOLD3 CHOLD4
0.1μF
AN126 F12
RUN
ROSCCOSC
1.58k1%
SENSE
SPREADLT4180
470pF3.3nF
3.3nF
330pF
0.047μF41.7k1%
1.37k1%
130k1%
10k
1μF
220μF35V
3.9k1/4W
* 1μF50V
VOUT24V, 500mA10Ω TOTAL WIRING DROP
LOAD RETURN
5.36k1%2k
47pFINTVCC
10k1%
LT3825
PGVCCSYNCSFST
201/8WBAS21LT1
OSCAP ROCMPPGOLYENOL CMPC TONSGND/PGND
FB
OVLO SENN
SENP
VC
0.022μF
100μF35V
3.9k1/4W
10μF35V
10μF35V
ES1G
T1200
1/4W
30pF500V
68pF250V
47k1/4W
Si7302DN4.7nF250V
0.05Ω1206
30k
1nF
220pF100k
30k
56pF
0.1μF
2.05k38.3k3.01k
1%
40.2k1%
68μF20V 0.1μF
14k1%
383k1% OPTIONAL
4.7μH
33nF
MMBT3906
56pF
2.2μF100V
10μF100V
56pF
+
VIN36V to 72V
VIN+
VIN–
12k
MMBT3908
1k
6.8k
+VCC
+
47k1/4W
12.3V TO 16.5V
+VCC
0.2Ω1% RWIRE
–VOUT
+
10μF TANYO YUDEN GMK325BJ106KN 1210100μF 36V NICHICON PL (M)10μF 100V SANYO 100CE10FS68μF 20V KEMET T491D686K020AS4.7nF 250V MURATA GA343DR7GD472KW01L4.7μH COOPER BUSSMANN SO3814-4R7-R1/4W RESISTORS ARE 12061/8W RESISTORS ARE 0805T1 PULSE PA2925NLGUARD PINS NOT SHOWN
= INPUT COMMON
* 12mA MINIMUM LOAD REQUIREMENT
MOC207
VN2222
LOAD RETURNWIRING DROP
–VOUT
Figure 12. Virtual Remote Sensed, Isolated 36VIN → 72VIN to 24VOUT Converter Accommodates 10Ω Lead Wire Resistance. LT3825/T1 Form Transformer Coupled Power Stage. LT4180 Provides Virtual Remote Sense, Opto-Coupled Feedback Maintains Output Isolation
Application Note 126
AN126-9
an126fa
OVFB
DIV0
DIV2
V IN
INTV
CC
INTV
CC2
V PP
COM
PGN
D
DRAI
N
DIV1
CHOL
D1CH
OLD2
CHOL
D3CH
OLD4 0.
1μF
AN12
6 F1
3
RUN
R OSC
C OSC
2.74
k1%
1.3k
SENS
E
0.03
3Ω1%
SPRE
ADLT
4180
470p
F47
0pF
470p
F
47nF
0.01
5μF
41.2
k1%
523Ω
1%
0.01
μF
13k
1%
1μF
C LOA
D*
3.3V
, 3A
0.4Ω
TOT
AL W
IRIN
G DR
OP
5.36
k1%
47pF
2200
pF10
.7k
1%
100μ
F10
V 2
T10.
4ΩW
IRIN
G DR
OP
LOAD
RETU
RN
LOAD
RET
URN
WIR
ING
DROP
V IN
18V
TO 7
2V+
1μF
PS28
01-1
VC SHDN
/UVL
O
FB RT
INTV
CC
GATE
SENS
E
SYNC
36.5
k1%
1μF
RCS1
0.03
3
T1 =
PUL
SE E
NERG
Y PA
1277
NLGU
ARD
PINS
NOT
SHO
WN
* C L
OAD
= 4×
, 470
μFAV
XTPS
E477
M01
0R00
50
Si48
48DV
100Ω1Ω
4.7μ
F50
VBA
S516
UPS8
40BA
V21W
V IN
V IN
GND
LTC3
758
SS
9.1k
51Ω
8.66
k1%10
5k1%
10k
4700
pF1μ
F10
0V1μ
F10
0V
INTV
CC2
= IN
PUT
COM
MON
= OU
TPUT
COM
MON
1M
Figu
re 1
3. 4
8V →
3.3
V Is
olat
ed S
tep-
Dow
n, R
emot
e Se
nsed
Re
gula
tor.
T1 D
eliv
ers
Isol
ated
Pow
er, L
T418
0 Re
mot
ely
Sens
es O
utpu
t, Su
pplie
s Fe
edba
ck v
ia O
pto-
Isol
ator
Application Note 126
AN126-10
an126fa
Figure 14, also a VRS isolated step-down supply, uses a commercially produced 48V isolated input module aug-mented with virtual remote sensing. The module sense terminals are unused. The LT4180 wiring drop correction is introduced at the module trim pin. Component values are shown for 3.3 and 5V outputs. The “black box” Vicor module trim pin transient response defi nes available control bandwidth. Figure 15, trace A, is the trim pin input step (see test circuit A), trace B, the module output. The trim pin directed dynamics set practical expectations for VRS equipped loop response around the module. Figures 16 and 17 do not disappoint. Figure 14’s load step response appears in Figure 16. Trace A is load step current, trace B, the resultant output voltage transient. The response enve-lope, bounded by module trim pin dynamics, is clean and well controlled. Figure 17 shows Figure 14’s turn-on into a 2.5Amp load. LT4180 activation arrests the initial abrupt rise at the 3rd vertical division. The ascent’s conclusion is controlled to the regulation point in damped fashion.
LT4180 sampling square wave residue is just discernible in the waveforms settled portion.
BEFORE PROCEEDING ANY FURTHER, THE READER IS WARNED THAT CAUTION MUST BE USED IN THE CONSTRUCTION, TESTING AND USE OF THIS CIRCUIT. HIGH VOLTAGE, AC LINE CONNECTED POTENTIALS ARE PRESENT IN THIS CIRCUIT. EXTREME CAUTION MUST BE USED IN WORKING WITH AND MAKING CON-NECTIONS TO THIS CIRCUIT. REPEAT: THIS CIRCUIT CONTAINS DANGEROUS, AC LINE CONNECTED HIGH VOLTAGE POTENTIALS. USE CAUTION.
Figure 18’s VRS aided “Off-Line” isolated output supply has a 5V output with 2A capacity. The schematic appears complex, but inspection reveals it to be essentially an AC line powered variant of Figure 13’s isolated approach. The LT4180 provides remote sensing and closes an isolated feedback loop with optical transmission.
Figure 14. Commercially Produced, Isolated 48V Input Module Augmented with Virtual Remote Sense. Module Sense Terminals Are Unused. Wiring Drop Correction Introduced at Module Trim Pin. Component Values Shown for 3.3V/5V Outputs
OV
FBVIN+ VOUT+
VOUT–
VSEN–
TRIM48V
VICORMODULEVI-230-EX
VSEN+
VIN–
VIN+
VIN–
DIV0DIV1VIN INTVCCVPP
COMP GND
DRAIN
DIV2
CHOLD1 CHOLD2 CHOLD3 CHOLD4
0.1μF
AN126 F14
RUN
ROSCCOSC
2.74k/1.69k
SENSE
SPREADLT4180
1nF3.3nF
3.3nF
0.047μF
4.7nF
42.2k1%
523Ω/4.64k
13.3k/17.4k
2.4k
10k
GUARD PINS NOT SHOWN
1μF
2200μF
3.3V/2.5A5V/2A0.4Ω TOTAL WIRING DROP
5.36k/5.36k
47pF
240k
WIRING DROP0.04Ω
LOADRETURN
LOAD RETURNWIRING DROP
+1μF
Application Note 126
AN126-11
an126fa
5ms/DIV
A = 5V/DIV
B = 0.5V/DIVON 5VDC
AN126 F15
PULSEGENERATOR
VICORVI-230-EX
V+
SEN
SENV–
TRIM24k
48V
48VRETURN
IN4148
LOAD
Trim Pin Pulse Test Circuit
20ms/DIV
A = 2A/DIVON 1A DC
B = 0.2V/DIV
AN126 F16 20ms/DIV
1V/DIV
AN126 F17
Figure 15.Vicor Module Trim Pin Transient Response Defi nes Available Control Bandwidth. Trace A is Trim Pin Input Step (See Test Circuit), Trace B, Module Output
Figure 16. Figure 14’s Load Step Response. Trace A is Load Step Current, Trace B Resultant Output Voltage Transient. Response Envelope, Bounded by Module Trim Pin Dynamics, is Well Controlled
Figure 17. Figure 14’s Turn-On into a 2.5A Load. LT4180 Activation Arrests Initial Abrupt Rise at Third Vertical Division. Ascent Conclusion is Controlled to Regulation Point. LT4180 Sampling Square Wave Residue is Discernible
VRS Halogen Lamp Drive Circuit
A fi nal circuit, Figure 19, uses the VRS to stabilize drive to a halogen lamp, in this case a 12V, 30W automotive type. Lamp output power remains constant despite 9V to 15V input variation and line resistance/connection uncertain-ties. Additional benefi ts include constant color output and extended lamp life. The circuit, a step up/down (“SEPIC”) converter, maintains 12V at the lamp despite the 9V to 15V input range3. The VRS functions in the manner previously described. Line resistance losses due to switches, wiring and connectors are obviated by VRS action. Figure 20 plots unaided vs remote sensed and regulated halogen lamp light output. VRS equipped luminosity is fl at over the 9 to 15V input range while unregulated performance
suffers dramatically. The regulation also benefi ts lamp life by greatly reducing lamp turn-on current. Figure 21 shows unregulated lamp turn-on exceeding 20A without regulation. In Figure 22, regulation cuts current peaking to 7A, a 3x reduction. This soft turn-on and constant 12V drive under high/low line conditions optimizes illumination and improves lamp life.
References
1. LT4180 Data Sheet, Linear Technology Corporation, 2010.
2. Ridley, R. “Analyzing the Sepic Converter”, Power Systems Design Europe, November, 2006.
Note 3. SEPIC operation is described in Reference 2.
Application Note 126
AN126-12
an126fa
OVFB
DIV0
DIV1
V IN
INTV
CC
INTV
CCV P
P
COM
PGN
DDR
AIN
DIV2
CHOL
D1CH
OLD2
CHOL
D3CH
OLD4
0.04
7μF
AN12
6 F1
1
RUN
R OSC
C OSC
2.67
k1%
SENS
E
SPRE
AD
LT41
80
470p
F3.
3nF
3.3n
F
10nF
0.1μ
F
41.2
k1%
0.47
μF
CNY1
7-3
4.53
k1%
750Ω
20.5
k1%
1μF
0.05
Ω1%
R WIR
E
5.36
k1% 1M
100p
F
6.8k
* V O
UT
5V, 2
A
2200
μF1Ω
TOT
ALW
IRIN
G DR
OP
V CC
FB RT/C
T
V CC
I SEN
COM
P
GND
LT12
41
V REF
V IN
6mH
RT1
OUT
270μ
F16
V10
μF16
V
MBR
2020
0CT
1μH
62Ω
V IN
V IN
12Ω
T1
7T70
T22
01/
4W
+15
0μF
16V
+ 10μF
16V
30pF
500V
47μF
400V
DF06
M
SPB0
3N60
C3
200V
P6KE
200A
90V
to 2
64VA
C IN
MUR
160E
510
2W
470k
1/4W
2.2n
F25
0VAC
“Y”
0.1μ
F25
0VAC
“X”
DANG
ER!!
HIG
H VO
LTAG
E!!
17T
150μ
F16
VV CC
2N70
02
2N39
04
BAS2
1
150p
F
+
270k
1/4W
270k
1/4W
13V
CMPZ
5243
B
1.2Ω
1/4W
18k
200k
1/2W
200k
1/2W 1μ
F22
0pF
0.1μ
F12
nF
+
470k
1/4W
= AC
LIN
E CO
MM
ON
= OU
TPUT
COM
MON
GUAR
D PI
NS N
OT S
HOW
N
NOTE
:47
μF 4
00V
CHEM
ICON
EKX
G401
ELL4
70M
L25S
2200
μF 1
0V S
ANYO
10M
V220
0AX
150μ
F 16
V SA
NYO
16M
V150
AX27
0μF
16V
SANY
O 16
SEPC
270M
10μF
16V
TDK
C32
25X7
RK10
6M1μ
H VI
SHAY
IHLP
2525
CZER
1ROM
6mH
PANA
SONI
C EL
F11M
030E
RT1
CANT
HERM
MF7
2-33
D7T1
PUL
SE P
A307
2NL
EF20
AL
= 10
0nH/
T2
* 10
0mA
MIN
IMUM
LOA
D RE
QUIR
ED.
1k
1k
3.9Ω
SCRE
ENED
ARE
A CO
NTAI
NS L
ETHA
L HI
GH V
OLTA
GES!
USE
CAU
TION
IN
CONS
TRUC
TION
AND
TES
TING
!IN
TVCC
200p
F20
0V
+
Figu
re 1
8. A
5V
Outp
ut “
Off-L
ine”
Con
verte
r Equ
ippe
d w
ith V
irtua
l Rem
ote
Sens
e.
LT41
80 P
rovi
des
Rem
ote
Sens
ing,
Clo
ses
Isol
ated
Fee
dbac
k Lo
op v
ia O
pto-
Isol
ator
WAR
NING
! SCR
EENE
D AR
EA C
ONTA
INS
LETH
AL A
C LI
NE C
ONNE
CTED
HIG
H VO
LTAG
ES. U
SE C
AUTI
ON IN
CON
STRU
CTIO
N AN
D TE
STIN
G.
Application Note 126
AN126-13
an126fa
OVFB
DIV0
DIV1
V IN
INTV
CCV P
P
COM
PGN
DDR
AIN
DIV2
CHOL
D1CH
OLD2
CHOL
D3CH
OLD4 0.
1μF
AN12
6 F1
9
RUN
R OSC
C OSC
3.4k
1%
SENS
ESP
READ
LT41
80
150p
F47
0pF
470p
F47
nF
47nF
1μF
42.2
k1%
4.99
k1%84
.5k
1%
1μF
WIR
ING
DROP
LOAD
RET
URN
WIR
ING
DROP
OSC
12V,
30W
HALO
GEN
LAM
P1Ω
CON
NECT
OR/S
WIT
CHC2
X10
μF20
V
22μF
25V 3 CERA
MIC
6.8μ
H
10μF
50V
6.8μ
HPD
S104
5
6.8μ
F50
V10
μF63
V
1000
μF25
V
6.65
k1%
4.12
k1%
6.8k
0.00
51W
42.2
k1%
47pF 13
.7k
1%
LT37
57
V IN
INTV
CC
GATE
SENS
E
SHDN
/UVL
O
SS SYNC
RTFB
XVC
GND
+
0.04
Ω1%
10μF
50V
0.1μ
H
4.7μ
F10
V
Q1 Si78
50DP
0.1μ
F
42.2
k10
k
100p
F
GUAR
D PI
NS N
OT S
HOW
NIH
LP40
40DZ
R6R8
M11
= 6
.8μH
UMK3
25Bd
106M
M-T
= 1
0μF,
50V
TMKB
d226
MM
-T =
22μ
FC2
X =
ZOSV
PIO
IHLP
1616
ABER
R10M
01 =
0.1
μH
200k
43.2
k
V IN
9V T
O 15
V
++
+
Figu
re 1
9. LT
4180
Ste
p Up
/Dow
n Co
nver
ter S
tabi
lizes
12V
Driv
e to
30W
Hal
ogen
Au
tom
otiv
e La
mp
Desp
ite 9
V →
15V
Inpu
t Var
iatio
n an
d Li
ne R
esis
tanc
e Un
certa
intie
s
Application Note 126
AN126-14
an126fa
BATTERY VOLTAGE (V)9
KILO
CAND
LES/
M2 10.0
12.0
14.014.5
8.0
6.0
10 1211 13 14 150
4.0
WITHOUT VIRTUAL REMOTESENSE/REGULATOR
2.0
AN126 F20
WITH VIRTUAL REMOTESENSE/REGULATOR
50ms/DIV
A = 5A/DIV
AN126 F21 50ms/DIV
A = 5A/DIV
AN126 F22
Figure 20. Unaided vs Remote Sensed/Regulated Halogen Lamp Light Output. Regulation Benefi ts Include Stable Illumination, Constant Color Output and Extended Lamp Life
Figure 21. Lamp Turn-On Current Exceeds 20A Without Regulation, Degrading Lifetime
Figure 22. Regulation Promotes Soft Turn-On, 12V Drive Under High/Low Line Conditions, Optimizing Illumination and Improving Lamp Life
Application Note 126
AN126-15
an126fa
APPENDIX A
A Primer on LT4180 VRS Operation
Voltage drops in wiring can produce considerable load regulation errors in electrical systems (Figure A1). As load current IL increases, voltage drop in the wiring (IL • RW) increases and the voltage delivered to the system (VL) drops. The traditional approach to solving this problem, remote sensing, regulates the voltage at the load, increas-ing the power supply voltage (VOUT) to compensate for voltage drops in the wiring. While remote sensing works well, it does require an additional pair of wires to measure at the load, which may not always be practical.
The LT4180 eliminates the need for a pair of remote sense wires by creating a virtual remote sense. Virtual remote sensing is achieved by measuring the incremental change in voltage that occurs with an incremental change in current in the wiring (Figure A2). This measurement can be used to infer the total DC voltage drop in the wiring, which can then be compensated for. The Virtual Remote Sense takes over control of the power supply via its feedback pin (VFB), maintaining tight regulation of load voltage VL.
Figure A3 shows the timing diagram for Virtual Remote Sensing (VRS). A new cycle begins when the power supply and VRS close the loop around VOUT (Regulate VOUT = H). Both VOUT and IOUT slew and settle to a new value, and these values are stored in the Virtual Remote Sense (Track VOUTHIGH = L and Track IOUT = L). The VOUT feedback loop is opened and a new feedback loop is set up commanding the power supply to deliver 90% of the previously measured current (0.9 IOUT). VOUT drops to a new value as the power supply reaches a new steady state, and this information is also stored in the Virtual Remote Sense. At this point, the change in the output voltage (ΔVOUT) for a –10% change in output current has been measured and is stored in the Virtual Remote Sense. This voltage is used during the next VRS cycle to compensate for voltage drops due to wiring resistance.
AN125 A1
POWER SUPPLY
VOUT
SYSTEM
REMOTE SENSE WIRING
POWER WIRING+
–VL
IL
RW+
–
AN125 A2
POWER SUPPLY
POWER WIRINGVFB
VIRTUALREMOTE SENSE
VOUT
SYSTEM+
–VL
IL
RWISENSE+
–
VOUT
REGULATE VOUTTRACK VOUTHIGH
REGULATE IOUT LOW
TRACK VOUT LOW
TRACK DVOUT
TRACK IOUT
AN126 A3
Figure A1. Traditional Remote Sensing Works Well But Requires Two Sense Wires
Figure A2. Virtual Remote Sensing Eliminates Sense Wires
Figure A3. Simplifi ed Virtual Remote Sense Timing Diagram. State Machine Driven Sequence Samples and Stores Information Necessary to Set Appropriate Power Supply Voltage to Correct for Wiring Losses
Application Note 126
AN126-16
an126fa
APPENDIX B
Design Guidelines for LT4180 VRS Circuits
INTRODUCTION
The LT4180 is designed to interface with a variety of power supplies and regulators having either an external feedback or control pin. In Figure B1, the regulator error amplifi er (which is a gm amplifi er) is disabled by tying its inverting input to ground. This converts the error amplifi er into a constant-current source which is then controlled by the drain pin of the LT4180. This is the preferred method of interfacing because it eliminates the regulator error ampli-fi er from the control loop which simplifi es compensation and provides best control loop response.
For proper operation, increasing control voltage should correspond to increasing regulator output. For example, in the case of a current mode switching power supply, the control pin ITH should produce higher peak currents as the ITH pin voltage is made more positive.
Isolated power supplies and regulators may also be used by adding an opto-coupler (Figure B2). LT4180 output voltage INTVCC supplies power to the opto-coupler LED. In situations where the control pin VC of the regulator may exceed 5V, a cascode may be added to keep the DRAIN pin of the LT4180 below 5V (Figure B3). Use a Low VT MOSFET for the cascode transistor.
Figure B1. Nonisolated Regulator Interface
DRAIN
AN126 B1
LT4180
ITH ORVC
REGULATOR
+–
DRAIN
AN126 B2
LT4180VC
INTVCCREGULATOROPTO-COUPLER+
–
DRAIN
AN126 B3
INTVCC
LT4180
TO VC
COMP
Figure B2. Isolated Power Supply Interface
Figure B3. Cascoded DRAIN Pin for Isolated Supplies
Application Note 126
AN126-17
an126fa
Figure B4. Design Flow Chart
LT4180 DESIGN FLOW
START
YES
NO
LINEAR SWITCHING
AN126 B4
WHAT TYPE OF POWERSUPPLY/REGULATOR?
CALCULATE fDITHER FROM POWER SUPPLYRESPONSE TIME OR CABLE PROPAGATION TIME
DRATIO = fOSC/fDITHER. USE NEAREST HIGHER FREQUENCY DIVISION RATIO
(TABLE 1, DATA SHEET)
CALCULATE ACTUAL fDITHER USINGSELECTED DIVISION RATIO
USE ACTUAL fDITHER TO COMPUTE CLOAD,AND CHOLD1–3, SET CHOLD4 = 1μF
CALCULATE FEEDBACK, UNDER ANDOVERVOLTAGE RESISTOR NETWORK
ADJUST CHOLD4 FOR PROPER VRS RESPONSE
TRY SPREAD SPECTRUM IF NARROW BANDINTERFERENCE IS ANTICIPATED
DONE
BUILD PROTOTYPE, ADJUST POWER SUPPLYCOMPENSATION USING LOAD STEP TESTING
WITH SPREAD SPECTRUM OFF
IS SUPPLYSYNCHRONIZED
TO LT4180?
fOSC = SWITCHINGSUPPLY FREQUENCY
fOSC = 2MHz, UNLESS SYSTEMREQUIRES ANOTHER FREQUENCY
DESIGN PROCEDURE
The fi rst step in the design procedure (Figure B4) is to determine whether the LT4180 will control a linear or switching supply/regulator. If using a switching power supply or regulator, it is recommended that the supply be synchronized to the LT4180 by connecting the OSC pin to the SYNC pin (or equivalent) of the supply.
If the power supply is synchronized to the LT4180, the power supply switching frequency is determined by:
fOSC = 4
ROSC • COSC
Recommended values for ROSC are between 20k and 100k (with 30.1k the optimum for best accuracy) and greater than 100pF for COSC. COSC may be reduced to as low as 50pF, but oscillator frequency accuracy will be somewhat degraded.
The following example synchronizes a 250kHz switching power supply to the LT4180. In this example, start with ROSC = 30.1k:
COSC = 4
250kHz • 30.1k= 531pF
This example uses 470pF. For 250kHz:
ROSC = 4
250kHz • 470pF= 34.04k
The closest standard 1% value is 34k.
The next step is to determine the highest practical dither frequency. This may be limited either by the response time of the power supply or regulator, or by the propaga-tion time of the wiring connecting the load to the power supply or regulator.
Application Note 126
AN126-18
an126fa
First determine the settling time (to 1% of fi nal value) of the power supply. The settling time should be the worst-case value (over the whole operating envelope: VIN, ILOAD, etc.).
F1 = 1
2 • tSETTLINGHz
For example, if the power supply takes 1ms to settle (worst-case) to within 1% of fi nal value:
F1 = 1
2 • 1e – 3= 500Hz
Next, determine the propagation time of the wiring. In order to ignore transmission line effects, the dither period should be approximately twenty times longer than this. This will limit dither frequency to:
F2 = VF
20 • 1.017ns/ft • LHz
where VF is the velocity factor (or velocity of propagation), and L is the length of the wiring (in feet).
For example, assume the load is connected to a power supply with 1000ft of CAT5 cable. Nominal velocity of propagation is approximately 70%.
F2 = 0.7
20 • 1.017e–9 • 1000= 34.4kHz
The maximum dither frequency should not exceed F1 or F2 (whichever is less):
fDITHER < min (F1, F2).
Continuing this example, the dither frequency should be less than 500Hz (limited by the power supply).
With the dither frequency known, the division ratio can be determined:
DRATIO =
fOSC
fDITHER= 250,000
500= 500
The nearest division ratio is 512 (set DIV0 = L, DIV1 = DIV2 = H). Based on this division ratio, nominal dither frequency will be:
fDITHER =
fOSC
DRATIO= 250,000
512= 488Hz
After the dither frequency is determined, the minimum load decoupling capacitor can be determined. This load capacitor must be suffi ciently large to fi lter out the dither signal at the load.
CLOAD = 2.2
RWIRE • 2 • fDITHER
where CLOAD is the minimum load decoupling capacitance, RWIRE is the minimum wiring resistance of one conductor of the wiring pair, and fDITHER is the minimum dither frequency.
Continuing the example, our CAT5 cable has a maximum 9.38Ω/100m conductor resistance.
Maximum wiring resistance is:
RWIRE = 2 • 1000ft • 0.305m/ft • 0.0938Ω/m
RWIRE = 57.2Ω
With an oscillator tolerance of ±15%, the minimum dither frequency is 414.8Hz, so the minimum decoupling capacitance is:
CLOAD = 2.2
57.2Ω • 2 • 414.8Hz= 46.36μF
This is the minimum value. Select a nominal value to ac-count for all factors which could reduce the nominal, such as initial tolerance, voltage and temperature coeffi cients and aging.
CHOLD Capacitor Selection and Compensation
CHOLD1
A 47nF capacitor will suffi ce for most applications. A smaller value might allow faster recovery from a sudden load change, but care must be taken to ensure full load p-p ripple at this node is kept within 5mV:
CHOLD2 = CHOLD3 = 2.5nF
fDITHER(kHz)
For a dither frequency of 488Hz:
CHOLD2 = CHOLD3 = 2.5nF
0.488(kHz)= 5.12nF
NPO ceramic or other capacitors with low leakage and di-electric absorption should be used for all HOLD capacitors.
Set CHOLD4 to 1μF. This value will be adjusted later.
Application Note 126
AN126-19
an126fa
Compensation
Start with a 47pF capacitor between the COMP and DRAIN pins of the LT4180. Add an RC network in parallel with the 47pF capacitor, 10k and 10nF are good starting values. Once the output voltage has been confi rmed to regulate at the desired level at no load, increase the load current to the 100% level and monitor the wire current (dither current) with a current probe. Verify the dither current resembles a square-wave with the desired dither frequency.
If the output voltage is too low, increase the value of the 10k resistor until some overshoot is observed at the leading edge of the dither current waveform. If the output voltage is still too low, decrease the value of the 10nF capacitor and repeat the previous step. Repeat this process until the full load output voltage increases to within 1% below the no load level. Refer to Figures B5a, B5b and B5c, which show compensation of the 12V 1.5A Buck Regulator Ap-plication on the data sheet. Check for proper voltage drop correction over the load range. The “dither current” should have good half-wave symmetry. Namely, waveform should have similar rise and fall times, enough settling time at top and bottom and minimum to no over/undershoot.
20μs/DIV
VLOAD11.2V
IDITHER50mA/DIV
AN126 B5a
Figure B5a. Dither Current and VOUT with 10nF, 10k Compensation 1.5A Load
Figure B6a. 500mA to 1A Transient Response Test with CHOLD4 = 25nF CHOLD4 Too Small
Figure B6b. 500mA to 1A Transient Response Test with CHOLD4 = 47nF Nicely Damped Behaviour
Figure B5b. Dither Current and VOUT with 10nF, 37k Compensation 1.5A Load
Figure B5c. Dither Current and VOUT with 3.3nF, 28k Compensation 1.5A Load
20μs/DIV
VLOAD11.9V
4180 F07b
IDITHER500mA/DIV
20μs/DIV
VLOAD11.9V
AN126 B5c
IDITHER50mA/DIV
Set Final Value of CHOLD4
Set the minimum value for CHOLD4, by performing a transient load test of 30% to 60% of the load and set the value of CHOLD4 to where a nicely damped waveform is observed. Refer to Figures B6a and B6b for an illustration.
After all the CHOLD values have been fi nalized, check for proper voltage drop correction and converter behavior (start-up, regulation etc.), over the load and input volt-age ranges.
10ms/DIV
VLOAD1V/DIV
AN126 B6a
IDITHER500mA/DIV
VLOAD1V/DIV
AN126 B6b
IDITHER500mA/DIV
10ms/DIV
Application Note 126
AN126-20
an126fa
Setting Output Voltage, Undervoltage and Overvoltage Thresholds
The RUN pin has accurate rising and falling thresholds which may be used to determine when Virtual Remote Sense operation begins. Undervoltage threshold should never be set lower than the minimum operating voltage of the LT4180 (3.1V).
The overvoltage threshold should be set slightly greater than the highest voltage which will be produced by the power supply or regulator:
VOUT(MAX) = VLOAD(MAX) + VWIRE(MAX)
VOUT(MAX) should never exceed 1.5 • VLOAD
Since the RUN and OV pins connect to MOSFET input comparators, input bias currents are negligible and a com-mon voltage divider can be used to set both thresholds (Figure B7).
RSERIES = 1.22 • RT
VUVL
⎛
⎝⎜
⎞
⎠⎟−R4
R1= RT −RSERIES −R4
R3 =1.22V − VOUT(NOM) • R4
RT
⎛
⎝⎜
⎞
⎠⎟
VOUT(NOM)
RT
R2 = RSERIES −R3
Where VUVL is the RUN voltage and VOUT(NOM) is the nominal output voltage desired.
For example, with VUVL = 4V, VOV = 7.5V and VOUT(NOM) = 5V,
RT = 7.5V200μA
= 37.5k
R4 = 1.22V200μA
= 6.1k
RSERIES = 1.22V • 37.5k4V
⎛⎝⎜
⎞⎠⎟− 6.1k = 5.34k
R1 = 37.5k − 5.34k − 6.1k = 26.06k
R3 =1.22V − 5V • 6.1k
37.5k
⎛
⎝⎜
⎞
⎠⎟
5V37.5k
= 3.05k
R2 = RSERIES −R3 = 2.29k
RSENSE SELECTION
Select the value of RSENSE so that it produces a 100mV volt-age drop at maximum load current. For best accuracy, VIN and SENSE should be Kelvin connected to this resistor.
Figure B7. Voltage Divider for UVL and OVL
R3
FB
AN126 B5
RUN
R2
LT4180
R4
OV
R1VIN
The voltage divider resistors can be calculated from the following equations:
RT = VOV
200μA, R4 = 1.22V
200μA
where RT is the total divider resistance and VOV is the overvoltage set point.
Find the equivalent series resistance for R2 and R3 (RSERIES). This resistance will determine the RUN voltage level.
Application Note 126
AN126-21
an126fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Figure B10. Clock Interface for Synchronization
Figure B8. Soft-Correct Operation, CHOLD4 = 1μF
Figure B9. Simplifi ed Leakage Models (with and without Guard Rings)
Soft-Correct Operation
The LT4180 has a soft-correct function which insures orderly start-up (Figure B8). When the RUN pin rising threshold is fi rst exceeded (indicating VIN has crossed its undervoltage lockout threshold), power supply output voltage is set to a value corresponding to zero wiring volt-age drop (no correction for wiring). Over a period of time (determined by CHOLD4), the power supply output voltage ramps up to account for wiring voltage drops, providing best load-end voltage regulation. A new soft-correct cycle is also initiated whenever an overvoltage condition occurs.
substantial leakage current through the leakage resistance (RLKG). By adding a guard ring driver with approximately the same voltage as the voltage on the hold capacitor node, the difference voltage across RLKG1 is reduced substantially thereby reducing leakage current on the hold capacitor.
Synchronization
Linear and switching power supplies and regulators may be used with the LT4180. In most applications regulator interference should be negligible. For those applications where accurate control of interference spectrum is de-sirable, an oscillator output has been provided so that switching supplies may be synchronized to the LT4180 (Figure B10). The OSC pin was designed so that it may directly connect to most regulators, or drive opto-isolators (for isolated power supplies).
Using Guard Rings
The LT4180 includes a total of four track/holds in the Virtual Remote Sense path. For best accuracy, all leakage sources on the CHOLD pins should be minimized.
At very low dither frequencies, the circuit board layout may include guard rings which should be tied to their respective guard ring drivers.
To better understand the purpose of guard rings, a simplifi ed model of hold capacitor leakage (with and without guard rings) is shown in Figure B9. Without guard rings, a large difference voltage may exist between the hold capacitor (Pin 1) node and adjacent conductors (Pin 2) producing
AN126 B9
1 2
RLKG
WITHGUARD RING
WITHOUTGUARD RING
1 2
RLKG1 RLKG2
OSCSYNC
AN126 B10
LT4180REGULATOR
Spread Spectrum Operation
Virtual remote sensing relies on sampling techniques. Because switching power supplies are commonly used, the LT4180 uses a variety of techniques to minimize potential interference (in the form of beat notes which may occur between the dither frequency and power supply switch-ing frequency). Besides several types of internal fi ltering, and the option for VRS/power supply synchronization, the LT4180 also provides spread spectrum operation.
By enabling spread spectrum operation, low modu-lation index pseudo-random phasing is applied to Virtual Remote Sense timing. This has the effect of converting any remaining narrow-band interference into broadband noise, reducing its effect.
Increasing Voltage Correction Range
Correction range may be slightly improved by regulating INTVCC to 5V. This may be done by placing an LDO between VIN and INTVCC. Contact Linear Technology Applications for more information.