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APPLICATION NOTE

Application information forTV processor + µP + CC decoder

TDA937X PS N2

AN01045

Version 1.0February 2002

Philips

Semiconductors

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Philips Semiconductors Version 1.0

TDA937X PS N2TV-processor + µP + CC

Application NoteAN01045

2

ABSTRACT

This report gives a description of the TDA937X PS N2 version, together with application aspects.

© Philips Electronics N.V. 2002

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent ofthe copyright owner. The information presented in this document does not form part of any quotation orcontract, is believed to be accurate and reliable and may be changed without notice. No liability will beaccepted by the publisher for any consequence of its use. Publication thereof does not convey nor

imply any license under patent- or other industrial or intellectual property rights.

Purchase of Philips I2Ccomponents conveys

a license under the I2C patent to use the

components in the I2C system, provided the

system conforms to the I2C specifications

defined by Philips.

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3

Application Note

Application information for TV Signal

processor & µP & Closed Caption decoderTDA 937X PS N2

AN01045

Author(s):

D. AllertonL. BakemaD. v.d. BrulT. BrutonG. Folmer

P.C.T.J. LaroD. Siersema

E. ArnoldF. Giuliano

J. LiuT. Lee

System Application, Mainstream T.V. SolutionsConsumer ICs Nijmegen,

The Netherlands

Keywords

Embedded micro-controller

OSDClosed Caption, VPS

Alignment free IF-PLL, Sound PLL

Synchronisation H/V

Geometry on vertical and E-W

Switches and filters

PAL/NTSC decoder

Delay line

Continuous Cathode Calibration

I2C

Date: February 2002

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4

Summary

This report gives a description of the application aspects of the TDA937X, a combination of TV signal

processor plus Closed caption decoder plus embedded microprocessor in one device.

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CONTENTS

1 INTRODUCTION...................................................................................................................................... 7

2 DEVICE INFORMATION ......................................................................................................................... 9

3 PINNING CONFIGURATION................................................................................................................. 11

4 DEVELOPMENT TOOLS ...................................................................................................................... 13

5 I2C CONTROL VIDEO PROCESSOR PART......................................................................................... 17

5.1 INPUT CONTROL BITS.................................................................................................................. 205.2 OUTPUT CONTROL BITS ............................................................................................................. 35

6 APPLICATION INFORMATION............................................................................................................. 41

6.1 MICROPROCESSOR ..................................................................................................................... 456.2 IF PART .......................................................................................................................................... 476.3 FM SOUND..................................................................................................................................... 506.4 QSS SOUND................................................................................................................................... 556.5 THE NARROW BAND PLL............................................................................................................. 576.6 FILTERS, SWITCHES AND COLOUR DECODER........................................................................ 596.7 HORIZONTAL AND VERTICAL SYNC GEOMETRY..................................................................... 636.8 GEOMETRY (HORIZONTAL AND VERTICAL) AND DRIVE OF VERTICAL DEFLECTION ........ 716.9 YUV / RGB PROCESSING AND CONTROL.................................................................................. 776.10 PICTURE IMPROVEMENT FEATURES ........................................................................................ 896.11 SUPPLY, GROUNDING AND DECOUPLING................................................................................ 956.12 EMC LAYOUT............................................................................................................................... 107

7 ALIGNMENTS...................................................................................................................................... 109

7.1 TUNER AGC................................................................................................................................. 1097.2 GEOMETRY.................................................................................................................................. 1107.3 SCREEN VOLTAGE ALIGNMENT............................................................................................... 1147.4 COLOUR TEMPERATURE ALIGNMENT .................................................................................... 118

8 BLOCK DIAGRAM .............................................................................................................................. 120

9 INTERNAL PINNING ........................................................................................................................... 121

10 APPLICATION EXAMPLE ( DEMO-BOARD ) .................................................................................... 128

11 REFERENCES..................................................................................................................................... 129

12 INDEX .................................................................................................................................................. 131

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1 INTRODUCTION

This report gives hardware/software application information concerning the TDA937x PS N2 family.

The TDA937x PS N2 series have both microprocessor and videoprocessor functions integrated in onesingle chip and this device is intended for economy TV applications with 90º and 110º picture tubes.Several features are implemented and control of TDA937x functions/features is carried out using thesupported I

2C bus and embedded software.

The microprocessor, which uses an enhanced 80c51-microprocessor core (12MHz clock) has OTPROM and built in RAM and it caters for:

- Closed Caption decoding (subtitle system in USA for people with hearing impediments).- OSD generation- Data Capture decoding of either Line 21 Data Services (525 Timing) or Euro-Caption (625 Timing)

The videoprocessor includes all the functions necessary for TV processing such as:- IF video processing and sound (FM + QSS).- Sync and geometry processing.- PAL/NTSC colour decoder.- RGB generation and processing of signals.

The device is encapsulated in a SDIP64 package (Shrink Dual In-line, 64 pin SOT274-1) and usesboth BIMOS and CMOS technologies.

The TDA937X family has been designed in order to have a low external component count forapplication and a single layer PCB technology can be used.

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2 DEVICE INFORMATION

The TDA937X family offers complete control and small signal video processing needed for TV applicationsin one device; it includes a microprocessor and a videoprocessor, both being encapsulated in a SDIP64(Shrink Dual In-line, 64 pins) package.The microprocessor block diagram is shown in chapter 8.

A summary of the functions/features of the microprocessor is:

• Combined 55K x 8 bit OTP Micro-controller Program ROM and 4.5K x 16 bit OTP Character ROM.

• 0.25K x 8 bit Main Data RAM ( Mov address space).

• 2.25K x 8 bit Auxiliary Data RAM (Movx address space).

• Additional 16 bit Timer with 8 bit pre-scaler.

• 4 bit software A/D convert with 4 multiplexed inputs.

• Low resolution PWMs for VST.

• Byte level I2C up to 400KHz.

• Watchdog Timer with 16-bit pre-scaler.

• Three power saving modes : Stand-by, Idle and Power-Down.

• 13 I/O for SDIP64 via individual addressable controls.

• Programmable micro-controller I/O for Push-Pull, Open Drain, Quasi-Bidirectional & highImpedance.

• OSD graphics engine with up to 48 characters in width by 16 rows.

• Closed Caption style organized as 34 characters by 16 rows.

• 256 displayable characters.

• Globally selectable character matrix: 12 x 10, 12 x 13, 12 x 16 and 16 x 18 (h x v).

• Globally selectable horizontal character spacing (up to 4 pixels).

• Globally selectable vertical character spacing (up to 7 TV lines).

• 16 DRCS at up to 16 x 18 character matrix.• 16 Foreground and 16 Background display colours selectable from a palette of 64.

• Enhanced display features including shadowing, underlining, overlining, italics and smoothing.

• Cursor Function.

• Contrast Reduction.

The videoprocessor block diagram, which is subdivided into four subsections, is shown in chapter 8

A summary of the functions/features of the videoprocessor are:

IF video & sound:

− Multi-standard vision IF circuit with alignment free PLL demodulator and IF frequency selection by I2C.

− Internal time constant for IF AGC circuit which can be selected via I2

C bus.− The FM PLL sound demodulator can be switched between 4.5/5.5/6.0/6.5 MHz frequencies with the I

2C

bus. At these frequencies extra internal selectivity can be selected under critical reception conditions byselecting the internal bandpass filter with the I

2C bus.

− Types available with FM demodulator or with QSS sound output as an input for a stereo decoder..

Filters/Switches & colour decoder:

− CVBS switching between the CVBS from the front end (IF) and CVBS from SCART which can also beused as an Y/C input.

− Integrated chroma trap, chroma bandpass (switchable center frequency with I2C) and cloche filters

− Integrated luminance delay line with adjustable delay time.

− Peaking function including depeaking and a variable positive/negative overshoot ratio .

− Integrated baseband delay line (for NTSC systems can be applied as comb filter).− ACL implemented for deviating standards having large chroma/burst ratios (>3).

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ACL function switched via I2C bus.

− PAL/NTSC colour decoder with fully automatic colour search system includingLATAM colour decoding for PAL M and PAL N signals.

− Only one 12MHz crystal required for all internal timing e.g. in the microprocessor, Close Caption

decoder, OSD and in the video processor IF frequency, sound carrier, colour decoder and horizontalfrequency

HV sync & geometry:

− Horizontal synchronization with 2 control loops and alignment free horizontal oscillator

− Vertical count down circuit

− Vertical driver optimized for DC coupled vertical output stages

− Horizontal and vertical geometry processing

− Horizontal and vertical zoom function for 16 : 9 applications

− Horizontal parallelogram and bow correction for large screen picture tubes

− Low stress by innovative slow start/stop of HOUT implying a gradual build-up of the EHT and deflectionenergy

− Only 3.3V 65mA needed for start up which simplifies the stand-by power supply

YUV/RGB processing & control:

− Picture improvement features as:

− dynamic skin tone

− black stretching

− contrast reduction possibility during mixed mode of OSD signals

− Linear RGB/YUV/ Y PB PR with fast blanking where the synchronisation on Y signals is possible via I2C

bus.

− CC or OSD signals are internally supplied from the CC decoder.

− Independent adjustable colour temperature for high/low light calibration.

− Beam current limiting, peak white limiting and soft clipper.

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3 PINNING CONFIGURATION

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

1819

20

21

22

23

24

25

26

27

28

29

30

31

32 33

34

35

36

37

38

39

40

41

42

43

44

45

4647

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64P1.3/T1

P1.6/SCL

P1.7/SDA

P2.0/TPWM

P3.0/ADC0/PWM0

P3.1/ADC1/PWM1

P3.2/ADC2/PWM2

P3.3/ADC3/PWM3

VSSC/P

P0.5

P0.6

VSSA

I.C.

VP2

DECDIG

PH2LF

PH1LF

GND3DECBG

AVL/EWD

VDRB

VDRA

IFIN1

IFIN2

IREF

VSC

AGCOUT

AUDEEM/SIFIN1

DECSDEM/SIFIN2

GND2

SNDPLL/SIFAGC

AVL/SNDIF/ REFO

HOUT

FBISO

AUDEXT/QSSO

EHTO

PLLIF

IFVO/SVO

VP1

CVBS1

GND1

CVBS/Y

C

AUDOUT

INSSW2

R2/VIN/PrING2/YIN

B2/UIN/PbIN

BCLIN

BLKIN

RO

GO

BO

VDDA

VPE

VDDC

OSCGND

XTALIN

XTALOUT

RESET

VDDP

P1.0/INT1

P1.1/T0

P1.2/INT0

T D

A 9 3 7 X

P S

N 2

L E A D E R

Figure 1: Pinning configuration

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IC version FM PLL version QSS version

East-west Y/N N Y N Y

CMB1, 0 bits 00 01/10/11 00 01/10/11 00 01/10/11 00 01/10/11Pin 20 AVL EWD AVL EWD

Pin 28 AUDEEM SIFIN1

Pin 29 DECSDEM SIFIN2

Pin 31 SNDPLL SIFAGC

Pin 32 SNDIF REFO AVL/SNDIF REFO REFO

Pin 35 AUDEXT AUDEXT QSSO AUDEXT QSSO

Table 1: Pin functions for various modes of operation

Note1. When additional (external) selectivity is required for FM-PLL system pin 32 can be used as sound IF

input. This function is selected by means of SIF bit in subaddress 28H.

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4 DEVELOPMENT TOOLS

To develop with the TDA937XPS/N2 family, the tools, listed below, need to beadapted/upgraded. To order the necessary upgrades, please contact your local marketingrepresentative.

Emulator

Depending on the emulator brand used, the following adaptations are necessary:

HITEX

Currently, Hitex can supply a probe, namely PxTDA93xx-N2, for the TDA935X/6X/8XPS/N2 family, which isalso suitable for emulating the TDA937XPS/N2 family,

as well. This probe includes all the adapters for the µprocessor bond-outs (SAA5512) and video processor

bond-out. (KN10161 QSS/FM).

However, existing UOC-N1 customers can upgrade their system, as well, for emulating theTDA937XPS/N2 devices, as described below.The HITEX with the existing PXSAA55xx probe for emulation of the TDA935X/6X/8X N1 consists of thefollowing PCBs:1. Main probe PCB, ref. 7313-903-0027-2 or ref. 7313-903-0027-32. QFP120 Daughter board PCB, ref. 7313-903-0033-23. UOC Interface board, ref. 7313-903-0007-2.

In order to emulate the TDA937XPS/N2 family devices, the above boards have to be replacedas below:

1. Main probe PCB ref. 7313-903-0027-3 (Only in case version is ref. 7313-903-0027-2)2. QFP120 Daughter board ref. 7313-903-0264-1 (replaces ref. 7313-903-0033-2)3. UOC interface board ref. 7313-903-0317-1 (replaces ref. 7313-903-0007-2)

The new Daughter board (ref. 7313-903-2641) plugs into the main probe PCB (ref. 7313-903-0027-3)

via an array of connectors, SK1...SK8. This board can accommodate the new υprocessor bond-outs(SAA5512).The new UOC interface board can accommodate the new video processor bond-out. (KN10161QSS/FM).

BL-MTS Systems Applications Group Southampton supplies the necessary µprocessor, videoprocessor bond-outs for emulation and replacement boards.The new set of boards supports the internal reset feature of the TDA937XPS/N2 family.Before using the probe, a set of jumpers on the Daughter board needs to be set as described below:

J1: HIJ2: HIJ3: OPEN (not used)J4: OPEN (not used)

A brochure with information about the new probe heads and bondouts is attached to this document.More details can be found in the Application Note PxTDA93xx-N2 available at our Support area on theSemiconductor Internet Site http://www.semiconductors.com.

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ASHLING ULTRA 51

Ashling announced that they would no longer support the existing CTS51 system. They offer full

support for the TDA937XPS/N2 with their new Ultra-51 Ashling system. The system is suppliedwith and adapter (AD-SAA55L+) to use for accommodating the microprocessor bond-out.An additional adapter, ref. 7313-903-03171, is needed for the video-processor bond-out and it can berequested from BL-MTS Systems Applications Group Southampton.Information about the new probe head can be found in the attached brochure.

Display Development Studio (DDS)

The DDS is needed to generate the proper character sets and the matching with the type number ofthe device.

The new version DDS 2.2 supports the new UOC – N2.PAT/PROMT tool is out of date; it is recommended to use the new PROMPT tool, which is included

within DDS 2.2 .It can be downloaded from our Support area on the Semiconductor Internet Sitehttp://www.semiconductors.com.

This Support area is located at http://download.semiconductors.com/protected/video/.To apply for access, please complete the electronic form located at our Support Area:

http://downloads.semiconductors.com/unregistered/

GTV development tool

GTV release 2.0 supports the TDA937XPS/N2 family. Older releases are not suitable for thethese devices.

Bench programmer

For programming the TDA937XPS/N2 the bench programmer must be a recent version. Theseversions can be easily recognized because they have a blue PCB.Some of older bench programmer versions (with green PCB) cannot be used with the TDA937XPS/N2PS/N1 devices, until a FPGA(s) upgrade is implemented.

Please contact the BL-MTS Systems Applications Group Southampton for more details.

TV demoboard and WIC software

For evaluation, a TV demoboard plus the latest WIC software is available for the TDA937XPS/N2version

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5 I2C CONTROL VIDEO PROCESSOR PART

FUNCTION SUBADDR DATA BYTE

(HEX) D7 D6 D5 D4 D3 D2 D1 D0

POR

ValueHorizontal parallelogram 06 0 0 A5 A4 A3 A2 A1 A0 20

Horizontal Bow 07 0 0 A5 A4 A3 A2 A1 A0 20

Hue 08 0 0 A5 A4 A3 A2 A1 A0 00

Horizontal shift (HS) 09 0 0 A5 A4 A3 A2 A1 A0 20

EW width (EW)(1)

0A 0 0 A5 A4 A3 A2 A1 A0 20

EW parabola/width (PW)(1)

0B 0 0 A5 A4 A3 A2 A1 A0 20

EW upper corner parabola(1)

0C 0 0 A5 A4 A3 A2 A1 A0 20

EW lower corner parabola(1)

0D 0 0 A5 A4 A3 A2 A1 A0 20

EW trapezium (TC)(1)

0E 0 0 A5 A4 A3 A2 A1 A0 20

Vertical slope (VS) 0F 0 0 A5 A4 A3 A2 A1 A0 20

Vertical amplitude (VA) 10 0 0 A5 A4 A3 A2 A1 A0 20

S-correction (SC) 11 0 0 A5 A4 A3 A2 A1 A0 20

Vertical shift (VSH) 12 0 0 A5 A4 A3 A2 A1 A0 20

Vertical zoom (VX)(1)

13 0 0 A5 A4 A3 A2 A1 A0 20

Black level off-set R 14 0 0 A5 A4 A3 A2 A1 A0 20Black level off-set G 15 0 0 A5 A4 A3 A2 A1 A0 20

White point R 16 0 0 A5 A4 A3 A2 A1 A0 20

White point G 17 0 0 A5 A4 A3 A2 A1 A0 20

White point B 18 0 0 A5 A4 A3 A2 A1 A0 20

Peaking 19 0 0 A5 A4 A3 A2 A1 A0 20

Luminance delay time 1A 0 0 0 0 YD3 YD2 YD1 YD0 00

Brightness 1B 0 0 A5 A4 A3 A2 A1 A0 20

Saturation 1C 0 0 A5 A4 A3 A2 A1 A0 20

Contrast 1D 0 0 A5 A4 A3 A2 A1 A0 20

AGC take-over 1E 0 0 A5 A4 A3 A2 A1 A0 20

Volume control 1F 0 0 A5 A4 A3 A2 A1 A0 20

Colour decoder 0 20 CM3 CM2 CM1 CM0 MAT MUS ACL CB 00

Colour decoder 1 21 0 0 0 0 0 PSNS BPS FCO 00

AV-switch 0 22 0 0 SVO CMB1 CMB0 INA INB 0 00

AV-switch 1 23 0 0 0 0 0 0 0 RGBL 00Synchronisation 0 24 0 HP2 FOA FOB POC STB VIM VID 00

Synchronisation 1 25 0 0 FSL OSO FORF FORS DL NCIN 00

Deflection 26 0 AFN DFL XDT SBL AVG EVG HCO(1)

00

Vision IF 0 27 0 IFB IFC VSW 0 AFW IFS STM 00

Vision IF 1 28 SIF 0 0 IFLH 0 AGC1 AGC0 FFI 00

Sound 0 29 AGN SM1 FMWS 0 SM0 0 FMB FMA 00

Control 0 2A 0 IE2 RBL AKB CL3 CL2 CL1 CL0 00

Control 1 2B 0 0 VSD SOY 0 YUV1 YUV0 HBL(1) 00

Sound 1 2C 0 0 ADX 0 0 AVL(2)

QSS 0 00

Features 0 2D 0 0 0 0 DSK 0 0 BKS 00

Features 1 2E 0 BPB RPO1 RPO0 0 0 0 0 00

Table 2: I2C input bits

NOTE:1. These functions are only available in versions that have the East-West drive output.2. The AVL function is only available in versions which have no East-West drive output or when the

subcarrier output is used for the connection of the AVL capacitor (via the bits CMB1, 0 in subaddress22hex).

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DATA BYTEFUNCTION SUBADDR(HEX) D7 D6 D5 D4 D3 D2 D1 D0

00 POR IFI LOCK SL CD3 CD2 CD1 CD0

01 XPR NDF FSI IVW WBC HBC BCF IN2Output status bytes

02 SUP X X QSS AFA AFB FMW FML

Table 3: I2C output bits

The TDA937X PS N2 uses an internal I²C-bus to read and write all its functions:

• Write slave address: 8AHEX : A6 A5 A4 A3 A2 A1 A0 R/W: 1 0 0 0 1 0 1 0• Read slave address: 8BHEX : A6 A5 A4 A3 A2 A1 A0 R/W: 1 0 0 0 1 0 1 1

For I²C-bus write-transmissions the TDA937X PS N2 has automatic sub-address increment, so multipledata bytes can be sent in one transmission.

Acknowledge acknowledge acknowledgefrom slave from slave from slave

0 Sub addressStart Slave address Ack Ack Data Byte Ack Stop

R/W first sub-address multiple data bytes, = = destination of each acknowledgedwrite first data byte by slave

Reading the three status bytes is done without sub-addressing. After receiving the I²C-bus read address,the TDA937X PS N2 always starts with status byte 0.

No acknowledgeacknowledge acknowledge from masterfrom slave from master (just clock pulse)

1 Status byte 0Start Slave address Ack Ack Status byte 2 Nack Stop

R/W = Read 1, 2 or 3 status bytesread

I²C-bus start-up procedure.

The TDA937X PS N2 has many alignment-free internal circuits that are calibrated with the frequency of thereference Xtal oscillator. To ensure correct start-up after the 3.3 Volt is applied, a start-up routine isavailable which should be included in the software to run as first block. We strongly advice to use thisroutine to prevent problems with initialising

1. Write all sub addresses from 00HEX to 2EHEX. When STB is written 1, the horizontal out will begin with

slow start when register 2EHEX is written, else the video processor will remain in stand-by.2. Keep reading I2C-bus status bytes till SUP = 1 (+ 8 Volt present)

Note: When the +8 Volt is supplied via the EHT flyback transformer, this has only sense when the deviceis set in operational mode (STB = 1)

Before the horizontal drive output can become active, all sub-address bytes 00HEX to 2EHEX must be loaded.Registers or register bits, not available or defined in certain versions, must be loaded with zero’s for (future)compatibility. Only when the +8 Volt supply is present, the oscillator is calibrated. Non-successful calibrationforces SUP to 0 irrespective the + 8 Volt supply to indicate a failure.

Each time before the sub-address bytes are refreshed, the status bytes must be read. If POR=1 then thestart-up routine and step 1, 2 must be executed to restart the IC. Not following this procedure may result inundesired conditions after power-up or a power dip (e.g. incorrect horizontal line frequency).

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Software monitoring or external I2C bus control is possible via the SCL, SDA pins at pins 2 and 3respectively.

Software monitoring (I2C data) between microprocessor and videoprocessor can be done by programming

ports 1.6/1.7 (SCL, SDA) as open drain and having pull up resistors on these pins. When programming theTXT21.1 (I2C Port0) then the I

2C data can be enabled/disabled on these pins.

Monitoring the I2C data is only possible after the software initialisation is completed therefore when the

Drv_InitUOC() function in the UOC BOOT Library has been called.

External I2C bus control (e.g. with WIC software) of a programmed device is possible via the SCL, SDApins only when communication between microprocessor and videoprocessor is disabled by customersoftware.Similarly, customer software can be implemented whereby required registers for alignment etc. can bechanged (e.g. Factory Service Mode).

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5.1 INPUT CONTROL BITS

Reg 06 D0..5 HP HOR. PARALLELOGRAMCORRECTION

Corrects when the vertical lines are not orthogonal on the horizontal lines.

Reg 07 D0..5 HB HOR. BOW CORRECTION

Corrects when the top and bottom of the vertical lines are slightly bent from the middle to left or right. Thiscan be used with black flatline cathode ray tubes to have optimum adjustment of vertical lines.

Reg 08 D0..5 HUE HUE

The hue control is active when the NTSC colour system is received

Reg 09 D0..5 HS HORIZONTAL SHIFT

Adjusts the horizontal position of the picture on the screen.

Reg 0A D0..5 EW E-W WIDTH

Adjusts the picture width. When all higher order terms (BCP, PW, TC, UCP) are aligned, the geometrycorrections will remain correct when changing the EW register for horizontal zoom.

Reg 0B D0..5 PW E-W PARABOLA WIDTH

Adjusts the parabola correction.

Reg 0C D0..5 UCP E-W UPPER CORNERPARABOLA

Adjusts the upper curve of the vertical lines.Set UCP in neutral position before starting alignment.

Reg 0D D0..5 BCP E-W BOTTOM CORNERPARABOLA

Adjusts the bottom curve of the vertical lines. Set BCP in neutral position before starting alignment.

Reg 0E D0..5 TC E-W TRAPEZIUM COR.

Adjusts the position of the vertical lines at the sides: can be bend inwards or outwards. The vertical linesremain straight. Set in neutral position before starting alignment.

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Reg 0F D0..5 VS VERTICAL SLOPE

Adjusts the vertical slope. This alignment is meant to compensate for spread on the value of the external

sawtooth capacitor (major) and spread on the internal reference current source (minor). This is the firstvertical alignment to execute in order to adjust the internal levels to exact nominal value. These nominalvalues are important to ensure that all derived correction waveforms (vertical S and horizontal geo) arecorrect. Use SBL (service blanking) for correct alignment. See also chapter geometry alignments.

Reg 10 D0..5 VA VERTICAL AMPLITUDE

Adjusts vertical amplitude. Adjustment does affect all horizontal geometry corrections and also the verticalS-correction. Before using VA, first align VS and VSH. Do not use for vertical zoom because overscan is notblanked!

Reg 11 D0..5 SC VERTICAL S-CORRECTION

Adjusts the vertical S-correction.

Reg 12 D0..5 VSH VERTICAL SHIFT

Adjusts the vertical shift. This alignment is meant to compensate for vertical offsets like DC offset verticalamplifier (major), mechanical offset picture tube gun (major) and internal offsets (minor). In this way, exactlanding in the vertical middle of the screen is ensured when the vertical deflection current outputs are zero.This alignment must be carried out after alignment of VS and is important to ensure that all derivedcorrection waveforms (vertical S and horizontal geo) are correct. See also chapter geometry alignments.

Reg 13 D0..5 VX VERTICAL ZOOM/EXPAND

This bit can be used to shrink the vertical amplitude (compressed 16:9 format on 4:3 tube) or expand thevertical amplitude (4:3 format on 16:9 tube). The vertical amplitude adjustment is 1 % per step, the neutralposition is chosen such (19HEX, 25DEC) that VX = 00 gives 25 % picture height reduction (75% pictureheight), suitable for displaying compressed 16:9 format on 4:3 tube. When zooming larger than 100 %,vertical overscan larger than 106 % will be blanked to prevent picture tube damage. It is important to set VXin neutral position before starting alignment!

Reg 14 D0..5 BLOR BLK LEVEL OFFSET RED

Reg 15 D0..5 BLOG BLK LEVEL OFFSET GREEN

Adjustment of an offset in the red and /or green channel to realise another colour temperature setting forlow lights as for high lights.

Reg 16..18 D0..5 WPR, G, B WHITE POINT RGB

Adjustment of the white point setting for colour temperature at high light in order to compensate for thephosphor efficiencies of different CRTs.

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Reg 19 D0..5 PEAK PEAKING

The peaking on the Y signal can be adjusted with this 6 bit register

Reg 1B D0..5 BRI BRIGHTNESS

Reg 1C D0..5 SAT SATURATION

Reg 1D D0..5 CON CONTRAST

Reg 1A D0..3 YD0..3 Y-DELAY

Adjusts the Y delay in order to achieve correct Y and chroma timing

Reg 1E D5..0 AGC TAKE OVER AGC TAKE OVER POINT

Reg 1F D5..0 VOLUME CONTROL VOLUME CONTROL

Reg 20 D0 CB CHROMA BANDPASSCENTRE FREQUENCY

To compensate for the roll-off at higher frequency in the SAW filter / IF part, the centre frequency of thechroma bandpass can be shifted upwards.

0 = Centre frequency at Fsc (chroma subcarrier frequency)1 = Centre frequency at 1.1 x Fsc (in principle used for internal mode only)

Reg 20 D1 ACL AUTOMATIC COLOURLIMITING

For signals with very large chroma/burst ratio this ACL can be enabled to maintain correct colour saturation.ACL has no influence on colour sensitivity (e.g. colour loss in VCR feature mode). It is not recommended touse the ACL function when SECAM is identified.

0 = ACL function not enabled (for standard burst/chroma transmissions)1 = ACL function enabled (for non-standard burst/chroma ratio)

Reg 20 D2 MUS MATRIX USA

Selects between the two built-in NTSC matrices.

0 = Japanese NTSC matrix1 = USA NTSC matrix

Reg 20 D3 MAT MATRIX SELECTION

Forces PAL matrix, even when NTSC is detected.When RGB-2 input is used, PAL matrix should be selected for correct colour reproduction ( MAT = 0)because the RGB -> YUV conversion is complementary to the PAL matrix.

0 = matrix adapted to standard (PAL matrix or by MUS selected NTSC matrix)1 = PAL matrix

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Reg 20 D4..7 CM0..3 COLOUR DECODER MODE

These bits select one of the automatic modes or forces to one of the standards.

CM3 CM2 CM1 CM0 Colour decoder mode Subcarr. freq.

0 0 0 0 PAL/NTSC A0 0 0 1 Spare0 0 1 0 PAL A0 0 1 1 NTSC A0 1 0 0 Spare0 1 0 1 PAL/NTSC (auto) B0 1 1 0 PAL B0 1 1 1 NTSC B1 0 0 0 PAL/NTSC(auto) ABCD1 0 0 1 PAL/NTSC(auto) C1 0 1 0 PAL C1 0 1 1 NTSC C1 1 0 0 PAL/NTSC (auto tri-normal) BCD1 1 0 1 PAL/NTSC (auto) D1 1 1 0 PAL D1 1 1 1 NTSC D

Table 4: Automatic colour standard manager settings

Frequencies:- A: 4.433619 MHz- B: 3.582056 MHz (PAL N)- C: 3.575611 MHz (PAL M)- D: 3.579545 MHz (NTSC M)

Reg 21 D0 FCO FORCED COLOUR ON

With this bit the colour killer function can be disabled to ensure maximum colour sensitivity under abnormalconditions e.g. VCR trick modes. Only active when one single colour system is forced.

0 = normal colour killer function1 = no colour killing (in forced single colour system mode only)

Reg 21 D1 BPS BYPASS CHROMA DELAYLINE

When active then the U, V signals bypass the built-in base band chroma delay line (e.g. for NTSC orPALplus) and are internally amplified by 6 dB to correct the levels.0 = Baseband chroma delay line active1 = Bypass baseband chroma delay line

Reg 21 D2 PSNS PAL SENSITIVITY NOISYSIGNALS

With this bit the colour killer sensitivity level for PAL can be increased for noisy signal conditions. Thisfeature is intended for the ASIAN countries.

0 = Normal PAL sensitivity, killing level typical 26 dBuV1 = Increased PAL sensitivity, killing level typical 21 dBuV

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Reg 22 D0, 1 INA, INB INPUT SELECTION

Selects CVBS/YC video inputs.

INA INB Selected signal

0 0 CVBS10 1 CVBS2/Y

1 1 Y/C

Table 5: Video input selection

Reg 22 D3, 4 CMB0, 1 COMB PIN FUNCTION

CMB1 CMB0 Function

0 0 AVL / SNIF active (depends on SIF bit)0 1 Output voltage 2.3 Volt + subcarrier1 0 Output voltage 0 Volt1 1 Output voltage 4.5 volt

Table 6: Comb filter pin function selection

Reg 22 D5 SVO SELECTED VIDEO OUT

With this bit it is possible to realise a monitor out function on pin 38.When SVO = 0, pin 38 delivers the CVBSINT out (including sound carrier) from IF.When SVO = 1, the signal, selected by the CVBS switch is routed to pin 38. At the same time, inside the IF

the CVBSINT out is muted by forcing VSW = 1.To realise the monitor out function, both SVO and INA, B must be used.

SVO INA INB Signal on pin 38 Level pk - pk 1)

0 X X CVBSINT out + intercarrier sound from IF 2)

2.5 V1 0 0 Internal CVBS pin 40 (not CVBSINT from IF!!)

3) 2.0 V

1 0 1 External CVBS pin 42 2.0 V

1 1 0 Y (pin 42) + C (pin 43) 2.0 V

Table 7: Selected video out options and corresponding video output levels

1) The level difference is related to technical differences between IF output and needed headroom in the

CVBS switch block.

2) Intercarrier sound only in case of mono FM versions3)

Note that in this condition CVBSINT out from IF is muted (VSW is forced to 1 for SVO = 1).When in this condition another CVBS signal (e.g. from a satellite tuner) is fed to the internal CVBS input pin40, this signal will be available on pin 38.To have CVBSINT out from IF available on pin 38, SVO must be set to 0!!

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Reg 23 D0 RGBL RGB OUTPUTS LOW

When this bit is set high, the RGB outputs are below 1.5V. This can be applied at start-up and switch-off for

picture blanking.0 = normal operation1 = RGB outputs blanked, black current loop disabled.

Reg 24 D0 VID VIDEO IDENT COUPLING

With this bit it is possible to activate a coupling between video ident (IFI) and PHI-1 loop. If this coupling isactive and no video is present (IFI = 0), the PHI-1 loop is switched to very slow. This assures a stable OSDdisplay under noisy conditions e.g. during search tuning or when no antenna input is connected (tunernoise). 0 = Video ident (IFI) switches PHI-1 loop on/off

1 = No influence of the video ident (IFI) on the PHI-1 loop

Reg 24 D1 VIM VIDEO IDENT MODE

The IF ident circuit (output IFI) can be connected to the internal CVBS input (CVBSINT) or after the inputselection switch to the selected video input for display. (see also VID reg 24 D0)

0 = Video ident circuit coupled to CVBS1INT1 = Video ident coupled to selected CVBS or Y/C (see INA, INB)

Reg 24 D2 STB STAND BY

When set to 1, the horizontal drive is initialised via slow start. Note that after power-up the horizontal driveonly will be released when POR = 0 and all I

2C registers are written. It is possible to set STB to 1 when only

the 3.3 Volt supply is present. In this way, the horizontal drive will be initialised via slow start and the + 8 Voltsupply can be derived from the flyback transformer. When STB is set to 0, the horizontal drive is stoppedvia slow stop and the RGB outputs are set for 1 mA discharge current of the picture tube (measured via theblack current loop). When no picture tube discharge via RGB drive is needed (e.g. applications with EHTbleeder) it is possible to force black switch-off by setting RBL = 1 together with STB = 0

0 = device in stand-by1 = device operational

Reg 24 D3 POC PHI ONE CONTROL

When this bit is switched to high, the PHI-1 loop is switched off completely.In this mode very stable OSD or TEXT can be displayed, independent of the selected source. This is useful

for e.g. installation menu’s, blue mute, ea. It is also useful to measure the free running frequency using inthis condition.

When forcing POC = 1, immediately SL is forced 0. This has the following consequences:- AFC information is disabled- Vertical divider switches immediately to mode, set by FORF/FORS- SL cannot be used to detect a valid CVBS signal on the selected input, IFI can be used for this purpose

For stable OSD during search tuning, it is better to use VID in stead of POC, see below:0 = Synchronisation active1 = Synchronisation not active

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Reg 24 D4, 5 FOA, FOB FORCED PHI ONE TIMECONSTANT

These two bits determine the speed of the phi-1-loop. It can be forced to slow and fast or set it in theautomatic mode. In auto mode a noise detector circuit can switch to slow time constant, when the signalhas too much noise.

FOA FOB PHI –1 loop mode

0 0 Auto, PHI-1 gating in slow mode1)

0 1 Slow, always gating (only for test purposes.)1 0 Slow/fast depends on noise detector, always gating1 1 Fast, no gating

Table 8: PHI-1 loop speed settings

Note:1)

Not suitable for weak video recorder signals, because of active ph-1 gating in slow mode. Use FOA,FOB=1,1 instead.

Suggested use of these bits:

Normal off-air reception conditions or cable:- Use FOA/FOB = 0 0 for program numbers, VCR reception via antenna possible- Use FOA/FOB = 1 1 for external input (VCR, DVD) Difficult off-air reception conditions (Weak signal and/or interference):- Use FOA/FOB = 1 0 for program nr. (optimal off-air reception due to gating)- Use FOA/FOB = 1 1 for special program nr. (program 0) for VCR reception via antenna- Use FOA/FOB = 1 1 for external input (VCR, DVD)

Reg 24 D6 HP2 HORIZONTAL REFERENCEOSD FROM PHI-2

Determines where the horizontal reference for OSD positioning is taken.0 = Ref. from PHI-1 (needed when HB and HP (see geo) are used)1 = Ref. from PHI-2 (For problems with OSD, no HB, HP possible)

Reg 25 D0 NCIN NO VERTICALCOINCIDENCE

Vertical divider mode: This forces the vertical divider immediately to the search window, to speed up verticalcatching at channel change. It saves the time for the vertical divider to switch back from standard mode tonarrow window and from narrow window to search window, which takes at least 6 fields.

For optimal performance, NCIN should be set back to 0 when SL becomes 1 (sync lock, indicating a validinput signal is detected) after forcing the vertical divider to the search window.

0 = Normal operation of the vertical divider1 = Vertical divider switched to search window

Reg 25 D1 DL DE-INTERLACE

0 = Interlace1 = De-interlace

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Reg 25 D2, 3 FORS/FORF FORCED FIELDFREQUENCY

This forces the vertical divider in a 60 Hz mode or automatic. In auto mode it can be given a preference for50 or 60 Hz (useful for multi-system situations when video signals are only 50 or 60 Hz) or to keep the lastdetected field frequency.

FORF FORS Vertical frequency

0 0 Auto, 60 Hz if not locked0 1 60 Hz forced

1)

1 0 Auto, keep last detected frequency2)

1 1 Auto, 50 Hz if not locked

Table 9: Vertical frequency selection options

Note:1)

60 Hz is immediately forced after writing FORF, FORS, so when a 50 Hz signal is present, it will start

rolling.2)

This mode is useful for areas where both 50 and 60 Hz signals can be received but due to bad receptioncondition the signal can be lost for a short moment. In that case, vertical catching is fast and screendisturbance remains limited, because the vertical divider does not change the vertical frequency.

Reg 25 D4 OSO OVERSCAN SWITCH OFF

Enable switch-off in vertical overscan. When switching to stand-by, the vertical deflection is kept in overscanposition at the top of the screen while during switch-off the picture tube is discharged with a fixed current sothe white drive is less visible

0 = Switch-off undefined1 = Enable switch-off in vertical overscan function

Reg 25 D5 FSL FIXED VERTICAL SLICINGLEVEL

Forces the slicing level during vertical synchronisation to 60 % amplitude of the sync pulse (measured fromblack level). Can solve problems with decoders, which insert a wrong and varying black level during verticalsynchronisation.Normal, the slicing level during vertical (measured from black level) is 35% at strong signal and 60% atnoisy signals (S/N < 20 dB), switched by the built-in noise detector.

0 = Automatic vertical slicing level1 = Vertical slicing level fixed to 60% of sync amplitude

Reg 26 D0 HCO HOR. COMPENSATION

EHT tracking mode. Selects to modulate only vertical or vertical and East-West with the voltage on pin 36.EHT tracking compensates picture size variations due to beam current variation. HCO = 0 is useful whenEast-West and vertical require different gain for the compensation. Vertical compensation can then be donevia the IC, while the East/West compensation is realised outside the IC with a different gain.

0 = EHT tracking only on vertical1 = EHT tracking on both vertical and East-West

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Reg 26 D1 EVG ENABLE VERTICAL GUARD

With this bit set high, a vertical guard failure will immediately blank RGBOUT to avoid damage to the picture

tube. To use this function, a vertical guard pulse has to be connected to pin 50 (BLKLIN / Vertical guard).When no vertical guard pulse is connected to pin 50, EVG must be set to zero to prevent unwanted blankingof RGBOUT.

0 = Only vertical guard detection (output bit NDF)1 = Detection (output bit NDF) and protection by blanking RGBOUT

Reg 26 D2 AVG ADJUSTMENT VG2VOLTAGE

When this bit is set high, the vertical deflection remains running and a black bar is visible at the top of thescreen. The beam current measurement is done during the black bar.The AVG bit can be used for Vg2 alignment.

0 = Normal operation1 = Vg2 adjustment (WBC and HBC bits in output byte 01 can be read)

Readout of the WBC and HBC bits via OSD in the lower half of the screen can also be used.

Reg 26 D3 SBL SERVICE BLANKING

This bit blanks the bottom half of the picture, starting exactly in the middle of the vertical scan (deflectioncurrents are zero). This bit is intended to align the vertical parameter VS in order to compensate forcomponent tolerances. See also the chapter about geometry alignment.

0 = No service blanking1 = Service blanking active

Reg 26 D4 XDT X-RAY DETECTION

This bit selects whether at triggering of the X-ray protection (voltage on pin 36 higher than 3.9 Volt) besidessetting XPR = 1 the device switches automatically off via the slow stop procedure with RGB drive for picturetube discharge or that only the XPR bit is set and latched.

0 = XPR + automatic switch-off1 = XPR only

Reg 26 D5 DFL DISABLE FLASH PROTECT.

The flash protection function on the PHI-2 pin 16 can be disabled using this bit. In this way, unwanted

switch-off from H-out by triggering due to disturbance can be prevented when this function is not used. Thisincreases the robustness (H-out remains running) under conditions like ESD, flash, etc. at the cost of higherstress for line transistor etc.

0 = Flash protection enabled1 = Flash protection disabled

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Reg 26 D6 AFN AFC NOT ACTIVE

The AFC information is updated every vertical retrace. Under weak signal conditions, this updating can

cause some disturbance of the AM sound output. By setting AFN = 1 the AFC updating can be disabled tominimise the disturbance. Advice for use:- When a PLL tuner is used and the transmitter is stable, switch-off the AFC when receiving AM sound.- When transmitter drift is expected, enable very short the AFC once every five minutes (two fields is

enough) to retune0 = AFC normal active, updated every vertical retrace1 = AFC circuit switched off

Reg 27 D0 STM SEARCH TUNING MODE

Can make the coincidence detector less sensitive, to avoid that search tuning systems stop at very weaksignals (output bit SL).

0 = Normal operation1 = Reduced dynamic sensitivity of coincidence detector (approx. 5 dB)

Note: this function is effective in static signal conditions

Reg 27 D1 IFS IF SENSITIVITY

When switched to an external source, the cross talk of noise on the internal signal to the external signal canbe reduced. This function is mainly intended for no-antenna input conditions.

0 = Normal sensitivity1 = Maximum gain reduced by 20 dB (sensitivity in practice 12dB less)

Reg 27 D2 AFW AFC WINDOW

AFC window around IF centre frequency: (to optimise search-tuning speed, see also output bits AFA andAFB).

0 = Nominal window, about 100 kHz wide1 = Enlarged window, about 300 kHz wide

Reg 27 D4 VSW VIDEO MUTE SWITCH

When this bit is set to high, it is possible to use the internal CVBS input pin 40 (CVBS1INT) to supply anexternal CVBS signal.

0 = Normal operation1 = IF video signal switched off (pin 27 and 38 are forced to ground level)

Reg 27 D5..7 IFB, IFC FREQUENCY SELECTION

IFB IFC IF frequency

0 0 58.75 MHz0 1 45.75 MHz1 0 38.90 MHz1 1 38.00 MHz

Table 10: IF frequency options

These frequencies are suitable for all market areas.Any adaptation on frequency response should be done via the SAW filter.

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Reg 28 D0 FFI FAST FILTER IFPLL

For RF-transmitter input signals with large phase modulation. (Not suitable for overmodulation, that requires

a slow filter)0= normal time constant for standard transmitter signals1= fast time constant for special market areas

The function can be used for both positive and negative modulated signals.The standard loopfilter of 390E/100nF is recommended for both settings of FFI.

Use FFI = 1 only:- For TV sets for special market areas. Set FFI = 1 during IC-initialisation- After sale service. Set FFI = 1 via service mode in case of specific field problems.See also application info on the IF-PLL loopfilter pin 37 in the IF Chapter.

Reg 28 D1, 2 AGC0, 1 AGC TIME CONSTANT

With previous IC versions an external IF-AGC capacitor was used. The standard value then was 2.2uF thatis now equivalent to the “norm” mode, see table on next page.The AGC speed can be adjusted with AGC1, AGC0 for:

AGC1, 0 AGC speed Equivalent AGCcapacitor

Function

0 0 0.7 x norm 3.1uF Slow AGC action, reserved if required in the field

0 1 Norm 2.2uF Standard recommended setting, optimal for bothpositive and negative modulation

1 0 3 x norm Faster AGC for negative modulation as toimprove airplane flutter performance

1 1 6 x norm Fastest AGC for negative modulation as toimprove airplane flutter performance

Table 11: AGC speed settings

Reg 28 D4 IFLH IF LOCK HOLD

Special bit for AV mode. Prevents IF video disturbance in case LOCK becomes zero at high modulationdepth. With IFLH it’s possible to make the IF-PLL calibration under control of IFI and not of LOCK anymore.

0 = standard, auto calibration under control of LOCK1 = calibration under software control, see below.

Recommended:If VIM = 0 than define IFLH := IFI.If VIM = 1 and in STB mode set VIM=0, so than IFLH := IFI which is same as aboveIf VIM = 1 and in AV mode: set IFLH=1 for no calibration at all. The IC automatically calibrates after power-on or after change of IFB and IFC.Some risk: after a flash the PLL might need re-calibration as to avoid PLL-out lock. This re-calibration willnot occur unless also a power on reset is active.

Reg 28 D7 SIF SOUND CARRIER IF INPUT

0 = No SIF input, pin can be used for combfilter or AVL1 = SIF input/output available when CMB0/1 = 00 This allows insertion of external sound pass

filters, also separate SIF signal from a other source can be applied.

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Reg 29 D0..2 FMB, FMA FM SOUND CARRIERSELECTION

FMB FMA Frequency

0 0 5.5 MHz0 1 6.0 MHz

1 0 4.5 MHz1 1 6.5 MHz

Table 12: Sound carrier selection

Reg 29 D3, 6 SM0, 1 SOUND MUTE

SM1 SM0 Mute at de-emphasis pin 28

0 1 Sound enhancer ( digital acquisition pulse limiter )

1 0 Mute on

1 1 Mute offTable 13: Sound mute options

The sound enhance option improves the sound noise behaviour under weak signal conditions. Theacquisition pulses are real time automatically muted. Recommended setting:

01 for no mute condition (when e.g. SL=1 and IFI = 1)10 for mute condition (when e.g. SL = 0 or IFI = 0)

Note: Mute on (SM1, 0 10) sets AVL (if present) in high gain mode (15dB) for fast settling time duringchannel switching.

Reg 29 D5 FMWS FM SEARCH WINDOWWIDTH

0 = Standard acquisition window for narrow band PLL (+ and -225kHz)1 = Wide acquisition window for narrow band PLL (+ and -450kHz) for signals with large FM swing.

The wide window setting allows more overmodulation of the soundcarrier with FM signals.

Reg 29 D7 AGN GAIN FM DEMODULATOR

Enables +6dB extra gain in the FM demodulator. To be used for 25kHz deviation NTSC video standard orfor specific customer needs.

0 = normal operation1 = gain + 6dB

Note: THD figures are higher in +6dB condition.

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Reg 2A D0..3 CL0..3 CATHODE DRIVE LEVEL

This can be used to adapt the black/white drive of the RGB outputs to match the required drive level for the

picture tube.The table gives approximated values.

CL3 CL2 CL1 CL0 Variation Cathode Drive Level

0 0 0 0 50 VBL-WH1 0 0 0 74 VBL-WH1 1 1 1 95 VBL-WH

Table 14: Cathode drive level

Conditions:- Nominal CVBS input signal (1 V pk-pk at CVBS input 40 or 42)- Nominal settings for contrast, WPA and no peaking- Black stretch switched off

- Gain of output stage such that no clipping occurs- Beam current limiting not active- Tolerance on given values: +/- 3 V.

Reg 2A D4 AKB AUTO KINE BIASING

With this bit, the automatic black current stabilisation loop can be switched off. This can be used for LCDapplication and other applications without picture tubes.

0 = Automatic black-current stabilisation (ABS) loop enabled1 = ABS loop disabled (suitable for LCD applications)

Reg 2A D5 RBL RGB BLANKING

Controls blanking of the RGB outputs. Can be used to keep the picture black at start-up of the set until theCCC loop is stabilised and the cathode emission is high enough to display a decent picture.Setting RBL = 1 before switching to Stand-By prevents the RGB outputs going high and discharging thepicture tube with a white flash.

Can also be used for blanking RGB outputs when black current loop is disabled (AKB = 1) for LCDapplications.

0 = Normal picture visible1 = RGBOUT (pins 51, 52, 53) blanked

Reg 2A D6 IE2 RGB INSERTION ENABLE(FAST BLANKING.)

Enable fast blanking (pin 45) of YUV/RGB-2 input.0 = Second fast blanking disabled1 = Normal fast blanking function

Reg 2B D0 HBL HOR. BLANKING MODE

Widens the horizontal blanking for well defined edges using underscan (e.g displaying 4:3 picture on 16:9picture tube)

0 = Normal horizontal blanking, related to horizontal flyback pulse width1 = Wider blanking (coupled to PHI-1)

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Reg 2B D1 YUV0, 1 RGB/YUV INPUT SELECTIONFOR PIN 46, 47, 48

YUV1 YUV0 Mode

0 0 RGB input activated

0 1 Spare1 0 YUV activated

1 1 YPbPr

Table 15: RGB/YUV input selection modes

Note: For the RGB input the synchronisation has to be fed to CVBS on pin 42.

Reg 2B D4 SOY SYNC ON Y

Reg 2B D5 VSD VERTICAL SCANDISABLE

To be used for Vg2 alignment. Setting the bit =1 sets the vertical deflection to zero (line in the middle of thescreen).The black level can be adjusted via the brightness control to the required DC level so that the correct cut-offlevels can be made at the CRT cathodes.The Vg2 can then be adjusted so that a visible line is just shown.

For more accurate Vg2 alignment the beam current can be set to 12-20 µA using the read-out bits HBC

(above / below) and WBC (beam current between 12-20 µA).These bits are only valid when VSD = 1.

0 = Normal vertical deflection1 = Vg2 alignment mode, No vertical deflection, HBC and WBC (valid for black levels >2.5V at theRGB outputs)

Reg 2C D1 QSS MODE QSS AMPLIFIER

Switches the QSS amplifier on and off0 = QSS amp not active1 = QSS amp active

Reg 2C D2 AVL AUTOMATIC VOLUMELEVELING

0 = AVL not active1 = AVL active and regulates high audio levels as e.g. from TV commercials

Reg 2C D5 ADX AUDIO EXTERN

Switch between internal and external sound

ADX Audio selection

0 Internal audio signal1 External audio signal

Table 16 Audio selection options

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Reg 2D D0 BKS BLACK STRETCH

This function stretches offsets in black of non-standard signals to black level

0 = Black stretch off1 = Black stretch on (to be switched off for WPA adjust)

Reg 2D D3 DSK DYNAMIC SKIN TONE

Enables dynamic skin tone function.0 = off1 = on

Reg 2E D4, 5 RPO0, 1 RATIO PRE_OVERSHOOT

RPO1 RPO0 Setting0 0 1:10 1 1:1.251 0 1:1.51 1 1:1.8

Table 17: Ratio pre- and overshoot

Reg 2E D6 BPB BANDPASS FILTER BYPASS

Bypasses the internal bandpass filter.0 = bandpass filter switched on (default)1 = bandpass filter bypassed

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5.2 OUTPUT CONTROL BITS

Reg 00 D0..3 CD0..3 COLOUR DETECTION

Shows the colour standard that is identified

CD3 CD2 CD1 CD0 Colour standard Subcarr. Freq

0 0 0 0 no colour standard identified0 0 0 1 NTSC A0 0 1 0 PAL A0 0 1 1 NTSC B0 1 0 0 PAL B0 1 0 1 NTSC C0 1 1 0 PAL C

0 1 1 1 NTSC D1 0 0 0 PAL D

Table 18: Detected colour standard

Frequencies:- A: 4.433619 MHz- B: 3.582056 MHz (PAL N)- C: 3.575611 MHz (PAL M)- D: 3.579545 MHz (NTSC M)

Reg 00 D4 SL SYNC LOCK

Horizontal lock indication:0 = Not locked1 = PHI-1 loop locked to the incoming video signal

Reg 00 D5 LOCK IF-PLL LOCK

The lock bit becomes one when the IF-PLL is in-lock, independent upon video contents. This means the bitcan also be used to identify sound carrier signals.

0 = PLL not locked1 = PLL locked

Note: AFC information is only valid when LOCK=1, see related bit, IFLH

Reg 00 D6 IFI VIDEO IF IDENT

Detects video at IF or selected source (see also VIM bit). This is a stand-alone detector that recognisesvideo signals, containing line frequent components.

0 = No video signal identified1 = Video signal identified

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Reg 00 D7 POR POWER ON RESET

Power on reset: Indicates detection of a power failure of the 3.3 Volt supply (including switch-off of the TV

set). It remains high until the status bytes have been read successfully to enable also to detect short powerfailures. When a failure is detected, the internal data is not reliable any more and should be refreshed.During normal operation the POR status should be read continuously, before sending any input data. During

start-up, the µprocessor part should read the IC status until the POR bit is low, immediately followed by thestart-up procedure.

0 = Device operational1 = Power failure detected

Reg 01 D0 IN2 RGB/YUV INPUT2 STATUS

Reflects the level on the fast blanking input pin 45.Level is only checked during vertical retrace to enable differentiation between OSD insertion (IN2 remains

0) and full RGB/YUV sources (IN2 becomes 1)0 = Pin 45 low (< 0.4V), no insertion1 = Pin 45 above insertion level (>0.9V, RGB/YUVIN inserted when IE2=1)

Reg 01 D1 BCF BLACK CURRENT LOOPFALSE

Reflects the condition of the black current loop. Can be used at start-up or for regular check during normaloperation to indicate RGB stage malfunctioning.

0 = Black current loop is stabilised1 = Black current loop is not stabilised

Reg 01 D2 HBC HELP ABOVE/BELOWBCL WINDOW

Valid when VSD = 1 (no vertical deflection). Can be used together with WBC (Window Beam Current loop)for factory alignment of the Vg2. Reading HBC indicates which direction to turn the Vg2 potentiometer to

bring the beam current in the window of 12 - 20 µA (see also WBC below).

Note that HBC switches from low to high at the moment the beam current is in the window of 12 - 20 µA(and does not toggle in the middle of the window!)

0 = below 12 µA

1 = above 12 µA

Reg 01 D3 WBC BCL WINDOW

Valid when VSD = 1 (no vertical deflection). Can be used together with HBC (Helper Beam Current loop) forfactory alignment of the Vg2.

Reading WBC indicates whether the beam current is in the window of 12 - 20 µA while the bit HBCindicates whether the current is above or below the window (see also HBC above)

0 = outside window

1 = inside window (beam current 12 - 20 µA)

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Reg 01 D4 IVW IN VERTICAL WINDOW

Condition vertical divider window:

0 = No standard video signal detected1 = Standard video signal detected, 522-528 or 622-628 lines/frame, vertical divider in narrowwindow or standard mode

Reg 01 D5 FSI FIELD SYNC INFORMATION

Field frequency indication of the selected CVBS signal0 = 50 Hz1 = 60 Hz

Reg 01 D6 NDF NO VERTICAL DEFLECTION

This bit is set to 1 when the vertical guard pulse at pin 50 (BLKIN / Vertical guard) is wrong.0 = Vertical deflection OK (correct guard pulse present)1 = Failure detected in the vertical output stage (incorrect guard pulse present)

Reg 01 D7 XPR X-RAY PROTECTION

This bit is set to 1 when an overvoltage is detected (voltage on pin 36 EHT / XPR > 3.9 Volt). When XDT isset to 0, the horizontal drive is stopped via slow stop including RGB drive for 1 mA discharge currentmeasured via the black current input.The bit is latched when the voltage on pin 36 > 3.9 Volt and can only be set to zero when the status bytesare read after the voltage on pin 36 has dropped below 3.9 Volt. The microprocessor part should monitor

XPR and when XPR = 1 the bit STB must be set to 0. When no problem seems present, the set can berestarted by setting STB = 1. Setting STB = 0 after XPR = 1 is essential because immediate writing STB = 1will not release the horizontal drive.

0 = No over-voltage detected1 = Over-voltage detected on EHT input pin 36

Reg 02 D0 FML FM PLL LOCK

0 = No lock1 = Indicates that the FM PLL is in lock

Reg 02 D1 FMW FM PLL IN WINDOW

0= Indicates the PLL VCO carrier is tuned within the catching range1= Out of window

A valid sound carrier is found when FML=1 and FMW=0.

Note: For search tuning algorithms, the sound carrier detection have to take place in a certain order toprevent that 4.43 MHz colour carrier can be detected as 4.5 sound carrier. Recommended sequence orderis: 5.5 MHz, 6.0 MHz, 6.5 MHz, and 4.5 MHz.

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Reg 02 D2, 3 AFA, AFB AFC OUTPUTS

AFA 0 = Outside window (see AFW bit)

1 = Inside windowAFB 0 = Below reference, increase tuner frequency

1 = Above reference, decrease tuner frequency

AFC output information is available for search tuning. An automatic AFC loop is achieved together with themicroprocessor and tuner. Because of the alignment free IF, AFC alignment is not required, the PLL iscalibrated fully automatically. The figure below gives the AFC bit status in relation to the incoming IF-frequency.

AFC read-out:- The applied IF-frequency is correct when in-window, AFA bit is "1" and AFB is (close to) altering.- AFC information can be read-out continuously but is updated during the vertical retrace. Therefore a

minimal wait of 20ms is required between changing the tuner frequency and reading-out AFA/B.- AFC information is only available and valid when LOCK=1. This is inherent to the alignment free

concept.

Note:- -AFC is valid when LOCK=1. This however does not guarantee that a picture carrier is found. E.g. the- PLL can also lock to a sound carrier. For this reason it’s advised to check also the sync lock bit SL.- -AFC remains valid in full OSD mode when POC=1 (than SL=0 but that is a don’t care for AFC)- -AFC remains valid in stand-by mode when STB=0 (than SL=0 but that is a don’t care for AFC) and is

useful for TV-VCR application.

- -AFA bit is forced to zero during automatic AFC calibration (takes place after signal loss). This prevents“false” AFA=1 read outs and optimizes the search tuning.

AFC accuracy:- High AFC resolution of 25kHz for both AFA and AFB (indicated by the gray area)- The AFA window position has a fixed relation to AFB. This ensures the window width of 100 and 300kHz.

Search tuning:- Have AFW=1 for large window. This allows larger frequency steps and faster search tuning.- Wait for LOCK and (SL or IFI) =1 before reading AFC information.- Increment RF frequency until AFA=1. Tune in small frequency steps until AFB just toggles.- For non-search tuning (normal TV) operation it’s recommended to select the normal window, have

AFW=0.

38.9MHz

100kHz

300kHz

above reference below reference

outside windowRF too low

IF too high

outside windowRF too high

IF too low

AFA

AFB

25kHz

AFA

reference

normal window

large window

Figure 2: AFC output bits

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Fine-tuning:The digital AFC information provides an accurate AFC loop. Fine-tuning is possible in an open AFC loop.Especially with PLL-tuners it’s easy to add a frequency offset via the microprocessor while ignoring the AFCoutput bits.

Reg 02 D4 QSS QSS/FM VERSION

This can be used to verify whether the device is a QSS or FM intercarrier type.0 = FM intercarrier1 = QSS

Reg 02 D7 SUP + 8 VOLT SUPPLY PRESENT

Indicates whether the + 8 Volt supply is present.When low power start-up is used with only 3.3 Volt supply present, the device will be first full operational

when this bit reads 1 (and the + 8 Volt supply is present).When during normal operation the + 8 volt drops below the detection level (about 6.2 Volts, 0.2 Voltshysteresis) the horizontal drive is switched off. When the +8 Volt supply rises again above detection level(about 6.4 Volts), the horizontal drive is automatically switched on via slow start. In this way, the devicerecovers automatically when a short power dip on the +8 Volt is present.When the +8 Volt is derived from the EHT flyback transformer, a drop in the + 8 volt supply can disable the+ 8 Volt supply because the horizontal drive is switched off. To restart the horizontal drive in this condition,first STB must be set to 0 and then to 1 again.

0 = no + 8 Volt supply present1 = + 8 volt supply present

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6 APPLICATION INFORMATION

Microprocessor GeneralIn this chapter, especially the hardware design aspects of the Micro-Controller pins are covered. For theprogramming aspects please refer to the Micro-Controller SFR registers of the embedded Micro-Controllerpart as defined in the specification.

* I/O portsPin 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 62, 63, 64

The I/O pins of the µprocessor can be configured in many ways. All port functions can be individuallyprogrammed by use of the SFR registers.Each port pin can be individually programmed in four output configurations. About detail please refer Table1 and Table 2.

Open drain

In this mode, the port can function as in- and output. It requires an external pull-up resistor. The maximumallowable supply voltage for this pull-up resistor is + 5 Volt.So in this mode, it is possible to interface a 5 Volt environment like I2C with 3.3 Volt supply of the Micro-Controller part.

Push-Pull

The push-pull mode can be used for output only. As well sinking as sourcing is active, which leads to steepslopes. The levels are 0 and VddP, the supply voltage of the output pins on pin 61, usually 3.3 Volt.

Quasi-bidirectional

This mode is a combination of open drain and push-pull. Normally the port is configured as open drain and itneeds a pull-up resistor to the same supply voltage as VddP (usual 3.3 Volt).Only during a low to high transition, the port is switched to push-pull operation for one clock cycle (166 ns)to speed up the rising edge.This is the default mode of all I/O pins after a reset.Note: This mode cannot be used with pull-up resistors to + 5 Volt!

High impedance

This mode can be used for input only operation of the port.Note: To minimise power consumption in stand-by, it is best to program all port pins in high impedance

mode when entering Stand-By mode.

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Extra functions of port pins

A number of port pins have extra functionality. This extra functionality can be programmed via the SFRregisters of the Micro-Controller. In the table below, the available extra functions are listed.

[ Table 1 ] TDA935XPS/6XPS/8XPS - SDIP64 Package

Port Pin 8mAsink

current

I2C

busPWM14 bits

PWM6 bits

ADC8 bits

Int. Timerexternal

input

P1.3 1 Tim. 1

P1.6 2 SCL

P1.7 3 SDA

P2.0 4 x

P3.0 5 x x

P3.1 6 x xP3.2 7 x x

P3.3 8 x x

P0.5 10 x

P0.6 11 x

P1.0 62 Int. 1

P1.1 63 Tim. 0

P1.2 64 Int. 0

Below, a more detailed description of the extra functions is given.

- 8 mA sink current (Port 0.5, 0.6 / Pin 10, 11)

These pins have the same functionality as the general I/O pins (same 4 modes) but in addition, their current

sink capacity is 8 mA in stead of 4 mA. These pins can be used for direct drive of LED ’s.

- I2C port (Port 1.6, 1.7 / Pin 2, 3)

Two output pins can be programmed as SDA (pin 3, port 1.7) and SCL (pin 2, port 1.6). The I2C is multi

master. The pins can be connected via pull-up resistors to the standard 5 Volt supply, commonly used forI2C provided the output is configured as open drain.

- 14 bits PWM (Port 2.0 / Pin 4), 6 bits PWM (Port 3.0..3.3 / Pin 5..8)

The Pulse Width Modulated outputs can be used to generate programmable DC voltage. This DC voltagecan be used for e.g. DC volume control or as DC tuning voltage for a Voltage Synthesized Tuner.The output is a square wave with a fixed frequency and a programmable duty cycle. The duty cycle can be

varied from 0 to 100 %.Transformation of the square wave to a DC voltage is achieved by applying an integrator network. In itssimplest form this can be a series resistor with a capacitor to ground.Standard the output range of the PWM cannot exceed the supply voltage of VddP (3.3 Volt). When highervoltages are needed, the port can be switched to open drain mode with a pull-up resistor to +5 Volt. Finally itis possible to drive a transistor with in the collector a resistor to a higher supply voltage. Because thetransistor inverts the square wave at the base, the duty cycle is reversed, which has to be taken intoaccount in the software.Note that the stability of the DC voltage is pending on the stability of the supply voltage. It is best to have ahigh ohmic load connected to these DC voltages or at least a constant load.

The 14 bits PWM is suitable for Voltage Synthesised Tuning because of its resolution. The frequency is23.44 kHz (repetition rate is 42.66 µs), in 16383 steps (14 bit) the average high time can be programmed

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from 0 to 100 %. (an interleaving technique is used to achieve this high resolution, so not all high times areequal).

The 6 bit PWM is suitable for general DC control like volume. The frequency is 46.88 kHz (repetition rate

21.33 µs), in 63 steps (6 bit) the high time can be programmed from 0 to 100 %.

- ADC input (Port 3.0..3.3 / Pin 5..8)

The Analogue to Digital Convertor uses successive approximation to determine the digital value of theoffered DC signal at the input.The resolution is 8 bits over a voltage range of 0 to 3.3 Volts, which gives 3.3 / 256 = 13 mV per step.However, the port configuration is such, that the input range from VddP - 0.75 Volts to VddP cannot beused. This is related to the threshold voltage of a protection transistor, needed to have the pin tolerant for+5 Volt in open drain mode.So the practical input range is 0 to 2.55 volts (worst case 0 to 2.25 volts with 3.0 Volt supply) with digitaloutput from 00 hex to C0 hex.The inputs can be used for scanning keyboards with resistor ladder network and to determine levels at the

SCART status input.

- Interrupt 0, 1 (Port 1.2 / Pin 64, Port 1.0 / Pin 62)

The external interrupt pins can be activated by level or edge.When programmed for level, the interrupt is active low.When programmed for edge, interrupt 0 will only react on the negative edges of the signal while interrupt 1will react on both positive and negative edges.The interrupt inputs can also be programmed as gating input to enable the timer/counter. When activated, ahigh level enables the timer/counter to count, a low level stops the counting. INT0 controls the gating ofTimer/counter 0 and INT1 controls the gating of Timer/counter 1.

- Timer external input 0, 1 (Port 1.1 / pin 63, Port 1.3 / Pin 1)

When configured as timer, as input the X-tal oscillator frequency divided by 12 is used. For the specified12Mhz X-tal this means an input clock of 1 MHz.When the internal timers are configured as counter, the counter content is increased on every negativeedge of the signal of the external timer input on pin 63 or pin 1.

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6.1 MICROPROCESSOR

Pins 58, 59, 57 XTALIN/XTALOUT/OSCGND 12 MHz crystal oscillator, ground

The crystal oscillator which operates at 12MHz supplies reference signal to different internal circuit blocksone of them being the DCO (digital colour oscillator).The specified Cl of the external crystal is valid for both series or parallel resonance as indicated on nextpage; the TDA937X PS N2 crystal oscillator uses the third configuration.

Figure 3: Crystal configuration

The crystal is placed between pins 58 and 59 and the external capacitors Cx1, Cx2 are connected betweenpins 58, 59 and the oscillator ground at pin 57.It is very important to connect only these two capacitors to this ground pin and to leave the oscillator groundpin floating; therefore do not connect pin 57 to the ground plane.

Example:

Saronix crystal (part no. = 9922 520 00169) has specified Cl=20pF.With Ci=Co = 7pF in Philips demoboard then Cx1=Cx2=33pF in order to have colour symmetry.Also low profile / SMD Saronix Xtals are available for miniature, LCD application etc.

Figure 4: Basic crystal oscillator application

Depending upon PCB layout Ci, Co can be different; then Cx1, Cx2 has to be optimised to have asymmetric colour catching. Avoid large ground planes in the vicinity of the crystal.

The values of Cx1=Cx2 in application should be between 12pF and 56pF, this places a restriction on thevalue of Cl which the crystal manufacturer specifies.For Ci=Co = 7pF then Cl is restricted between the values 13pF and 30pF approximately.

59 5758

12MHz reference

Ci Co

Cx1 Cx2

276K

Cl

Cl 2Cl 2Cl

(1) seriesresonance

(2) parallelresonance (3)

parallelresonance

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The crystal resistance should be less than 100E.The colour catching range is internally defined and is not dependent upon the motional capacitance as isthe case with present analogue colour decoders.The frequency tolerance should be typical +/-30ppm; larger tolerance is allowed but this leads to more

spread in colour assymmetry.

Pin 60 Reset Power On Reset (POR)

The reset pin is coupled to the internal reset circuitry as indicated in the microprocessor block diagram.A Power On Reset (POR) of the microprocessor occurs when VddA (3.3V at pin 54) dips belowapproximately 2.5V and in order to realise this there is a internal direct hardwire communication betweenboth microprocessor and videoprocessor.

Also an external reset circuit in application can be implemented if necessary but is not required.An example of an external reset circuit is given in the application diagram.To prevent false I

2C messages to the non-volatile memory during rise or fall of the supply, also the memory

supply should be switched-off during reset. In this way, data corruption is prevented.

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6.2 IF PART

Pin 23, 24 IFIN1, IFIN2 IF video input

The IF input frequency range is 32 - 60 MHz.

The IF input impedance is 2 kΩ in parallel with 3 pF.

This matches the required load for commonly used SAW filters. DC coupling is allowed, therefore no seriescapacitors between SAW filter and IF input are necessary. For maximum IF performance (also forasymmetric tuners) keep the signal path from tuner to the IF input pins as short and symmetrical aspossible.

The table below gives an example of possible SAW filters.

Type Mode Standard Remarks (sound shelf and IF frequency)

K2955M Intercarrier B/G, D/K -20dB, IF=38.9

K2960M Intercarrier B/G, D/K -14dB, IF=38.9

K2962M Intercarrier B/G -15dB, IF=38.9

K1984M Intercarrier B/G -14dB, IF=38.9

M1970M Intercarrier M/N -14dB, IF=45.75, for FCC EIA/IS-31

M1865D Intercarrier M/N -13dB, IF=45.75, for FCC EIA/IS-31, SIP5D

K3953MK9456M

QSS - VideoQSS - Sound

B/G, D/K, L/L’B/G, I, D/K/L or L’NICAM

Double Nyquist Slope (38.9 and 33.9)Pin 1= L’, pin 2= B/G, I, D/K, LThis SAW filter needs ASYM tuner!

G3962MG9353M

QSS - VideoQSS – Sound

B/GB/G-Nicam

IF=38.9Single bandpass

K9354M QSS – Sound B/G, I, D/K, L Broad single bandpass

Table 19: Siemens Matsushita SAW filter Combinations (all SIP5K packages)

Pin 27 AGCOUT Tuner AGC output

This output pin is used to control the tuner gain for varying RF signal conditions.The tuner AGC pin is an open collector output, which is acting as a variable current source to ground.An external pull-up resistor determines the slope of the tuner output voltage swing and therefore the

maximum IF-input amplitude variation, called slip. Suggested pull-up resistor is 1k2Ω, with R = 180Ω inseries with the pin. The exact resistor value depends on the tuner voltage control range.Once the tuner AGC is active the IF input signal level is constant within the slip. The level on which the

tuner becomes active (Tuner take over point) can be adjusted by I²C bus. With a pull-up resistor of 1k2Ωthe slip is about 4 dB.

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Figure 5: Positive modulated signal with top white reference pulse

The time constant of the tuner AGC can be defined separately from the gain (pull-up resistor) setting.

Stability of the loop becomes difficult when the loop gain is too high (pull-up resistor >> 1k2Ω). Specialattention on stability is required for reception of positive modulated signals (VITS line at 100% and videoabout 50%).

Notice that when the IF-part is muted via VSW = 1, than the tuner output pin is pulled to ground level forminimum tuner gain. After switching on again, the tuner AGC capacitor must re-charge (and also the tunergain). The time constant is determined by the capacitor value and pull-up resistor value.

IF-AGC actions:Optimal IF performance is achieved with gating signals derived from the horizontal oscillator. They becomeautomatically active once the coincidence detector SL = 1.

In external mode the top white AGC remains available only, because in external mode the sync part islocked to the AV signal.

Gating signalsInput modeAlways available Activated when SL = 1

Internal (RF mode) Top white AGC Black clamp AGC AGC line gatingExternal, Decoder mode Top white AGC - -

Table 20: Gating signals in the two input modes

AGC speedThe AGC speed can be adjusted with AGC1, AGC0, see section I2C.

Pin 37 PLLIF PLL loopfilter

The standard loopfilter configuration is R = 390Ω and C = 100 nF in series to ground. The loopfilterbandwidth is 60 kHz and is chosen optimal for fast catching as well as sufficient video suppression to obtainoptimal sound performance.

The loopfilter time constant can be changed by I2C bus function FFI (Fast filter IF-PLL). See for detailed

description of the function, chapter picture improvement.

Note:For special market areas with large phase modulation we recommend:

Keep FFI=0 (off)Change loopfilter R=390E -> 1k5 (2k2 maximum)

C=100 nF -> 47nF (33 nF minimum)Drawback: higher loopfilter bandwidth is less optimal for sound performance (video -> sound)

one field

100% white

Tilt

AGC voltage

Reference

pulse

Video outputsignal

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Pin 38 IFVO / SVO IF video out / selectedvideo out

The level of the video output signal:B/G

Video amplitude is typical 2.5 [Vpp]top sync (fixed by AGC) 2 [V]

Selected CVBS out 2V [Vpp] (When SVO=1)

Although the video output impedance is low it is recommended to avoid high frequency current in the outputdue to for instance sound trap filters. This can be achieved by means of an emitter follower at the video

output with a 1kΩ resistor in series with the base.This pin includes a double function. When SVO = 1 than the selected CVBS signal becomes available for aSCART monitor function. See table below.Some remarks as regards performance issues related to pin 38.

Beat of 2.9 MHz:In some applications a 2.9 MHz beat becomes present at the video output pin. The mechanism is that the3rd Xtal harmonic (3 x 12 MHz) is 36 MHz is injected to the IF input path. Demodulated at 38.9 MHz resultsin a beat of 2.9 MHz.Attention points to minimize this effect:- Symmetrical path between tuner, SAW filter and IF input pins. This gives optimal common mode

rejection.- Avoid radiation of I/O ports into IF-input.- Remove capacitor of decoupling digital supply 3.3V pin 15.- Please see section “Oscillator, supply, decoupling, grounding and supply startup/shutdown”.

Cross talk INT->EXT aspects:- Avoid PCB tracks with video signals being close to the AV input. (voltage cross talk)

- Avoid high video currents in supply lines and or ground close to IC.- Decouple collector of emitter follower(s)- Use minimal current in emitter follower(s)

At no antenna signal condition the video noise peak-peak level (approx. 4 Vpp) is higher than the normalvideo amplitude (2.5 Vpp). Depending upon application this might give extra cross talk and line jitter. Thisnoise level can be reduced by means of I²C busIFS = 1. This reduces the maximum IF-gain by 20 dB. In practice overall sensitivity reduction will only be 12dB due to the combination of tuner and IF stage.

Switch-off IF part:- Switch off the IF-part by means of I²C bus command VSW = 1.

In this condition the video output pin voltage is 0V and tuner AGC output is forced low for minimal tunergain.

Note: after switching on again, the tuner AGC capacitor must charge again. The capacitor value and pull-upresistor defines the time constant.CVBS1 input pin 40 can be used as extra input pin. (This is only possible when VSW = 1 else cross linksbetween IF and sync part will remain active)

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