An Introduction to Starburst Technologies, Inc. for DoD DMSMS Teaming Group by Richard S. Lowry.

An Introduction toAn Introduction toStarburst Starburst

Technologies, Inc.Technologies, Inc.forfor

DoD DMSMS Teaming DoD DMSMS Teaming GroupGroup

by Richard S. Lowryby Richard S. Lowry

Agenda Introduction to Starburst Technologies, Inc.Introduction to Starburst Technologies, Inc.

A brief discussion about our facility, our A brief discussion about our facility, our equipment and tools, our people, and our equipment and tools, our people, and our experience. experience.

VHDLVHDLA short discussion on VHDL. Panacea to re-A short discussion on VHDL. Panacea to re-engineering????engineering????

Increasing Challenges in Dealing with Increasing Challenges in Dealing with ObsolescenceObsolescence

Future ChallengesFuture ChallengesFuture SolutionsFuture Solutions

Introduction to Starburst Technologies, Inc.

About Us Incorporated in October 1992Incorporated in October 1992 We are a Woman-Owned BusinessWe are a Woman-Owned Business Internationally recognized ASIC design firmInternationally recognized ASIC design firm Finest Engineering staff in the WorldFinest Engineering staff in the World

– 100+ years design experience100+ years design experience– 100+ ASIC designs100+ ASIC designs– 50+ design conversions50+ design conversions

Offices located in Orlando, FloridaOffices located in Orlando, Florida

Our Home

Our Facility We lease 3,700 Sq. Ft. of Office Space.We lease 3,700 Sq. Ft. of Office Space. The space includes:The space includes:

10 Offices10 Offices

3 Design Centers with 15 design seats3 Design Centers with 15 design seats

Multi-media Conference RoomMulti-media Conference Room

ReceptionReception

LibraryLibrary

Break/Lunch RoomBreak/Lunch Room

STI’s Design Center Ultra30, Ultra2, Sparc, and NT workstationsUltra30, Ultra2, Sparc, and NT workstations FTP site with T1 connection to InternetFTP site with T1 connection to Internet State-of-the-art Design Software AvailableState-of-the-art Design Software Available

Model Tech System V simulatorModel Tech System V simulator

Renoir High-level design toolsRenoir High-level design toolsLeonardo Spectrum synthesisLeonardo Spectrum synthesisLSI Logic’s Toolkit, CMDE, FlexStream, VegaLSI Logic’s Toolkit, CMDE, FlexStream, VegaTeraForm RTL Place and RouteTeraForm RTL Place and RouteDFT Advisor, BSD Architect, and FastScan DFT Advisor, BSD Architect, and FastScan Verilog -XLVerilog -XL

We Have Extensive ASIC-Related Tool Experience

We have experience in most ASIC tools.We have experience in most ASIC tools.

Verilog-XLVerilog-XL VCSVCS Verilog-NCVerilog-NC QuicksimQuicksim ModelSimModelSim Design CompilerDesign Compiler MOTIVE MOTIVE Leonardo SpectrumLeonardo Spectrum AMBIT Build GatesAMBIT Build Gates PrimeTimePrimeTime Test CompilerTest Compiler FastScanFastScan

DFT AdvisorDFT Advisor PKS PKS FormalityFormality RenoirRenoir

Visual HDLVisual HDL BestBenchBestBench TeraFormTeraForm

Sta rb urst T echnologies O rga niza tion

EUROPE(3)

UNITED STATES(6)

David S. JohnsonDirector

Consulting Services

Richard S. Low ryPresident

Adm inistrative Staff(3)

Elaine Kim berOffice M anager

Vickye L. Low ryChief Executivel OfficerChief Financial Officer

Services Provided Turn Key ASIC and FPGA DesignTurn Key ASIC and FPGA Design Test Bench DevelopmentTest Bench Development Design VerificationDesign Verification Design ConversionsDesign Conversions Verilog TrainingVerilog Training On-Site Design ConsultingOn-Site Design Consulting Design Center ServicesDesign Center Services Core DevelopmentCore Development Design Tool and Methodology Consulting Design Tool and Methodology Consulting

We Have a Strong Customer Base

Ericsson Ericsson Smiths IndustriesSmiths Industries AMIAMI Honeywell/AlliedSignalHoneywell/AlliedSignal LSI LogicLSI Logic Schwartz Electro OpticsSchwartz Electro Optics Lucent TechnologiesLucent Technologies DPT/ADAPTECDPT/ADAPTEC Lockheed MartinLockheed Martin RaytheonRaytheon Theseus LogicTheseus Logic Synova, Inc.Synova, Inc. Esperan, Ltd.Esperan, Ltd. HarrisHarris Metric Systems Cadence Design SystemsMetric Systems Cadence Design Systems

We Have Design Experience in Many Technologies

AT&T BELL LABS - NAVY NTDS chipAT&T BELL LABS - NAVY NTDS chip LOCKHEED MARTIN – GAPP Image Proc. ASICsLOCKHEED MARTIN – GAPP Image Proc. ASICs LOCKHEED MARTIN – RADAR Sig. Proc. ASICsLOCKHEED MARTIN – RADAR Sig. Proc. ASICs LUCENT - GIGABIT Ethernet / PCI ChipLUCENT - GIGABIT Ethernet / PCI Chip APPLE COMPUTER - 3 Graphics Chips - PCIAPPLE COMPUTER - 3 Graphics Chips - PCI ERICSSON - Telecom Network Switch ASICsERICSSON - Telecom Network Switch ASICs ERICSSON - Wireless Internet ASICsERICSSON - Wireless Internet ASICs

We Have Design Experience (Cont’d)

XLNT - Gigabit Ethernet ChipXLNT - Gigabit Ethernet Chip SYMBOL TECHNOLOGIES - Bar Code DecoderSYMBOL TECHNOLOGIES - Bar Code Decoder SYNOVA - Rad Hard MIPS ProcessorSYNOVA - Rad Hard MIPS Processor BROCADE - Router on a chip - RAMBUS & BROCADE - Router on a chip - RAMBUS &

serial links serial links DPT - Data Path Chip – PCIDPT - Data Path Chip – PCI Igt – ATM ASICIgt – ATM ASIC

We Have Extensive ASIC-Related Tool Experience

We have experience with several ASIC Vendor We have experience with several ASIC Vendor tools and design flows.tools and design flows.

AMI CHIP EXPRESSAMI CHIP EXPRESS

HONEYWELL LSI LOGICHONEYWELL LSI LOGIC

LUCENT TILUCENT TI

ASIC-Related Language Experience

We employ industry standard languages in our day-We employ industry standard languages in our day-to-day operations.to-day operations.

We are proficient with both Verilog and VHDLWe are proficient with both Verilog and VHDL– Verilog is our primary HDL for designVerilog is our primary HDL for design– We use VHDL as required.We use VHDL as required.

We employ C/C++ as scripting and modeling We employ C/C++ as scripting and modeling languages.languages.

We Have Conducted All Types of Design Conversions

FPGA to Gate ArrayFPGA to Gate Array 18 18 LSI Gate Array to FPGA 6LSI Gate Array to FPGA 6 LSI Gate Array to AMI ASICLSI Gate Array to AMI ASIC 30 30 LSI Gate Array to Other ASIC LSI Gate Array to Other ASIC 6 6 LSI MIPS Core to HW RADHARD 2LSI MIPS Core to HW RADHARD 2 LSI DSP chip to LSI RADHARDLSI DSP chip to LSI RADHARD 2 2 VLSI Std Cell to LSI Std Cell 4 VLSI Std Cell to LSI Std Cell 4

Design Conversions

We have converted designs from 1,500 to We have converted designs from 1,500 to 150,000 gates.150,000 gates.

Completely regenerated a design from Completely regenerated a design from schematics.schematics.

Have reengineered several proprietary Have reengineered several proprietary megafunctions.megafunctions.

StarBlocks StarBlocks

StarBlocks Starburst Technologies is in the process of Starburst Technologies is in the process of

developing a comprehensive set of developing a comprehensive set of synthesizable functions. Some of the synthesizable functions. Some of the functions that are currently available are:functions that are currently available are:

3 port adders3 port adders fast adders fast adders

two’s compliment multiplierstwo’s compliment multipliers

Reed-Solomon DecoderReed-Solomon Decoder

UARTsUARTs FIFOsFIFOs

VHSIC Hardware Description Language

VHSIC Hardware Description Language (VHDL)

Developed as a procurement specification.Developed as a procurement specification. Evolved into a Synthesis and Simulation Evolved into a Synthesis and Simulation

language.language. Different levels of abstraction available.Different levels of abstraction available.

– Behavioral – Simulation OnlyBehavioral – Simulation Only– RTL – Simulation and SynthesisRTL – Simulation and Synthesis– Gate – Simulation Gate – Simulation

Behavioral VHDL Only describes the functionality of the design.Only describes the functionality of the design.

A + B = CA + B = C

Used for definition and debug of design requirementsUsed for definition and debug of design requirementsandand

For definitions within testbenchesFor definitions within testbenches

Extensive engineering effort required to reproduce aExtensive engineering effort required to reproduce acomplete design from a Behavioral model.complete design from a Behavioral model.

Register Transfer Language (RTL) VHDL

Describes the functionality and architecture of a Describes the functionality and architecture of a design.design.

RTL is the input to Synthesis tools.RTL is the input to Synthesis tools. Additional information is required to duplicate Additional information is required to duplicate

design:design:– Synthesis ConstraintsSynthesis Constraints– Timing ConstraintsTiming Constraints

Some engineering effort required to reproduce aSome engineering effort required to reproduce aComplete design from a RTL description.Complete design from a RTL description.

Gate-Level VHDL Describes the design as related to a particular Describes the design as related to a particular

Manufacturer’s gate-level library.Manufacturer’s gate-level library. Also tied to a particular process.Also tied to a particular process. May not provide a complete description for May not provide a complete description for

conversion:conversion:– Proprietary MegafunctionsProprietary Megafunctions– Memory ElementsMemory Elements– FPGAFPGA

With the exception of missing elements, requires the leastWith the exception of missing elements, requires the leastamount engineering effort to reproduce a complete design.amount engineering effort to reproduce a complete design.

Increasing Challenges in Dealing with Obsolescence

Future Challenges Designs are getting bigger.Designs are getting bigger.

– 1,000,000+ gates1,000,000+ gates

– Embedded IPEmbedded IP

.5 micron lines are shutting down.5 micron lines are shutting down Design documentation typically Design documentation typically

not available.not available.– Misplaced netlistsMisplaced netlists

– No baseline simulationsNo baseline simulations

DSM timing closureDSM timing closure

Future Solutions

First we must instill a discipline in our First we must instill a discipline in our engineers and managers to:engineers and managers to:

Design for Reuse Design for Reuse Reuse Methodology ManualReuse Methodology Manual, , Keating and Bricaud. Kluwer Academic Publishers, 1998Keating and Bricaud. Kluwer Academic Publishers, 1998

Document and Properly Archive DesignsDocument and Properly Archive Designs

Solutions for Today Each design must be evaluated separately.Each design must be evaluated separately. When chip re-engineering is required:When chip re-engineering is required:

– Use as much of the original design database as Use as much of the original design database as possible.possible.

– Understand what pieces to the puzzle are Understand what pieces to the puzzle are missing and what it will take to regenerate these missing and what it will take to regenerate these pieces.pieces.

– Understand the pitfalls of using the newer Understand the pitfalls of using the newer manufacturing technology. DSM designs will manufacturing technology. DSM designs will inevitably have timing closure issues.inevitably have timing closure issues.

Solutions for Today Remember that no set of simulation vectors Remember that no set of simulation vectors

can provide 100% verification of the can provide 100% verification of the conversion.conversion.

Static Timing Analysis and Formal Static Timing Analysis and Formal Verification techniques should be used Verification techniques should be used wherever possible.wherever possible.