ISSN 2322-0929 Vol.02, Issue.09, November-2014, Pages:0933-0936 www.ijvdcs.org Copyright @ 2014 IJVDCS. All rights reserved. An Implementation of Assertion Based Verification (ABV) Algorithm for DDR Memory Cores KORUKONDA SAILESH 1 , S.Ranjitha 2 1 PG Scholar, Dept of ECE (VLSI), Institute of Aeronautical Engineering, Hyderabad, Telangana, India, Email: [email protected]. 2 Asst Prof, Dept of ECE, Institute of Aeronautical Engineering, Hyderabad, Telangana, India, Email: [email protected]. Abstract: In this paper, we present an Assertion based functional verification methodology for DDR type memory cores. The methodology is based on formulating DDR pattern properties extracted from JDEC standard which are then translated to synthesizable DDR Type SVA Protocol checkers for HW Emulation Platforms. The protocol checker verifies the validity of command sequences, command Timing, Mode Registers settings, and Initialization sequence when a DDR Type Memory controller is connected to a DDR Memory Core. The checker records command sequences using SVA coverage semantics during run time. The viability and potential of the approach is demonstrated by a case study using LPDDR3 Memory Protocol. Keywords: Memory Protocols, ABV, Functional Verification, DDR3. I. INTRODUCTION Assertion-based verification (ABV) is a methodology in which designers use assertions to capture specific design intent either through simulation, formal verification, or emulation of these assertions, verify that the design correctly implements that intent. Assertion Based Verification (ABV) is a technique that aims to speed one of the most rapidly expanding parts of the design flow. It can also be used in simulation, emulation and silicon debug. Research has suggested that verification can take up 70% of the time and cost of a full design cycle and that, within that, functional verification can take up more than half of the verification time. A number of studies have concluded the use of ABV reduces functional verification dramatically compared with traditional methods. This technique also reduces 50% verification effort through the use of the same formally derived assertions during the unit, subsystem and system verification phases. A. Assertions One way of considering assertions is to say that they are active comments. Where design and verification engineers have historically inserted passive code into a design to describe the intent of what is being exercised at a particular point in RTL or test bench code, assertions are “executable specifications”. They describe either legal or illegal behavior that can be observed at the point of their insertion by tools, and then flagged as having passed or failed. In itself, this is an easy-to-grasp extension of how comments work (and indeed passive comments are still added to assertions to ease communication as to their purpose between various participants in a design project). They are well suited to control signals because they are inherently specific. Assertions are essentially produced in three forms. The design engineer will insert them in the main design file alongside the code to be verified. The verification engineer will insert them in the bind files used as part of the verification process. A third party – a standards group or a tools vendor – will provide a library of off-the-shelf assertions for common use-cases. There are then two types of assertion Concurrent assertions must always be satisfied by a design. Temporal assertions must be satisfied by the design under certain defined (often clock-based) conditions. These conditions can either contain an individual set or a sequence of sets. III. INTRODUCTION TO THE ARCHITECTURE OF AHB COMPLIANT SDRAM CONTROLLER The controller is expected to synchronize data transfer between the processor and memory. To achieve this, the controller has to accept the requests from the processor side and convert them to a form suitable to the memory and execute the requests. Since the processor is faster than the memory, it is illogical to make the processor wait till each command is executed for it to give the next command. So the controller has to have some kind of storage as given in figure above, so that it can buffer multiple requests from the AHB slave interface while the processor continues with other work. We used FIFO to store the Read/Write
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ISSN 2322-0929
Vol.02, Issue.09,
November-2014,
Pages:0933-0936
www.ijvdcs.org
Copyright @ 2014 IJVDCS. All rights reserved.
An Implementation of Assertion Based Verification (ABV) Algorithm for
DDR Memory Cores KORUKONDA SAILESH
1, S.Ranjitha
2
1PG Scholar, Dept of ECE (VLSI), Institute of Aeronautical Engineering, Hyderabad, Telangana, India,
Email: [email protected]. 2Asst Prof, Dept of ECE, Institute of Aeronautical Engineering, Hyderabad, Telangana, India,