An automatic tool flow for the combined implementation of multi-mode circuits Brahim Al Farisi, Karel Bruneel, João Cardoso, Dirk Stroobandt.

An automatic tool flow for the combinedimplementation of multi-mode circuits

Brahim Al Farisi, Karel Bruneel, João Cardoso, Dirk Stroobandt

Overview

2

• Multi-mode circuit• FPGA• Dynamic reconfiguration:• Modular dynamic reconfiguration (MDR)• Dynamic circuit specialization (DCS)

• Novel tool flow• Experiments and results• Conclusions • Future work

Multi-mode circuit

3

• Several circuits, called modes, that are used mutually exclusive in time

• Example: software defined radio• Goal: Area efficient implementation

through hardware resource sharing

FPGA

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FFLUT

0

1

1

0

1

0

0

1

01 0

0 0

10

1 0

0 1

00

0

0

0

1

0

1

1

1

0

Conventional FPGA tool flow

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• Input: textual description of functionality

SYNTHESIS

MAP

PLACE

HDL design

Configuration

ROUTE

LUT circuit

entity multiplexer isport( sel : in std_logic_vector(1 downto 0); in : in std_logic_vector(3 downto 0); out : out std_logic);end multiplexer;

architecture behavior of multiplexer isbegin out <= in(conv_integer(sel));end behavior;

Textual description: HDL design

6

in0

in1

in2

in3

sel0

sel1

out

Conventional FPGA tool flow

7

SYNTHESIS

MAP

• Input: Textual description of functionality• Internal representation: LUT circuit• Output: FPGA configuration

PLACE

HDL design

Configuration

ROUTE

LUT circuit

100101011100001111

Dynamic reconfiguration of FPGAs

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• Advantages:• Smaller area• Lower power usage• Increased speed

M1 M2 M3

• Goal: area reduction with reduced reconfiguration time

M1M2M3

• Disadvantage:• Reconfiguration

time

Dynamic reconfiguration of FPGAs

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M1 M2 M3

• 2 tool flows:• Modular Dynamic Reconfiguration (MDR)• Dynamic Circuit Specialization (DCS)

M1M2M3

Modular Dynamic Reconfiguration (MDR)

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Mode 1

SYNTHESIS

MAP

PLACE

Configuration 1

ROUTE

Mode 2

SYNTHESIS

MAP

PLACE

Configuration 2

ROUTE

MDR

• Different modes are implemented independently• Complete area is rewritten Results in long reconfiguration times

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Dynamic Circuit specialization

• Design with parameters: input signals that only change once a while

• Implement dependency on parameters using dynamic reconfiguration

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Dynamic circuit specialization

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• Input: annotated textual description of functionality

SYNTHESIS

Param. HDL

TMAP

TPLACE

Param. Conf.

TROUTE

Tunable circuit

entity multiplexer isport( --BEGIN PARAM sel : in std_logic_vector(1 downto 0); --END PARAM in : in std_logic_vector(3 downto 0); out : out std_logic);end multiplexer;

architecture behavior of multiplexer isbegin out <= in(conv_integer(sel));end behavior;

Parameterised HDL design

14

in0

in1

in2

in3

sel0

sel1

out

Dynamic circuit specialization

15

SYNTHESIS

• Input: Annotated textual description of functionality

• Internal representation: Tunable CircuitParam. HDL

TMAP

TPLACE

Param. Conf.

TROUTE

Tunable circuit

Tunable circuit

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Tunable look-up tableTunable connection

Dynamic circuit specialization

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• Input: Annotated textual description of functionality

• Internal representation: Tunable Circuit• Output: Parameterised configuration

Param. HDL

SYNTHESIS

TMAP

TPLACE

Param. Conf.

TROUTE

Tunable Circuit

1A01010111B00C1111

A = sel0 AND sel1

B = sel1 C = sel0 OR sel1

Dynamic Circuit Specialization

• Reduced reconfiguration time• Takes as input 1 parameterised design• How to implement several modes with DCS?

18

Goal of our research

• Develop tool flow for dynamic reconfiguration of multi-mode circuits

• Reduce reconfiguration time • Combined implementation of different modes: Utilize similarities Increase correlation between configurations of the different modes

19

Novel tool flow

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Mode 1

SYNTHESIS

MAP

Mode 2

SYNTHESIS

MAP

Param. Conf.

TROUTE

Merge

PLACE

Configuration 1

ROUTE

PLACE

Configuration 2

ROUTE

Generating a Tunable multi-mode circuit

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Combined placement: virtual 3D FPGA

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• Simultanous placement of different LUT circuits on FPGA• Extension of a simulated annaeling placer

Different cost functions

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• CFRT: estimation of reconfiguration time (= number of switches that need to

be rewritten in the routing)

• CFWL: estimation of total wire length Tunable circuit

Reconfiguration time optimization

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• Uses “edge matching” - previously proposed *

• Try to overlap connections of different modes

• Connections that overlap don’t require parameterised bits in the routing

*M. Rullmann and R. Merker, “Maximum edge matching for reconfigurablecomputing,” Parallel and Distributed Processing Symposium,International, vol. 0, p. 179, 2006.

Wire-length optimization

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• Cost function that estimates total wire length needed by TRoute to implement Tunable circuit

Experiments

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• Implemented novel tool flow in our JAVA version of VPR

• Regular expression matching hardware, constant coefficient FIR filters, and general MCNC benchmarks

• Circuits of 200-400 LBs• Only 2 modes considered• Comparison of MDR and DCS (this work)• Metrics:• Reconfiguration time• Wire length (of each mode separately)

Wire length

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Results

28

Results

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Conclusions

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• Using combined placement and DCS:• Around 5X speedup of reconfig. time• Limited increase in wire length

• Better to optimize for wire length during combined placement: this also reduces reconfiguration time!

Future work

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• Combining logic circuits instead of LUT circuits

• Take configuration frames into consideration

Questions?

An automatic tool flow for the combinedimplementation of multi-mode circuits