AN ATM SWITCH USING STARBURST PACKET SWITCH FABRIC Massoud Hadjiahmad A thesis submitted in conformity with the requirements for the degree of Master of Applied Science, Graduate Department of ElectricaI and Cornputer Engineering, in the University of Toronto @ Copyright by Massoud Hadjiahmad 1998
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AN ATM SWITCH USING
STARBURST PACKET SWITCH
FABRIC
Massoud Hadjiahmad
A thesis submitted in conformity with the requirements
for the degree of Master of Applied Science,
Graduate Department of ElectricaI and Cornputer Engineering, in the
University of Toronto
@ Copyright by Massoud Hadjiahmad 1998
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An ATM Switch Using Starburst Packet Switch Fabric
A thesis submitted in confomity with the requirements
for the degree of Master of Applied Science,
Graduate Department of Electrical and Cornputer Engineering, in the
University of Toronto, 1998
by
Massoud Hadjiahmad
ABSTRACT
In this thesis, we present the design and analysis of an ATM switch using the Starburst packet
switching architecture. The first part of the thesis provides an introduction to ATM network
concepts and specifications, Starburst packet switching lntegrated Circuit, and the board design
of the Starburçt cell switch fabric. This introduction provides an ovewiew on the intemal
structure, functional and design requirements of intemal modules, and the overall picture of an
ATM switch in the network.
The second part of the thesis presents aie design of the Il0 module and system controller
interface. This portion of the aiesis defines the interface between vanous bfocks of the switch,
design criteria, and design implementation. The implementations are in the form of state
diagrams, and schernatics. Furthemore, guidelines and pointers are provided to enable future
hardware and software irnplementation of the Starburst ATM switch.
It is a pleasure to acknowledge rnany people who have diredy or indirectly cantnbuted ta the
contents of this thesis. First and foremost, I would like to thank Professor A Leon-Garcia for his
guidance and support airough the course of my MASc. work, and for many helpfut discussions
that contributeci to the design of the proposed Starburst switch.
Thanks go to my thesis cornmittee, Professors A Leon-Garcia, P. Chow, A Banejea, and 1.
Katzela. Thanks go to Professors K Sharifi and S.K Chan for reading some of the early
manuscripts and their guidance. 1 am gratefuf to Mehran Shirazi for his guidance in software
implementation of the Starburst switch.
Finally, I would like to thank my famiiy fUr the support and encouragement
2.1 m o ~ u c n o ~ ....... .... .................................................................................................................... 19
....................................................................................................... 2 2 STAR SUR^^ CHIP ARC HI TE^ 2 0
............................................................................................................... 2.2.1 Starburst Packet Format 20
.............................................................................................................................. 3.1 m O D U C ï i û N 29
......................................................................................................................... Figure f : An A TM Nemork... -3
........................................................................................................................................ Figure 2: A TM Cell -4
............................................................................................... Figure 3: UNI and MVI Cell Header Fonnats -5
...................................................................................................... Figwe 4: Cell Deiineation State Diagram 9
Figure 5: An ATM Switch Architecture ......................................................................................................... I 2
Figwe 7: A Simple Starbwst Swt'tch ...................................................... ...... . 19
Figure 8: Stmbwst P mket Format ............................................................................................................... 21
. . . Figure 9: EOP Corn1 Btt T m t g ................................................................................................................ 22
............................................................ Figure 27: NTC-SBA Intetfoce Controller T r m i t S tae Diagrm 40
Figure 28: Starburst A w t e r Transmit State Diagram ................................................................................. 41
................................................................................................................... Figure 29: M e S ~ b t u s t Packet 42
FIFO and each bit of the tags are used as a byte for the outgoing Starburst packet Bits 3-7
of the second tag are not used, hence they are discarded (Figure 30). While in this state. the
bit wunter is increased at each dock cycie, The byte counter also increases every eight
dock cycles.
Figure 30: Valid S&rburst Packet Generation
Valid Payload: The payload of an active Starûurst packet is the incorning ATM ceII. This ceIl
is read from the SBA Rx FIFO and appended to the Stahurst packet header genemted based
' The active bit is set to logic '1 ' and the remaining bits are set to '0'.
42
on the routing tag provided by the NTC packet The vaIue of the byte counter is increased at
every dock cyde while the bit munter will hold a constant value.
3.3.4.3 SBA Transmit Operation
The transmit operation of the Starburst adapter is best described by the state diagram provided in
Figure 31. The state diagram provides only the transition condiions and the variable
assignments at the transition. However, an explanation of the operation of the circuit while it
remains in each state follows:
Hunt The operation of the transmit SBA starts in this state and retums to this state with
reset The arriva1 of the EOP control signal from the CSF causes a transition to the Check
Headerstate. The EOP signal indicates that the incoming data, concurrent with the EOP
signal, is the first bit of the incoming Starburst packet from the CSF.
f- /- r Hunt 4 7 (üyte-m53 Bit-ent=i)
(EO-13 (Byle-ait=O = ((Bi-cnt=i! aa T*DIW1') II (eir-~m7 aa ~ ~ r w 1 9 ) ) -
(~i-cnt c O i --ait a O) t ~ ( B ~ - a i t - - l & B ~ a i t = 2 & & T h W I ~ ~
(Bit-- cf 7 a @?te-Qit = 2)
i Check Pay load
I
, Dummy Header
f
Pa yload
Figure 37: Starburst Adapter Transmit State Diagram
Check Header In this state, the transmit SBA checks the active bit of the incorning Starburst
packet to ensure that the packet is active before transfem'ng the packet to the NTC. If the
Active bit is set, the inmming invalid packet is discarded and the transmit SBA goes to the
Hunf state. However, if the incoming packet is a valid packet, the transmit SBA generates the
NTC routing tags from the Starburst packet header and trançfers an NTC packet to the NTC
module (Figure 32). While in this state, the bit counter is increased every clock cycle and the
byte counter is increased every eight cycles.
Valid Payloact The payload of an active Starburst packet is the outgoing ATM cell. This cell
is appended to the routing tags, generated based on the incoming Starburst header from the
CSF, and written to the SBA Tx FIFO. The value of the byte counter is increased at every
dock cycle while the bit counter will hold a constant value,
Figure 32: M C packet Generation
Dummy Payload: The transmit SBA enters this state only if the SBA Tx FIFO is full and it is
not possible to write the correct data into aie FIFO. To prevent generating short NTC packets
( les than 55 bytes) this state will write dummy bytes to the Tx FIFO, when there is space
available. And retums to Hunf state when a complete NTC packet is wntten to the SBA Tx
FIFO. This will result in synchronous operation of the NTC and SBA with respect to ceII
timing. However, due to FlFO ovemn valid ATM cells will be lost The value of the byte
counter is increased at every clock cycle if the SBA Tx FlFO is not full, while the bit counter
will hold a constant value.
4. System Control Interface
4.1 Introduction
The System Control Interface Module (SCIM) is the last module that is required to enable the
implementation of the Starburst ATM switch. This module is responsible for initialkation,
registerdook up table updates, system management, and network interface. The SCIM design is
based on the 10M requirements and using an AMCC PCI bus controller (13, 141. It is possible to
design the SCIM interface using a microprocesso~ or other bus types. However, the use of the
PCI bus for this application was based on the fact that PCI bus c m operate at 33 MHz and higher.
The a b i l i to transfer networking and controt data over the system bus at hig h speeds (more than
the switch dock frequency of 19.44 MHz) is an advantage and a system design requirement It is
essential for any system to be able to transfer control information at the least at the same speed
as the user data, atthough the system control software may not need to access the registers and
networking information very of€en-
The SClM was not designed using direct connection to microprocessors. It is more feasible to
upgrade the externat PC (or any other system with 33 MHz, 32-bit PCI bus) than upgrade a
rnicroprocessor. A rnicroprocessor based design would require extemal mernones as the sue of
the design increases. Tbe future expansion in the switch size, look up table size, and functions
that will be supported by the CAC and SM blocks witl define the system hardware requirements.
This expandability requirement is more easity manageabte based on the industry trend if an
externat PCI-based PC is used. As we know, more powerful and cost effective PCs are and will
be available. Another advantage of the PCI based SCIM design is that it is possible to upgrade, if
Network Termination Conboller data book [il] explains various micmprocwor interfaces that cm directly connect to the NTC.
required, the 33 MHz, 32-bit PCI bus to 66 MHz with 32 or 64 bit data bus. It is, also, possible to
use extended addressing mode of the PCI bus to expand the switch size. The AMCC PCI
wntroller is used due to aie fact that at the time of SCIM design this was the most cost effective
solution availa ble.
This chapter will provide a detailed discussion of the Systern Controller Interface Module design,
Section 4-2 presents an overview of the SCIM design. A general introduction to AMCC PCI
controller is provided in Section 4.3, Memory rnap and ttie implemented software funcüons are
presented in Section 4.4, while the hardware design of the SCIM is discussed in Section 4.5
4.2 Design Overview
The System Contraller Interface Module consists of hardware and software components The
SCIM hardware architecture is show in Figure 33. The hardware implernentation design provides
the following through the target controller circuit
Read and write access to the NTC controüstatus registers,
Write access to the ATC look up table,
Read access to the ATC status register.
However, the master and intempt controller circuit can provide the hllowing functions:
DMA write access to the host memory for transfer of network statistics and
receive/transrnit extracted cells from the NTC,
DMA read access to the host rnemory for transfer of the NTC DMA Iink descriptors
and receiveftransmit cells to be inserted in the outgoing cell stream by the NTC,
Trançfer of NTC Intempts to the software intempt handler.
The software portion of the SCIM is required to integrate the network and system management
functions with the hardware functions to provide a seamless operation for the user. The following
are the functions the SClM software provides:
PCI controller configuration test,
Base address dewon from the PCI contmller configuration register,
Network Temination Controller DMA link descriptor initialization in the host,
Init iaf i ion of the ATC look up table,
Initiaiiiation of the NTC control register,
InitiaSiahion of the Intenupt handler routine,
Provide start comrrtand for the operation of the Starburst switch,
Provide a user interface to enable monitoring the switch operation.
IOM
Master & Intempt Controller
AMCC ?CI
Controller
Figure 33: SClM Hardware Structure
4.3 PCI Bus ControIIer
The AMCC PCI controller consists of the PCI bus and the peripheral bus interfaces. The PCI bus
interface performs PCI data transfer funchions between the application and the host software
based on the PCJ standards and specifications. lssuing commands on the PCI bus and hnsfer
of dab through the PCI bus is the function of the operating systern and neither SClM hardware
nor software is involved in exact implernentation of the PCI functions.
The peripheral bus interface is the portion that is of interest to this project. This interface provides
a PCI Master and a PCI Target interface to the peripheral device. The PCI master operationsg
(read and write) are performed via an interface called Add-on FI FOI0 controller. PCI Master read
. operation is performed using the following steps:
The address of the memory location that is to be accessed is written to the bus
master read address register in the PCI controller.
The size of the burst is written in the bus master read counter register.
The bus master read enable (AMREM') signal is asserted.
The data will be available when the FlFO empty signal (RDEMPTY) is deasserted.
PCI Master Write operation is perfomied in a similar manner, as follows:
The data is written to the PCI mntroller FIFO.
The addres of the rnemory location that is to be accessed is written to the bus
master write register of the PCI controller.
The burst size of the wnte operation is written to the bus master write counter
reg ister.
PCI Master and Target operations can not be performed concunently, Le. Me peripheral deviœ can be master if and only if it is not a target at any given time. 'O A tenn used by AMCC to define the PCI Master intehce. " Signal names that are mentioned here refer to the signal name in Figure 33.
The bus master write enable signal ( A M E N ) is asserted to complete the
transaction.
The PCI Controller Target interface is generally used to read statusldata registers and update the
control registers of the application device, The PCI target operations of the AMCC PCI controller
is performed through the Pass- th~ '~ controller. The PCI target read operation is performed as
follows:
r The target operation active signal (PTATM 'j) is asserted with read signal indication
(PM = '03.
The address of the memory address on the peripheral can be read from the Pas-thnr
address register by asserüng the read address signal (PTADR#). - When the data is ready to be transferred to the PCI controller, aie data is wrÏtten to
the Pass-thru data register and the data ready signal is asserted (P7RDY#).
The PCI target write operation is perfomied in a similar manner, as follows: - The target operation active signal (PTATM) is asserted with write signal indication
( P M = '7'). - The address of the memory address on the peripheral can be read from the Pas-thru
address register by asserüng the read address signal (PTADM). - When the target is ready to transfer the data from the PCI controller, the data is read
from the Pass-thru data register and written to the appropriate peripheral register and
the data ready signal is asserted (PTRDY#).
The AMCC PCI controller provides a set of incoming and outgoing mailbox registers. These
registers can be used to transfer wmmand and data to the peripheral device or the host These
'* A tenn used by AMCC to define the PCI Target interface. '' The active low signals are indicated using the '# ' in this document
register are used in the SClM design to transfer intermpts generated by the VU module to the host
intempt handler. The intemrpt request transfer is performed by writing to an outgoing rnailbo~'~.
The PCI controller generates an intempt to the host to indicate a read operation from the mailbox
is required. The operation is completed when the host reads the mailbox This PCI host read will
generate an intempt to the peripheral interface to indicate the cornpletion of the transaction.
4.4 Memory Map/Software Functions
Every PCI bus deviœ contains a set of configuration registers that can be read and configured by
the system BlOS at power up. These registers provide various information to the system to
ensure the plug and play capabilzties of the PCI bus devices. Sorne of the information that the
PCI configuration registers contain, and is of interest to this document, are as follows:
Mernory and If0 base address registers,
PCI cornmand and Status registers,
Vendor and Device Identification.
The Vendor and Device Identification registers are used to uniquely identify the PCI device
manufacturers and their products, The PCI command and Status registers are indicative of what
PCI functions the device is capable of. The most important register for implementation of the
memory mapping and soîtware functions is the Memory and 110 base address registers. The
Memory base address register is read by aie system BIOS at the power up. The default value of
this register indicates the arnount memory space that is required by the PCI device. The system
BlOS writes aie starting address of the required memory space back to this register. The default
mernory required by the AMCC PCI controller is 32 K bytes. This default memory allocation is
large enough to handle the present design of the Starburst switch. However, it is possible to
AMCC PCI controller defines incomingloutgoing maifbox from Me point of view of the peripheral device.
change the defauit values of the AMCC PCI controller via a serial PPROM provided with the
developers kit, as rnaybe required in the future.
The mernory mapping for this implementation of the SClM is based on the number of registers in
the NTC and ATC devices. Each NTC component contains 64 control and 64 status, word size'?
registers- Due to the ske of the Starburst switch (16 110 ports) the totat number of required
address spaces for the NTC registerç are 8 K bytesq6. As a result, the assigned mernory space is
divided into 4 blocks of 8 K bytes. Therefore, the SCIM hardware will require only 2 bits to
decode which memory block is k i n g accessed. Table 3 provides the necessary memory
rnapping information. The 17 higher order address bits represent a constant base address that is
assigned by the BlOS at the power up.
Table 3: SClM Memory Map
I
C
To reduce the complexity of the SCIM hardware design the lower two bits of al1 addresses are
ignored and should ahivays be assigned to logic '0'. This will, aiso, prevent any conflict between
l5 16 bit registers; Le. bit O of the address is ignored.
51
2AOOW 2COOW 2EOO\H
5 6 7
OAOOW OC00ü-i OEOOW
memory rnap addressing and PCI bus specificaüon for addreçs cycles? The A 8 4 2 address bits
of are used to refer to the appropriate registers inside each NTC component The remaining h o
mernory rnap blocks are not used in the present design of the SCIM.
(Al-AO) are not used t Figure 34: Starburst Switch Address Decoding Structure
The sofhAlare written for this design of the SCIM does not provide full functionality with respect to
Call Admission Control and System Management functions. The software for mis thesis design
only provides basic fundons required to communicate with the IOM and transfer the required
data to and from the IOM components. The CAC, SM, and interrupt service routines will have to
be written based on the device driver software that is provided by this thesis. However, it is
recommended that the modifications to the device driver software be irnplemented as neceççary.
This implementation assumes Me registers are 32 bits wide to simplify the design. l7 PCI requires the addres provided on the bus during the address cycle have the Iower two bits set to logic 'O', i.e. long word addressing must be used.
The basic operation of the SCIM device driver starts with performing a ?CI configuration test on
the PCI controller device. The Memory base address register is obtained from the PCI
configuration register. The mernory base address is appended to the memory rnapped addresses
to access the required registers in the Starburst switch (Figure 34). The Starburst switch driver
will setup the chained link descriptors for the NTC DMA controllers [If). The ATC look up table
and NTC controt registers initialkation is the next task that the software driver completes. The
intempt handler routine is started and the user interface program is invoked to provide the
system manager with the necessary information,
4.5 SCIM Hardware Design
The AMCC Matchmaker kit provides a set of daughter cards with the PCI controller card. These
daughter cards a n be used to implement the SCIM hardware on an FPGA or PLD device. The
transfer to the PCI controller. The description of aie above funcüons and the state diagrams are
provided in the following sections18. The state diagrams for the SCIM functions are presented
individually to provide a better understanding of the operation of the circuit However. the actual
implementation will need to combine these state diagrams to generate only one state machine
with &firent branches. Due to the fact that the PCI Target functions are not perfonned as often
as the Master readiwrite operations, the Target functions are given priority over Master
operations. It is possible to design a more complex arbiter to provide a different type of priority
scheme as required, in the future.
4.5.1 System Controller Master Read
The SClM master read (SCMR) function is used to implement the DMA controller read operation
of the NTC cornponents of the IOM ports. The SCIM-IOM interface signals are similar to the lntel
The signals names used in Figures 35-39 are the same as the signals in Figure 33.
53
16 bit microprocessor. The M e diagram in Figure 35 provides oniy aie transition conditions and
the variable assignments at the transition. An explanation of the operation of the circuit is given
beiow:
f ldle 4.
Figure 35: SCIM Master Read State Diagram
Idle: The operation of the SCMR function starts in this state and retums to this state with
reset The assertion of Pas-thru inactive (PTATN#='I ') and bus request (HOU)) frorn the
DMA controlier signals causes a transition to Wait Read state. At the transition, the hold
acknowledge ( H U A ) is asserted and SCIM target functions (TAKEN)'' are disabled.
Wait Read: This wait state is introduced to ensure that the M C DMA controller issues a read
wrnmand and provides aie address for the read command. The assertion of the read
command causes a transition to the Waif Data state while SCMR assigns appropriate values
to the PCI controller signais.
Wait Da&: The SCMR remains in this state until it receives the requested data from the PCt
controller via the Add-on FIFO interface of the AMCC chip set The deassertion of read FIFO
empty signal indicates that the data is available. The data is read from the PCI controller
FlFO More the SClM goes to the Send Data &te.
Send Data: The DMA is notified of the data availability by asserting the READY# signal. The
SClM master read state machine is capable of providing back to back reads. If the target
active signal is not asserted by the PCI controller, the SClM master read operation goes to
the Waif Read state to start another read cycle. However. if the PCI controller asserts the
PTATM signal, the SClM Target Controller is activated, In this case, if the DMA bus request
is still active. the bus clear (BCLR#) signal is asserted. The bus clear signal causes the NTC
DMA controller to stop transmission and wait for hold acknowledge before continuing to
transfer the remaining data.
4.5.2 System Conboller Master Write
The SCIM master write (SCMW) function is used to implement the DMA controller write operation
of the NTC cornponents of the IOM ports. The state diagram in Figure 36 provides only the
transition conditions and the variable assignments at the transition. An explanation of the
operation of the circuit is given below:
Idfe: The operation of the SCMW function starts in this state and returns to this state with
reset The assertion of Pass-thru inactive (PTATWJ1 ') and bus request (HOLD) from the
DMA controller signals causes a transition to Waif Wnte state. At the transition, the hold
acknowledge (HLDA) is asserted and SClM target functions (TAR-EN) are disabled.
Wait Write: This wait state is introduçed to ensure that the NTC DMA controller issues a wrïte
comrnand. The assertion of the write command causes a transition to the Lafch Data state
while assigning appropnate values to the PCI controller signals.
'9 This is an intemal signal that is used to enable or disable SCIM target operations.
55
Latch Data: The SCMW remains in this state b r only one dock cycle. The data is latched in
and held to ensure the data value does not change by the DMA controller before it is written
to the PCI controller FIFO.
Figure 36: SClM Master Write State Diagram
PCI Wnte: in this state, the SClM issues write FIFO cornrnand to the PCI controller to write
saved data to the PCI controller FIFO. The master write state machine asserts the data
ready signal to alert the DMA controller of completion of the transaction before moving to the
Send Data state.
Send Data: The S C W state machine is capable of providing back to back wrÏte operations.
If the target active signal is not asserted by the PCI controller, the master write state machine
goes to the Wait Wnte state to start another write cycle. However, if the PCI controller
asserts the PTATM signal, the SClM Target Controller is activateci. in this case, if the D M .
bus request is still active, the bus clear (BCLR#) signal is asserted. The bus clear signal
causes the NTC DMA controller to stop transmission and wait for hoId acknowledge before
continuing to transfer the remaining data.
4.5.3 System ConfmIIer Target Read
The SClM target fundons are different from the master operations in their neeâ to decode the
memory address for the requested access. The SClM Target Read (SCTR) fundion performs the
read function for the Starburst switch driver. The state diagram in Figure 37 provides oniy the
transition conditions and the variable assignments at the transition. An explanation of the
operation of the circuit is given below
ldle: The operation of the SCTR function startç in this state and retums to this state with
reset The assertion of Pas-thni active (PTATM) along with read request (PTWR='O') and
target enable will result in a transition to iatch Address state. At the transition, an address
read request (PTADR#) is issued to the PCI controller Pass-thni interface.
Latch Addmss: In this state, SCTR circuit decodes the address provided by the Pass-th ru
interface based on the SClM memory map (Table 3). The SCTR state machine can move to
Read NTC or Read ATC states depending on the address provided. ln either case, the Pass-
thru address read request is deasserted and the ASA2 address bits are latched and held.
Read NTC: The chip sel& and NTC read command is asserted while the saved address is
assigned to the IOM address lines,
Waif NTC: The SCTR sbte machine will remain in this state until it recenles the confirmation
of data availability (RDYOUT='l? at the output of the NTC module. The assertion of the
RDYOUT signal will result in the transition to the Write PCI state. The SCTR issues a write
wrnmand to the PCI controller while asserb'ng the data ready signal (PTRDY#) for the Pass-
thm interface.
Read AT%: The chip select and ATC read cornmand is asserted while the saved address is
assigned to the IOM address lines. The ATC modules do not require any address lines for
The chip select signals for both ATC and NTC modules are provided based on the combination of CS#, ICS[l:O], and BS[2:0] signals. This is due to the fact that there are 16 ATC and 16 NTC modules that needs to be accessed. The BS[2:O] signals distinguish bebeen eight IOM boards, while the ICS[l:O] signals select which of the four modules (2 ATC and 2 NTC) on each board is to be accesçed.
the read or write operation. This is due to the fact that the ATC modules are designed such
that it provides oniy one readable register.
(NTCADR-1') * (TEMP-A C= P C I O ( 8 ~ 8 PTADRAI '1')
Address
(MC-RD#- '0. & sw_A[s:a] - 7EMP-A 8 iCSI1:q - t2\H or Ni) & =Fol = (o-T) a cs#cr]'& 1
f
Wait NTC
* f Y
\ Write d
PCI
Figure 37:SCIM Target Read State Diagram
Wait ATC: The SCTR state machine will remain in this state for only one cycle. Based on the
timing specifications of the ATC, the data is available within one dock cycle. The transition to
the Write PCI state is cornpleted by isçuing a write command to the PCI controller while
asserting the data ready signal (PTRDY#) for the Pass-ttiru interface.
Write PCI: This is a wait state to ensure that the correct data is transferred to the PCI
controller. The SCTR will move to the idle state after this state al1 the signals will resurne
their default values.
58
4.5.4 System ContmIIer Target Write
The SClM Target Wnte (SCTW) function is difkrent for ATC and NTC modules due to the timing
requirements of each module. However, the SCTW perfom the write function for the SClM
software driver. The &te diagram for NTC and ATC target write operations are provided in
Figure 38 and Figure 39, respectively. These state diagrarns only provide the transition
conditions and the variable assignments at the transition. An explanation of the operation of the
NTC target write state machine is provided below
Idle: The operation of the SCTW function for the NTC module starts in this state and returns
to this *te with reset The assertion of Pas-thru active ( P T A W along with write request
( P M = ' ? ') and target enable will result in a transition to Latch Addms state. At the
transition, an address read request (PTADR#) is issued to the PCI controller Pass-thni
interface.
iatch Addfess: In this state, SCTW circuit decodes the address provided by the Pass-thru
interface based on the SClM rnemory map (Table 3). The SCTW remains in this state for
only one dock cycle and moves to the 1-Cycle Wait state, while the A&A2 address bits are
latched and held, the PCI read signal is asserted and the Pasthni address read request is
deasserted.
?-Cycle Wait= This wait cycle provides sufficient time to ensure that the PCI controller data is
available. The SCTW issues a write command to the NTC module by providing the chip
select, write enable, valid data and address.
Hold Daîa: The SCTW circuit will remain in this &te until it receives the confirmation of
wmmand completion (RDYOUT='I') at the output of the NTC module. The assertion of the
RDYOUT signal will result in the transition to the Wrote NTC state- The SCTW deasserts the
write enable signal while asserting the write command completion flag (PTRDY#) for the
Pass-thru interface. The register address is incremented to enable back to back writes to the
NTC reciisters.
l -Cycle Wait
Figure 38: SCIM Target Write to NTC State Diagram
Wrote W C : The SCTW state machine can move to either Hold Data or ldle state depending
on the value of the PTBURST# signal. If the burst write request signal is asserted, the target
write circuit asse& the W C write enable, new address, and data, while deasserting the write
completion fiag (PTRDY#) to the Pass-#ni interface. However, if the burst wnte Rag is
disabled, the SCNV will move to the idle state and al1 the signals will hold their default values.
The SCW state machine is different for the ATC modules due to different timing requirernents
and the manner in which the wnte transactions are treated. The ATC look up table entries are
m e n without requiring extemal address lines. The ATC module requires seven consecutive
write comrnands to update one of the look up table entries, Every write command increments an
intemal counter to generate the address for the following write command into the ATC Control
Word registers? After the final wrÏte is issued, the ATC will transfer the data in al1 the Contral
Word registers to the next available look up table entry and asseris a ready flag. The SCTW state
diagram for the ATC modules are provided in Figure 39. An explanation of the operation of the
ATC target Mite state machine is provided below
ldle: The operation of the SCTW function for ATC module starls in this state and retums to
this state with reset The assertion of Pass-thru active (PTATN#) along witfi write request
(PfWR='l? and target enable will result in a transition to Lafch Address state. At the
transition, an address read request (PTADR#) is issued to the PCI controller Pass-thni
interface.
Latch Address: In this state, SCTW circuit decodes the address provided by the Pass-thru
interface based on the SClM memory map (Table 3). The SCTW remains in this state until
the data request flag (DREQ) is asserted by the ATC. Riis will cause the transition to the 3-
Cycle Wait state, white the write counter is set to zero, the PCI read signal is asserted and the
Pasç-thru address read request is deasserted.
&Cycle Wait: This wait state provides sufficient ornep to ensure that the ATC is ready for a
new cycle of seven wnte cornmands- At the transition to the Hold Data state, the SCTW
issues a write comrnand to the ATC module by providing the chip select, write enable, and
valid data. The wnte counter is also incremented.
Hold Da&: The SCTW circuit will remain in this state for only one cycle and moves to the
Wmte ATC state. The SCTW deasserts the write enable and chip select signals white
asserthg the write command completion flag (PTRDY#) to the Pass-thru interface.
" Control Word register is a terni used in the ATC data book There is approxirnately a maximum delay of 100 ns frorn the rising edge of the DREQ signal to
the actual time that the AT% is ready to accept new data. With the assumption that the PCI clock is running at 33 MHz, three clock cycles is sufficient to ensure correct operation of the modules.
Figure 39: SClM Target Write to ATC State Diagram
Wrote ATC: The target write state machine can rnove to either Hold Data or ldle state
depending on the value of the PTBURST#, and write counter. If the burst write request signal
is asserted and the nurnber of writes is less #an seven, the target write circuit asserts the
ATC write enable, chip select, and data, while deasserthg the write completion fl ag
(PTRD Y#) to the Pass-thru interface. However, if the burst write flag is disa bled or the write
counter equals seven, the SCTW will move to the idle state and al1 the signals will hold their
expected values.
5. Conclusions
Based on the fact that ATM technology is s ü H evoiving, many of the standards developed up to
this point in time are not complete. This provides a challenge in design and irnplementation of an
ATM switch that would be cornpliant with standards and initiates a platform for design and
development of products that have practical implications. The initial goals of this project were to
understand vanous important design issues on developing a complete system that can implement
ATM switctiing and move forward with completing the Starburst project that had started a few
years ago. It has since been a long joumey, studying various articles and documents,
researching component availability and their functions, discussing ideas with friends and
wlleagues, and leaming vanous aspects of systern design requirernenis.
The Starburst ATM Swiich architecture ernerged from the these efforts. The challenge in
designing the switch system lay in meeting Starburst cell switch fabnc requirements and ATM
network specifications. Availability of products that can provide ATM Physical Layer functions,
look up table and routing tags, while perforrning seamless operation with other systern
wrnponents via predefined interfaces, was a major part of decision rnaking process in how
sophisticatéd and robust the Starburst ATM switch design can be. Many different modules
manufactured by various companies were studied and the feasibility of their utilkation on reducing
the complexity and cost of the switch design were considered.
Section 5.1 provides a brief summary of the contributions. Finalîy, some suggestions for future
research and development are presented in Section 5.2.
5.1 Contributions
In Chapter 1, ATM network concepts, Physical Layer specifications. an overview of a general
ATM switch architecture including required nehnrork Connection Admission Control and System
Management functions, and the Stahurst ATM Switch structure were presented. The
architecture and functionality of the output buffered, non-blocking Starburst packet switching IC
was introduced in Chapter 2-
Chapter 3 presented a cbmplete design of the Starburst Switch I f0 Modules that included an
overview of the IOM data path, functional description of the components, and design of the
Starburst Adapter circuit In Chapter 4, the design of the Systern Control Interface Module was
discussed. All the required SCIM hardware and software functions, including PCI controller
Interface Masterrïarget operations, and the Starburçt Switch Memory Mapping were described.
The circuit design of the SBA was simulated, synthesized and routed to ensure the functionality of
the module and the correcbiess of the implementation. The SCIM software functions were tested
by transferring data to and from the PCI controller device.
5.2 Future Directions
There are several directions in which this project w n proceed. This thesis only sets the ground
work for development and implementation of an ATM switch. However, the first step is to
implement the design provided. Without any doubt, improvements can be made to enable the
Starburst switch to become a more complete solution by writing the required SM and CAC
functions and modifying the hardware design as required to becorne more efficient. The Starburst
switch was designed to be modular and this rnodularity can be an advantage in having a robust
and expandable ATM switch- One of the known disadvantages to the design is the inability of the
switch to obtain statistical data from the CSF and to use aiis information to improve the
performance of the system. This inability is due to existing design of the Starburst CSF. It may
be possible to impiement a different design for the CSF that increases the size of Starburst
header and uses the extra bits for transfemng statistical information.
The purpose of this thesis is to provide a starting point for implernentation of an ATM switch. It is
hop& that this work can generate interest and encourage other researchers to innovate and
irnplernent new ideas.
Appendix A: Starburst Switch Schematics and Codes
The Starburst &ch design, as was presented in this thesis, is accompanied with a technical
report document [la that provides:
The schematics for Il0 Module Printed Circuit Board (PCB) design-
PCB layout guidelines for the iOM.
The PL0 equations for the chip select decoder for each IOM PCB.
Pin assignment for the back plane bus connection for the IOM, CSF, and Clock
generator PCB.
The VHDL code for the Starburst Adapter module of the IOM-
The C code for the sofhrvare functions of the SCIM.
This technical report can be obtained from Professor Alberto Leon-Garcia at the Communications
group of the Department of Elecnical and Cornputer Engineering at the University of Toronto.
The schematics of the 110 Module, VHDL code for the Starburst Adapter, and the C code for the
System Controller Interface Module software fundons can, also, be obtained from Professor
LeonGarcia if required.
References
IlW-T Recommendation 1.361, '&ISDN ATM Layer Specification", March 1993.