AN 894: Signal Tap Tutorial with Design Block Reuse...Tutorial with Design Block Reuse for Intel Cyclone 10 GX FPGA Development Board Document Version Intel Quartus Prime Version Changes

AN 894: Signal Tap Tutorial withDesign Block Reusefor Intel® Cyclone® 10 GX FPGA DevelopmentBoard

Updated for Intel® Quartus® Prime Design Suite: 19.3

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Contents

1. Introduction................................................................................................................... 31.1. Tutorial Software and Hardware...............................................................................41.2. Tutorial Files......................................................................................................... 41.3. Signal Tap with Core Partition Reuse.........................................................................51.4. Signal Tap with Root Partition Reuse.........................................................................6

2. Core Partition Reuse Debug—Developer..........................................................................92.1. Step 1: Creating a Core Partition............................................................................. 92.2. Step 2: Creating Partition Boundary Ports............................................................... 102.3. Step 3: Compiling and Checking Debug Nodes......................................................... 122.4. Step 4: Exporting the Core Partition and Creating the Black Box File...........................132.5. Step 5: Copying Files to Consumer Project.............................................................. 142.6. Step 6: Creating a Signal Tap File (Optional)............................................................142.7. Step 7: Programming the Device and Verifying the Hardware.....................................162.8. Step 8: Verifying Hardware with Signal Tap............................................................. 18

3. Core Partition Reuse Debug—Consumer........................................................................203.1. Step 1: Adding Files and Running Synthesis............................................................ 203.2. Step 2: Creating a Signal Tap File...........................................................................213.3. Step 3: Creating a Partition for blinking_led_top...................................................... 223.4. Step 4: Compiling the Design and Verifying Debug Nodes..........................................233.5. Step 5: Programming the Device and Verifying the Hardware.....................................243.6. Step 6: Verifying Hardware with Signal Tap............................................................. 24

4. Root Partition Reuse Debug—Developer........................................................................264.1. Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region............... 264.2. Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition........ 274.3. Step 3: Generating and Instantiating the SLD JTAG Bridge Host................................. 284.4. Step 4: Generating HDL Instance of Signal Tap ....................................................... 294.5. Step 5: Compiling Export Root Partition and Copying Files to Consumer Project............304.6. Step 6: Programming the Device and Verifying the Hardware.....................................314.7. Step 7: Generating a Signal Tap File for the Root Partition......................................... 314.8. Step 8: Verifying the Hardware with Signal Tap........................................................31

5. Root Partition Reuse Debug—Consumer........................................................................335.1. Step 1: Adding Files to Customer Project................................................................ 335.2. Step 2: Generating and Instantiating SLD JTAG Bridge Host in Reserved Core Partition..345.3. Step 3: Synthesizing, Creating Signal Tap File, and Compiling ................................... 345.4. Step 4: Programming the Device and Verifying the Hardware.....................................355.5. Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap...................355.6. Step 6: Verifying Hardware of Root Partition with Signal Tap...................................... 37

6. Document Revision History for AN 894: Signal Tap Tutorial with Design BlockReuse for Intel Cyclone 10 GX FPGA Development Board........................................ 38

Contents

AN 894: Signal Tap Tutorial with Design Block Reuse: for Intel Cyclone 10 GXFPGA Development Board

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1. IntroductionThe Intel® Quartus® Prime Pro Edition software supports verification of block-baseddesign flows with the Signal Tap logic analyzer. This tutorial demonstrates how toincorporate internal signal verification into design block reuse flows in the IntelQuartus Prime Pro Edition software.

A design block is the logic comprising a hierarchical design instance. Block-baseddesign flows enable preservation of blocks within a project via Incremental Block-Based Compilation, as well as reuse of design blocks in other projects via Design BlockReuse. To preserve or reuse a design block, you must designate the block as a designpartition.

Figure 1. Core Partition Reuse Example

Core Partition

Developer Design

Reused Core Partition

Consumer Design

Export CorePartition

Verifying a block-based design requires planning to ensure visibility of logic insidepartitions and communication with the Signal Tap logic analyzer. The preparation stepsdepend on whether you are reusing a core partition or a root partition.

For basic information about designing with reusable blocks, refer to the Intel QuartusPrime Pro Edition User Guide: Block-Based Design. For step-by-step instructions onreusing design blocks, refer to AN 839: Design Block Reuse Tutorial for Intel Arria® 10FPGA Development Board.

This tutorial uses a provided design example to walk through the steps required toperform Signal Tap debugging in reused design blocks.

Related Information

• Intel Quartus Prime Pro Edition User Guide: Block Based Design

• AN 839: Design Block Reuse Tutorial

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1.1. Tutorial Software and Hardware

Steps in this tutorial correspond with the following Intel software and hardware:

• Linux installation of Intel Quartus Prime Pro Edition software version 19.3, withIntel Cyclone® 10 GX device support.

• The Intel Cyclone 10 GX FPGA Development Kit.

You can adapt this tutorial for Windows and other software or hardwareconfigurations.

1.2. Tutorial Files

This tutorial includes the following design example organized into directories thatcorrespond with the flow (Core or Root partition reuse) and role (Developer orConsumer).

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/c10_pcie_devkit_design_block_reuse_stp_v193.zip

Figure 2. Tutorial Directory Structure

Core_Partition_Reuse

Completed

Consumer

Developer

Scripts

Consumer

Scripts

Developer

Root_Partition_Reuse

Completed

Consumer

Developer

Scripts

Consumer

Scripts

Developer

The Completed directories contain the final versions of all files required to completethat tutorial module. You can use the files in Completed directories to bypass tutorialsteps, or skip to the final step of the tutorial module. The Scripts directories containbash scripts and files to restore the single project.

• To restore all of the tutorial files to the original run the following from the projectdirectory:

./restoreall.sh

• To restore a single project, run the following from the Consumer or Developerdirectory:

Script/restore.sh

(1) This feature has some known limitations. Refer to Why I can't compile Intel Stratix 10partitions exported from another project with a different top level and Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder.cpp.

1. Introduction

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1.3. Signal Tap with Core Partition Reuse

To perform verification in a reusable core partition, in the Developer project, you mustidentify the signals of interest, and then make those signals visible to a Signal Taplogic analyzer instance. The Intel Quartus Prime software supports two methods ofmaking core partition signals visible for verification:

• Signal Tap HDL instance—In the Developer project, you create a Signal Tap HDLinstance in the reusable core partition and connect the signals of interest to thatinstance. The Compiler ensures top level visibility of Signal Tap instances insidepartitions. Since the root partition and the core partition have separate HDLinstances, the Signal Tap files are also separate.

The Consumer must generate one Signal Tap file for each HDL instance present inthe design.

• Partition boundary ports—In this method, the Developer directly assigns signalsas ports to the partition boundary. The top level partition contains an instance ofSignal Tap, and signals in the partition boundary connect to it. Assigning boundaryports simplifies the management of hierarchical blocks, by automatically creatingports and tunneling through layers of logic, without making RTL changes. Youcreate partition boundary ports through an Intel Quartus Prime Settings File(.qsf) assignment, or with the Assignment Editor.

The Developer must include the user created partition boundary ports in the blackbox file. This action allows the Consumer to tap these ports as pre-synthesis orpost-fit nodes.

Figure 3. Consumer Debug Setup with Reused Core Partition

Signal Tap HDL InstanceParent Partition

JTAGTAP

RTL

Reused Core PartitionJTAGHUB

Signal TapInstance

Partition Boundary PortsParent Partition

JTAGTAP

Reused Core PartitionJTAGHUB

Manual ConnectionAutomatic Connection

RTL

Partition Boundary Ports

Signal TapInstance

Signal TapInstance

The Consumer can add the Signal Tap logic analyzer to the parent partition with any ofthese methods:

• Signal Tap HDL instance

• Signal Tap GUI to tap pre-synthesis nodes

• Signal Tap GUI to tap post-fit nodes

1. Introduction

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In this core partition reuse tutorial, the Developer creates partition boundary portswith the Assignment Editor, and the Consumer adds pre-synthesis nodes to the parentpartition with the Signal Tap GUI. The following figure describes the Developer andConsumer flows:

Figure 4. Tutorial Design Flow for Core Partition Reuse

Add Boundary Portsthrough Assignment

Editor

Export Partition

Add New BoundaryPorts to Black Box

File

Developer Flow Consumer Flow

Add pre-synthesis nodes from parent and imported partition to boundary ports

Assign QDB filesto Partitions

Create SOF

Create Project

Add Source

Synthesis

Create Partitions

Fitter

Synthesis

Use Signal Tap GUI

Fitter

Synthesis

Synthesis

Create Project

Add Source

Create Partitions

1.4. Signal Tap with Root Partition Reuse

In a root partition reuse flow, the Developer extends the debug fabric into theReserved Core partition with a debug bridge. The debug bridge also allows debuggingof the reserved core partition in the Consumer project. The components of a debugbridge are:

• SLD JTAG Bridge Agent Intel FPGA IP: Instantiate in the higher-level partitionto connect to an SLD JTAG Bridge Host in the child partition.

• SLD JTAG Bridge Host Intel FPGA IP: Instantiate in the child partition toconnect to an SLD JTAG Bridge Agent in the higher-level partition.

With the bridge in place, the Developer adds the Signal Tap logic analyzer to the rootpartition with either of the following methods:


• Signal Tap GUI to tap pre-synthesis or post-fit nodes

The Intel Quartus Prime Pro Edition software supports multiple instances of bridgecomponents in partitions and their children. The Compiler assigns an index number todistinguish each instance. The bridge index for the root partition is always None. Youcan view the bridge index for child partitions in the synthesis report, under JTAGBridge Agent Instance Information.

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Each instance of the Signal Tap logic analyzer can only connect within the partitionthat the instance resides. Therefore, the root partition and reserved core partitionrequire separate Signal Tap files in this flow.

The Consumer must instantiate the SLD JTAG Bridge Host in the reserved corepartition, and add Signal Tap to the reserved core partition with either of the followingmethods:


• Signal Tap GUI to tap pre-synthesis or post-fit nodes

Figure 5. Debug Setup with Reused Root Partition

Root Partition

JTAGTAP

JTAGHUB

Manual Connection

Automatic Connection

RTL

Signal Tap

Reserved Core

JTAGHUB

Signal Tap

SLD

JTAG

Bridg

e Age

nt

SLD

JTAG

Bridg

e Hos

t

In this root partition reuse tutorial, the Developer adds an HDL instance of the SignalTap logic analyzer to debug the root partition, and adds bridge components to enabledebug of the reserved core partition. Then, in the Consumer project, the Consumeradds the SLD JTAG Bridge Host to enable debug of the reserved core partition, anduses the Signal Tap GUI to tap pre-synthesis nodes.

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Figure 6. Tutorial Design Flow for Root Partition Reuse

Export Partition

Add pre-synthesis nodes from Reserved Core

partition to boundary ports

Assign QDB filesto Partitions

Create SOF

Create Partitions

Fitter

Synthesis

Use Signal Tap GUI

Synthesis

Create Project

Add Source

Add HDL Instance

Add JTAG Bridge andassociated ports

Create STP file for HDL instance

in the QDB file

Synthesis

Create Project

Add Source

Fitter

Synthesis

Related Information

• Debugging Partial Reconfiguration Designs Using Signal Tap Logic AnalyzerIn Intel Quartus Prime Pro Edition User Guide: Debug Tools

• SLD JTAG Bridge Intel FPGA IPIn Intel Quartus Prime Pro Edition User Guide: Debug Tools

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2. Core Partition Reuse Debug—DeveloperProcess Description

In this tutorial module, the Developer assigns signals as ports to the partitionboundary using the Assignment Editor, and then exports the core partition to a .qdbfile. As a result, these user created boundary ports are available for debug as pre-synthesis nodes in the Consumer project, as a part of the reused .qdb file.

Completed Tutorial Files

In the c10_pcie_devkit_design_block_reuse_stp folder, theCore_Partition_Reuse/Completed/Developer/ directory contains thecompleted files for this tutorial module.

Tutorial Module Steps

This tutorial module includes the following steps:

• Step 1: Creating a Core Partition on page 9

• Step 2: Creating Partition Boundary Ports on page 10

• Step 3: Compiling and Checking Debug Nodes on page 12

• Step 4: Exporting the Core Partition and Creating the Black Box File on page 13

• Step 5: Copying Files to Consumer Project on page 14

• Step 6: Creating a Signal Tap File (Optional) on page 14

• Step 7: Programming the Device and Verifying the Hardware on page 16

• Step 8: Verifying Hardware with Signal Tap on page 18

2.1. Step 1: Creating a Core Partition

During this step, you open the project, run synthesis, and define a design partition forthe core logic.

1. In the Intel Quartus Prime Pro Edition software, click File ➤ Open Project, andopen the c10_pcie_devkit_design_block_reuse_stp/Core_Partition_Reuse/Developer/top.qpf project file.

2. On the Compilation Dashboard, click Analysis & Synthesis to synthesize thedesign. When synthesis is complete, the Compilation Dashboard displays a checkmark.

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Figure 7. Compilation Dashboard

3. In the Project Navigator, right-click the u_blinking_led_top instance in theHierarchy tab, and then click Design Partition ➤ Default. A design partitionicon appears next to each instance you assign.

Figure 8. Create Design Partition

Note: If the Design Partition Window is not visible on the GUI, clickAssignments ➤ Design Partitions Window.

2.2. Step 2: Creating Partition Boundary Ports

Follow these steps to create partition boundary ports to expose signals from theparent partition.

2. Core Partition Reuse Debug—Developer

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1. In the Intel Quartus Prime software, click Assignments ➤ Assignment Editor.

2. In the Assignment Editor, locate the <<new>> row at the bottom of the list.

3. Double-click the To column, and then click the Node Finder button.

Figure 9. Assignment Editor

4. In the Node Finder, type * in the Named field, set Filter to Signal Tap: pre-synthesis, and then click Search.

Figure 10. Node Finder Search

The Matching Nodes list shows signals that match the search criteria.

5. In the Matching Nodes list, expand u_blinking_led_top, and then expandu_counter.

6. Select count_int[0], count_int[1], count_int[2], and count_int[24], andclick > to move them to the Nodes Found list. Do not click OK.

7. In the Matching Nodes list, expand u_blinking_led_top, and select value.Click >.

Figure 11. Node Finder Copy Nodes

8. Click OK to close the Node Finder.

9. In the Assignment Editor window, for each of these nodes, populate informationfor rest of the columns.

For example, for node u_blinking_led_top|u_blinking_led|value, double-clickAssignment Name and select Create Partition Boundary Ports. Double-clickvalue to provide a port name db_value. Leave rest of the columns as default.


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Figure 12. Assignment Editor

10. Click File ➤ Save to save all changes.

11. Optionally, you can verify the following assignments in /Core_Partition_Reuse/Developer/top.qsf.

set_instance_assignment -name CREATE_PARTITION_BOUNDARY_PORTS db_count_1 \-to u_blinking_led_top|u_counter|count_int[1]set_instance_assignment -name CREATE_PARTITION_BOUNDARY_PORTS db_count_24 \-to u_blinking_led_top|u_counter|count_int[24]set_instance_assignment -name CREATE_PARTITION_BOUNDARY_PORTS db_count_2 \-to u_blinking_led_top|u_counter|count_int[2]set_instance_assignment -name CREATE_PARTITION_BOUNDARY_PORTS db_value \-to u_blinking_led_top|valueset_instance_assignment -name CREATE_PARTITION_BOUNDARY_PORTS db_count_0 \-to u_blinking_led_top|u_counter|count_int[0]

2.3. Step 3: Compiling and Checking Debug Nodes

1. Click Compile Design on the Compilation Dashboard.

Figure 13. Full Compilation in Compilation Dashboard

2. Open the compilation report by clicking Processing ➤ Compilation Report.

3. Under Table of Contents, find Synthesis ➤ In-System Debugging ➤ CreatePartition Boundary Ports.


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Figure 14. Create Partition Boundary Ports

2.4. Step 4: Exporting the Core Partition and Creating the Black BoxFile

After compilation, you export the core partition and create a supporting black box portdefinitions file. This tutorial reuses the final compilation snapshot.

1. Click Project ➤ Export Design Partition. Select blinking_led_top for thePartition name, and the final Snapshot for export.

2. Confirm blinking_led_top.qdb as the Partition Database File name, andthen click OK. The final blinking_led.qdb that you export preserves theplacement and routing information from the Developer project reused in theConsumer project.

3. To create the black box file, click File ➤ New, select SystemVerilog HDL Fileunder Design Files, and then click OK.


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A blank .sv file opens to allow you to enter the port definitions for the partitionyou export and the partition boundary ports created in Step 3: Compiling andChecking Debug Nodes on page 12.

4. Include any Verilog parameters or VHDL generics in the definition. The portdefinitions in the black box file must look just like the original, without the logicRTL.

module blinking_led_top( output [3:0] value, input clock, output db_count_0, output db_count_1, output db_count_2, output db_count_24, output db_value_0, output db_value_1, );

endmodule

5. Save the black box file as blinking_led_top_bb.sv. When saving this file, turnoff the option to Add file to current project.

2.5. Step 5: Copying Files to Consumer Project

After exporting the core partition and creating the black box file, copy the files to theConsumer project directory for subsequent use.

Copy the blinking_led_top.qdb and blinking_led_top_bb.sv files to theCore_Partition_Reuse/Consumer/ directory.

Note: The .sdc file does not influence the logic, placement, or routing of a finalized partitionin the Consumer project.

In the Core Partition Reuse Debug-Consumer tutorial module, the Consumerintegrates the blinking_led_top.qdb and blinking_led_top_bb.sv files intothe Consumer project.

Related Information

Step 1: Adding Files and Running Synthesis on page 20

2.6. Step 6: Creating a Signal Tap File (Optional)

In this step, you configure the Signal Tap logic analyzer, and then tap partitionboundary ports and pre-synthesis nodes from the parent partition to debug in theDeveloper project. Configuring the Signal Tap logic analyzer includes adding areference clock and specifying acquisition settings.

1. In the Intel Quartus Prime Pro Edition software, click Tools ➤ Signal Tap LogicAnalyzer.


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Figure 15. Signal Tap Logic Analyzer Window

2. In the Instance Manager, click auto_signaltap_0.

3. In the Setup tab, double-click to launch the Node Finder.


5. In the Matching Nodes list, expand u_blinking_led_top. Select db_value_0,db_value_1, db_value_0, and db_value_1.


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Figure 16. Node Finder Copy Nodes

6. In the Matching Nodes list, expand the u_blinking_led_top ➤ u_counter ➤count_int.

7. From the node list, select count_int[0], count_int[1], count_int[2], andcount_int[24], and insert the nodes by clicking >.

8. Click Insert, and then Close.

9. In the Signal Tap window, under Signal Configuration, click (…) next to theClock field.

10. In the Node Finder, search for *, and select the clock.

11. Click >, and then click OK to close.

12. Leave all other options as default under Signal Configuration.

13. Go to File ➤ Save and save the file as stp_core_partition_reuse.stp.A dialog box appears asking if you want to enable Signal Tap file for the project.

14. Click Yes, and close the file.


2.7. Step 7: Programming the Device and Verifying the Hardware

1. To open the Intel Quartus Prime Programmer, click Tools ➤ Programmer.

2. Connect the board cables:

• JTAG USB cable to board

• Power cable attached to board and power source

3. Turn on power to the board.

4. In the Intel Quartus Prime Programmer, click Hardware Setup.


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Figure 17. Hardware Setup

5. In the Hardware list, select USB-BlasterII, and then click Close. The devicechain appears.

Note: If the device chain does not appear, verify the board connections.

6. Click Auto-Detect. The device chain populates.

7. In the Found Devices list, select the device that matches your design and clickOK. For this tutorial, select the 10CX220YF device that matches the10CX220YF780 FPGA on the Intel Cyclone 10 GX Development Kit.

8. Right-click the 10CX220YF row in the file list, and then click Change File.

9. Browse to select the top.sof file from the appropriate tutorial/output_files/ directory.

10. Enable the Program/Configure option for the 10CX220YF row.

Figure 18. Program/Configure Option

11. Click Start. The progress bar reaches 100% when device configuration iscomplete. The device is now fully configured and in operation.

Figure 19. Programming Successful


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Note: If device configuration fails, make sure the device you select forconfiguration matches the device you specify during .sof file generation.

12. Verify the LEDs behavior.

After completing this tutorial module:

• LEDs D20-D21 map to the blinking_led_top core.

• LEDs D19-D22 map to the top-level (root) design.

The blinking_led_top core flashes LEDs in binary order, and the top-level designLEDs are On.

2.8. Step 8: Verifying Hardware with Signal Tap

1. In the Signal Tap window, click File ➤ Open, and openstp_core_partition_reuse.stp.

2. Ensure that the development kit is powered ON and connected to the machinefrom which you open the Signal Tap logic analyzer.

3. In the JTAG Chain Configuration tab, set up the JTAG connection to the boardby clicking Setup and then selecting the USB-BlasterII under Hardware.

The device populates automatically.

Figure 20. JTAG Scan Configuration

The Instance Manager window shows Ready to acquire.

Figure 21. Instance Manager

4. To set the trigger condition, select count_int[24], right-click the column underTrigger Conditions, and set to Falling Edge.


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Figure 22. Trigger Conditions

5. Run analysis by clicking Processing ➤ Run Analysis.When the analysis finishes, the Waveform tab shows the captured data.

Figure 23. Waveform after Signal Tap Analysis

• The count_int[25:24] register in u_blinking_led_top|u_counter|count_int[25:24] drives u_blinking_led_top|u_blinking_led|value[1:0].

• The partition boundary ports created for each bit of value[1:0] aredb_value_1 and db_value_0.

• The value of db_value_0 changes a cycle later after count_int[24] transitionsto 0. The count_int[2:0] shows the transitioning of the counter during thisprocess


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3. Core Partition Reuse Debug—ConsumerIn this tutorial, the Consumer receives a final core partition with boundary ports thatcorrespond to signals useful for debugging. The Consumer adds the black box file andassigns the .qdb in the Consumer project. Then, the Consumer debugs the parentand reused core partition with a Signal Tap HDL instance, tapping partition boundaryports as pre-synthesis nodes.

Because the exported .qdb includes compiled netlist information, the Consumerproject must target the same FPGA device part number, and use the same IntelQuartus Prime version as the Developer project.


The Core_Partition_Reuse/Completed/Consumer/ tutorial directory containsthe completed files for this tutorial module.



• Step 1: Adding Files and Running Synthesis on page 20

• Step 2: Creating a Signal Tap File on page 21

• Step 3: Creating a Partition for blinking_led_top on page 22

• Step 4: Compiling the Design and Verifying Debug Nodes on page 23


• Step 6: Verifying Hardware with Signal Tap on page 24

3.1. Step 1: Adding Files and Running Synthesis

Incorporate the black-box file to the Consumer project.

1. Open the /Core_Partition_Reuse/Consumer/top.qpf project file.

2. Click Project ➤ Add/Remove Files in Project.

3. On the Files pane, click the browse (...) button next to the File name field tolocate and select the /Core_Partition_Reuse/Consumer/blinking_led_top_bb.sv black box file.

4. Click Open, and then click OK.The file is now a source file in the project.


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Related Information

Step 5: Copying Files to Consumer Project on page 14

3.2. Step 2: Creating a Signal Tap File

Create a Signal Tap file that includes partition boundary ports from the reused corepartition.

1. Click Tools ➤ Signal Tap Logic Analyzer.

2. In the Signal Tap logic analyzer GUI, click auto_signaltap_0.



Figure 24. Node Finder Search

The Matching Nodes list shows signals that match the search criteria.

5. Add the boundary ports from the imported partition (db_*) fromu_blinking_led_top to the Nodes Found list.

The names must match what appears in the Developer project's report file.

Figure 25. Node Finder

3. Core Partition Reuse Debug—Consumer

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Note: If you add nodes other than the db_* nodes from the imported partition,the Compiler leaves them unconnected.

6. Add nodes count[2:0] from the root partition to the Nodes Found list, andclick Insert.

7. Configure the Signal Tap acquisition. Refer to Step 6: Creating a Signal Tap File(Optional) on page 14 for details.

Figure 26. Specifying the Clock Source

8. Click File ➤ Save, and save the file as stp_core_partition_reuse.stp.A dialog box appears asking if you want to enable Signal Tap file for the project.


Related Information

Step 6: Creating a Signal Tap File (Optional) on page 14

3.3. Step 3: Creating a Partition for blinking_led_top

Create a new partition and assign the .qdb file from the Developer project to thepartition.

1. In the Project Navigator, right-click the u_blinking_led_top instance in theHierarchy tab, and then click Design Partition ➤ Default. A design partitionicon appears next to each instance you assign.


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Figure 27. Create Design Partition


2. Double-click in the Partition Database File cell for the u_blinking_led_topinstance, and then click browse (...). Select the blinking_led_top.qdb filecopied from the Developer project.

Figure 28. qdb Assignment in Design Partitions Window

3. Click the partition name blinking_led_top to deselect the Partition DatabaseFile column. This action confirms the .qdb file assignment.

Related Information

Step 5: Copying Files to Consumer Project on page 14

3.4. Step 4: Compiling the Design and Verifying Debug Nodes

After creating Signal Tap files for the parent and blinking_led_top partitions, youare ready to run a full compilation of the design. Then, verify the debug nodesconnection.


2. In the Compilation Report, under Synthesis, view the In-System Debugging➤ Connections to In-System Debugging Instance “auto_signaltap_0” reportto verify the connection of the ports.

In the report, the Status column shows the connected debug ports.


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You can now verify the results of the Core Partition Reuse—Consumer tutorial moduleon the hardware.

1. Program the device, as Step 7: Programming the Device and Verifying theHardware on page 16 describes.

2. After programming is complete, verify the following:

• LEDs D21-D20 map to the blinking_led_top core

• LEDs D19-D22 map to the top-level (root) design

After configuring the FPGA, the blinking_led_top core flashes LEDs in binaryorder. The top-level design shows a shifting bit in green.

3.6. Step 6: Verifying Hardware with Signal Tap

1. In the Signal Tap window, click File ➤ Open, and openstp_core_partition_reuse.stp.


3. Set up the JTAG Chain Configuration, and ensure Instance Manager is Ready toacquire.

4. As trigger condition, select db_count_24, right click the column under TriggerConditions, and set to Falling Edge.


Figure 29. Captured Data in Waveform Tab


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• db_value_0 and db_count_24 signals behaves identically to the Developer flowtutorial.

• The db_value_0 changes as per db_count_24 a cycle later.

• The db_value_* and db_count_* are the partition boundary ports from theimported partition.

• db_count_0, db_count_1 and db_count_2 signals show the transition of thecounter inside the imported partition.

• The count[0], count[1], count[2] signals show the transition of anothercounter in the parent partition during this process.

Related Information

Step 8: Verifying Hardware with Signal Tap on page 18


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4. Root Partition Reuse Debug—DeveloperProcess Description

The Developer adds bridge components to enable debug of the reserved core partition,and adds a Signal Tap HDL instance to debug the root partition. Then, the Developercompiles and exports the root partition, including logic and periphery resources, andfinally, copies the root_partition .qdb and .sdc files to the Consumer project.


In the c10_pcie_devkit_design_block_reuse_stp folder, theRoot_Partition_Reuse/Completed/Developer/ directory contains thecompleted files for this tutorial module.

Steps


• Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region onpage 26

• Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partitionon page 27

• Step 3: Generating and Instantiating the SLD JTAG Bridge Host on page 28

• Step 4: Generating HDL Instance of Signal Tap on page 29

• Step 5: Compiling Export Root Partition and Copying Files to Consumer Project onpage 30


• Step 7: Generating a Signal Tap File for the Root Partition on page 31

• Step 8: Verifying the Hardware with Signal Tap on page 31

4.1. Step 1: Creating a Reserved Core Partition and Defining a LogicLock Region

1. c10_pcie_devkit_design_block_reuse_stp/Root_Partition_Reuse/Developer/top.qpf project file.


3. In the Project Navigator, right-click the u_blinking_led_top instance in theHierarchy tab, and then click Design Partition ➤ Reserved Core. A designpartition icon appears next to each instance you assign.

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Figure 30. Set Reserved Core Partition Type

4. Right-click the u_blinking_led_top instance in the Project Navigator, and clickLogic Lock Region ➤ Create New Logic Lock Region.

5. To modify the region properties, click Assignments ➤ Logic Lock RegionsWindow.

6. Change the Width to 123, and the Height to 61.

7. In the Origin column, specify X63_Y102.

8. Enable the Reserved and Core-Only options.

9. In the Size/State column, specify Fixed/Locked.

10. Click the Routing Region cell. The Logic Lock Routing Region Settings dialogbox appears.

11. Specify Fixed with expansion with Expansion Length of 0 for the RoutingType. The actual size and location are arbitrary for this tutorial. However, you canview and adjust the Logic Lock Region shape in the Chip Planner.

12. Click the <<new>> cell and then repeat steps 5 through 12 to create anempty_region with the following properties:

• Width of 103 and Height of 1.

• Origin of X20_Y20.

• Reserved and Core-Only are On.

• Size/State of Fixed/Locked.

• Routing Region is Unconstrained.

Figure 31. Logic Lock Regions Window

4.2. Step 2: Generating and Instantiating SLD JTAG Bridge Agent inthe Root Partition

1. From the IP Catalog (Tools ➤ IP Catalog), select and generate the SLD JTAGBridge Agent Intel FPGA IP. Set the name as debug_agent.

4. Root Partition Reuse Debug—Developer

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For details about generating the SLD JTAG Bridge Agent Intel FPGA IP, refer to theIntel Quartus Prime Pro Edition User Guide: Debug Tools.

2. Open the top.sv file, uncomment lines 56 to 65 and 74 to 79, and save the file.

This action instantiates the SLD JTAG Bridge Agent in the root partition.

Lines 56 to 65:

// wire tck, tms, tdi, vir tdi, ena, tdo; // debug_agent debug_agent_inst ( // .tck (tck), //output, width=1, connect_to_bridge_host .tck// .tms (tms), //output, width=1, .tms// .tdi (tdi), //output, width=1, .tdi// .vir_tdi (vir_tdi),//output, width=1, .vir_tdi// .ena (ena), //output, width=1, .ena// .tdo (tdo) // input, width=1, .tdo// );

Lines 74 to 79:

// .tck (tck), //input, width=1, connect_to_bridge_host .tck// .tms (tms), //input, width=1, .tms// .tdi (tdi), //input, width=1, .tdi// .vir_tdi (vir_tdi), //input, width=1, .vir_tdi// .ena (ena), //input, width=1, .ena// .tdo (tdo) //output, width=1, .tdo

Related Information

Instantiating the SLD JTAG Bridge AgentIn Intel Quartus Prime Pro Edition User Guide: Debug Tools

4.3. Step 3: Generating and Instantiating the SLD JTAG Bridge Host

1. From the IP Catalog (Tools ➤ IP Catalog), select and generate the SLD JTAGBridge Host Intel FPGA IP. Set the name as debug_host.

For details about generating the SLD JTAG Bridge Host Intel FPGA IP, refer to theIntel Quartus Prime Pro Edition User Guide: Debug Tools.

2. Open the blinking_led_top.sv file, uncomment the lines 25 to 30 and 41 to48, and save the file.

This action instantiates the SLD JTAG Bridge Host in the Reserved Core partition,connecting the debug fabric to the parent partition.

Lines 25 to 30:

// input wire tck (tck), // connect_to_bridge_host .tck// input wire tms (tms), // .tms// input wire tdi (tdi), // .tdi// input wire vir_tdi (vir_tdi), // .vir_tdi// input wire ena (ena), // .ena// output wire tdo (tdo) // .tdo

Lines 41 to 48:

// debug_host debug_host_inst ( // .tck (tck), //input, width=1, connect_to_bridge_host .tck// .tms (tms), //input, width=1, .tms// .tdi (tdi), //input, width=1, .tdi// .vir_tdi (vir_tdi), //input, width=1, .vir_tdi// .ena (ena), //input, width=1, .ena// .tdo () //output, width=1, .tdo// );


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https://www.intel.com/content/www/us/en/programmable/documentation/nfc1513989909783.html#clc1490637166752


Related Information

Instantiating the SLD JTAG Bridge HostIn Intel Quartus Prime Pro Edition User Guide: Debug Tools

4.4. Step 4: Generating HDL Instance of Signal Tap

1. From the IP Catalog (Tools ➤ IP Catalog), select and double-click the SignalTap Logic Analyzer Intel FPGA IP. Set the name as stp_root_partition.

2. In the IP Parameter Editor, change Data Input Port Width to 6 and TriggerInput Port Width to 6.

Figure 32. Signal Tap Logic Analyzer Intel FPGA IP Parameter Editor

3. Generate the IP.

4. In the top.sv file, uncomment lines 45 to 49, and save the file.

This action instantiates the HDL Signal Tap logic analyzer in the root partition.Lines 45 to 49:

// stp_root_partition stp_root_partition inst (// .acq_clk (clock),// input, width=1, acq_clk.clk// .acq_data_in \// ({top_LED, count[3:0]}),// input, width=4, tap.acq_data_in// .acq_trigger_in \// ({top_LED, count[3:0]})// input, width=4, tap.acq_trigger_in// );


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https://www.intel.com/content/www/us/en/programmable/documentation/nfc1513989909783.html#rmu1492825155793


4.5. Step 5: Compiling Export Root Partition and Copying Files toConsumer Project

When you export the root partition, you include all resources outside of the reservedcore partition. The logic inside the reserved core, including the SLD JTAG Bridge Host,are not exported.


2. To export the root partition to a .qdb file, click Project ➤ Export DesignPartition. Select root_partition for the Partition name, final for Snapshotand turn on Include entity-bound SDC files for the selected partition:

Figure 33. Export Design Partition

3. Copy the root_partition.qdb and top.sdc files to theRoot_Partition_Reuse/Consumer/ directory.

When you include entity bound .sdc files with the partition export, you need toonly copy the top-level .sdc file, which is not bound to an entity. The top-leveldesign uses constraints for analysis only, and does not drive any logic or routing.

When reusing the root partition, the Consumer integrates the root_partition.qdband top.sdc files into the Consumer project. The Consumer can also include aseparate .sdc file to constrain the logic that they use in the reserved core partition.

The Logic Lock (Standard) boundary is visible in the Chip Planner in the Consumerproject for reference only. The Consumer cannot modify this region.

Related Information

Step 1: Adding Files to Customer Project on page 33


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When you create and load the .sof, the blinking_led_top core does notilluminate any LEDs. The top-level design shows a shifting bit in green. Thebehavior of the periphery LED driver carries into the Consumer project via thefinal .qdb file.

4.7. Step 7: Generating a Signal Tap File for the Root Partition

1. Go to the shell from where you opened the Intel Quartus Prime software.

2. In the shell, go to directory a10_pcie_devkit_design_block_reuse_stp/Root_Partition_Reuse/Developer, and then run the following command:

quartus_stp top --create_signaltap_hdl_file --stp_file \stp_root_partition.stp

4.8. Step 8: Verifying the Hardware with Signal Tap

1. In the Signal Tap window, click File ➤ Open, and open thestp_root_partition.stp file, which you created in the previous step.



4. Verify that Bridge Index is set to None Detected in the JTAG ChainConfiguration window.

Figure 34. JTAG Chain Configuration

5. To set the trigger condition, select the count[0], count[1], count[2], andcount[3] signals, right-click the column under Trigger Conditions, and selectFalling Edge.


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7. Verify the transition of the nodes in the root partition.

Figure 36. Waveforms for Root Partition Nodes in Developer Project

In this tutorial design, the count[3:0] signals represent the counter in the rootpartition, and the top_LED signals represent the green LEDs on the board, which alsomap to the top-level (root) design. After the trigger activates, only one of the top_LEDbits is low, at any time.

If the root partition reuse succeeds, the Consumer project must present an identicalbehavior to the Developer project, since the Consumer imports the root partition .qdbfile from this Developer project.

Related Information



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5. Root Partition Reuse Debug—ConsumerProcess Description

The root partition Consumer receives from the Developer the final top-level, placed,and routed root partition, and optionally a .sdc file. Then, the Consumer enables thereserved core partition for debug by instantiating the SLD JTAG Bridge Host, whichcommunicates with the SLD JTAG Bridge Agent instantiated in the root partition.Finally, the Consumer taps pre-synthesis nodes in the Signal Tap GUI to debug thereserved core partition.


The Root_Partition_Reuse/Completed/Consumer/ tutorial directory containsthe completed files for this tutorial module.



• Step 1: Adding Files to Customer Project on page 33

• Step 2: Generating and Instantiating SLD JTAG Bridge Host in Reserved CorePartition on page 34

• Step 3: Synthesizing, Creating Signal Tap File, and Compiling on page 34


• Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap on page35

• Step 6: Verifying Hardware of Root Partition with Signal Tap on page 37

5.1. Step 1: Adding Files to Customer Project

You import the timing constraints and the root partition database from the Developerproject.

1. c10_pcie_devkit_design_block_reuse_stp/Root_Partition_Reuse/Consumer/top.qpf project file.

2. Click Project ➤ Add/Remove Files in Project.

3. On the Files pane, click the browse (...) button next to the File name field tolocate and select the top.sdc file, and click Add.

4. Click Apply, and then click OK.

5. If the Design Partitions Window is not visible, click Assignments ➤ DesignPartitions Window.

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6. In the Design Partitions Window, locate the root partition row, double-clickthe Partition Database File field, and then click browse (...).

7. Select the root_partition.qdb file copied over from the Developer project.

8. Click the partition name to confirm the .qdb assignment.

Related Information

Step 5: Compiling Export Root Partition and Copying Files to Consumer Project onpage 30

5.2. Step 2: Generating and Instantiating SLD JTAG Bridge Host inReserved Core Partition

Exporting the root partition in the Developer project does not include logic inside thereserved core or the SLD JTAG Bridge Host. The Consumer must add the SLD JTAGBridge Host to the reserved core in the Consumer project.

1. From the IP Catalog (Tools ➤ IP Catalog), select and generate the SLD JTAGBridge Host Intel FPGA IP. Set the name as debug_host.

2. Open the blinking_led_top.sv file, uncomment lines 26 to 31 and 48 to 55,and save the file.

Related Information

Step 3: Generating and Instantiating the SLD JTAG Bridge Host on page 28

5.3. Step 3: Synthesizing, Creating Signal Tap File, and Compiling


2. In the Project Navigator, right-click the u_blinking_led_top instance in theHierarchy tab, and then click Design Partition ➤ Default.

Important: root_partition.qdb contains the information aboutu_blinking_led_top from Developer project. It is not necessary toset the partition type to Reserved Core and create the Logic LockRegion for it.

3. In the Intel Quartus Prime Pro Edition software, click Tools ➤ Signal Tap LogicAnalyzer.

4. In the Instance Manager, click auto_signaltap_0.



7. In the Matching Nodes list, expand the u_blinking_led_top|count.

8. Select count[0], count[1], count[2], and count[24]. Insert the nodes byclicking >.

9. Select value_top under u_blinking_led_top. Click >, then click Insert, andthen click Close.

5. Root Partition Reuse Debug—Consumer

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10. In the Signal Tap window, under Signal Configuration, click (…) next to theClock field.

11. In the Node Finder, search for *, and select the clock node in the reserved corepartition u_blinking_led_top. Click >, and then click OK to close.

12. Leave all the other options as default under Signal Configuration. Go to File ➤Save and save the file as stp_periphery_reuse_core.stp.A dialog box appears asking if you want to enable Signal Tap file for the project.








After configuring the FPGA, the blinking_led_top core flashes LEDs in a binarycounting order. The top-level design shows a single bit shifting in green.

5.5. Step 5: Verifying the Hardware of Reserved Core Partition withSignal Tap

To use Signal Tap GUI for the reserved core:

1. Determine the bridge index according to the number in the synthesis report file(Root_Partition_Reuse/Developer/output_files/top.syn.rpt), underJTAG Bridge Agent Instance Information in the Developer project.

Figure 37. Synthesis Report

2. In the Signal Tap window, click File ➤ Open, and openstp_periphery_reuse_core.stp.



5. Set the Bridge Index as found in the synthesis report(Root_Partition_Reuse/Developer/output_files/top.syn.rpt in theDeveloper Project

If the values for Bridge Index are different, Signal Tap reports Instance notfound.


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Figure 38. Setting the Bridge Index

6. To set the trigger condition, select count[24], right click the column underTrigger Conditions and select Falling Edge.



8. Verify the transition of reserved core nodes in Signal Tap GUI. The expectedbehavior is:

— value_top[0] transitions along with count[24].

— count[0], count[1], and count[2] show the transition of other counterbits in the reserved core partition during this process.


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Figure 40. Waveforms for reserved core Partition Nodes in Consumer Project

Related Information


5.6. Step 6: Verifying Hardware of Root Partition with Signal Tap

1. Go to the shell from where you opened the Intel Quartus Prime software.

2. In the shell, go to directory c10_pcie_devkit_design_block_reuse_stp/Root_Partition_Reuse/Consumer, and then run the following command:

quartus_stp top --create_signaltap_hdl_file --stp_file \stp_root_partition.stp

3. In the Signal Tap window, click File ➤ Open, and open thestp_root_partition.stp file, which you created in the previous step.


5. Verify that Bridge Index is set to None in the JTAG Chain Configurationwindow

6. To set the trigger condition, select the count[0], count[1], count[2], andcount[3] signals, right-click the column under Trigger Conditions, and selectFalling Edge.


8. Verify the transition of the nodes in the root partition.

Figure 41. Waveforms for Root Partition Nodes in Consumer Project

In this tutorial design, the count[3:0] signals represent the counter in the rootpartition, and the top_LED signals represent the green LEDs on the board, which alsomap to the top-level (root) design. After the trigger activates, only one of the top_LEDbits is low, at any time.

If the implementation succeeds, the Consumer project behaves identically to theDeveloper project.


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6. Document Revision History for AN 894: Signal TapTutorial with Design Block Reuse for Intel Cyclone 10 GXFPGA Development Board

Document Version Intel QuartusPrime Version

Changes

2019.11.11 19.3 Initial release of document.

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AN 894: Signal Tap Tutorial with Design Block Reuse...Tutorial with Design Block Reuse for Intel Cyclone 10 GX FPGA Development Board Document Version Intel Quartus Prime Version Changes

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