December 2010 Altera Corporation AN-611-1.0 Application Note Subscribe © 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 101 Innovation Drive San Jose, CA 95134 www.altera.com Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design This reference design describes how to map a 3-gigabit-per-second serial digital interface (3G-SDI) Level B and a dual link high-definition serial digital interface (HD-SDI) using the Altera ® SDI MegaCore ® function and the Audio Video Development Kit, Stratix ® IV GX Edition. The Audio Video Development Kit, Stratix IV GX Edition, consists of the Stratix IV GX development board and two SDI high-speed mezzanine cards (HSMC). The dual link HD-SDI consists of two SMPTE 292M HD-SDI operating at a nominal rate of 2.970 GB per second or 2.967 GB per second. This application note describes the following two demonstrations: ■ Mapping of 3G-SDI level B to dual link HD-SDI (receiver) ■ Mapping of dual link HD-SDI to 3G-SDI level B (receiver) f For more information about the Stratix IV GX audio and video development kit, refer to the Audio Video Development Kit, Stratix IV GX Edition User Guide. For more information about the Stratix IV GX FPGA development board, refer to the Stratix IV GX FPGA Development Board Reference Manual; for more information about the SDI HSMC, refer to the SDI HSMC Reference Manual or AN 600: Serial Digital Interface Reference Design for Stratix IV Devices. For more information about the SDI MegaCore function, refer to the SDI MegaCore Function User Guide or contact your Altera representative. Functional Description The reference design provides a general platform to perform signal mapping from 3G-SDI Level B signal to two HD-SDI signals and vice versa. Figure 1 on page 2 and Figure 2 on page 3 show two high-level block diagrams of the reference design.
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December 2010 Altera Corporation
AN-611-1.0
© 2010 Altera Corporation. All QUARTUS and STRATIX are RAll other trademarks and servicwww.altera.com/common/legaaccordance with Altera’s standawithout notice. Altera assumes service described herein except version of device specifications
101 Innovation DriveSan Jose, CA 95134www.altera.com
Mapping 3G-SDI Level B and Dual LinkHD-SDI (SMPTE372) Reference Design
Application Note
This reference design describes how to map a 3-gigabit-per-second serial digital interface (3G-SDI) Level B and a dual link high-definition serial digital interface (HD-SDI) using the Altera® SDI MegaCore® function and the Audio Video Development Kit, Stratix® IV GX Edition. The Audio Video Development Kit, Stratix IV GX Edition, consists of the Stratix IV GX development board and two SDI high-speed mezzanine cards (HSMC). The dual link HD-SDI consists of two SMPTE 292M HD-SDI operating at a nominal rate of 2.970 GB per second or 2.967 GB per second.
This application note describes the following two demonstrations:
■ Mapping of 3G-SDI level B to dual link HD-SDI (receiver)
■ Mapping of dual link HD-SDI to 3G-SDI level B (receiver)
f For more information about the Stratix IV GX audio and video development kit, refer to the Audio Video Development Kit, Stratix IV GX Edition User Guide. For more information about the Stratix IV GX FPGA development board, refer to the Stratix IV GX FPGA Development Board Reference Manual; for more information about the SDI HSMC, refer to the SDI HSMC Reference Manual or AN 600: Serial Digital Interface Reference Design for Stratix IV Devices. For more information about the SDI MegaCore function, refer to the SDI MegaCore Function User Guide or contact your Altera representative.
Functional DescriptionThe reference design provides a general platform to perform signal mapping from 3G-SDI Level B signal to two HD-SDI signals and vice versa. Figure 1 on page 2 and Figure 2 on page 3 show two high-level block diagrams of the reference design.
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rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, eg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. e marks are the property of their respective holders as described at l.html. Altera warrants performance of its semiconductor products to current specifications in rd warranty, but reserves the right to make changes to any products and services at any time no responsibility or liability arising out of the application or use of any information, product, or as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest before relying on any published information and before placing orders for products or services.
Page 2 Functional Description
Mapping of 3G-SDI Level B to Dual Link HD-SDIThe following sections describe the various elements used in the mapping of the 3G-SDI level B to dual link HD-SDI as shown in Figure 1.
.
3G-SDI ReceiverThe triple-standard SDI receiver MegaCore function provides a 3G-SDI level B receiver interface.
Dual Link HD-SDI Transmitter
The dual link HD-SDI transmitter MegaCore function outputs two links of 1.485-Gbps 1080i data stream.
Demux
The demultiplexer logic receives the input from the internal pattern generator or the 3G-SDI signal from the triple-standard receiver, and then demultiplexes the 3G-SDI signal to two HD link data stream. The DIPSW6 on the development kit selects either the HD link A or HD link B option.
Pattern Generator
The pattern generator outputs a test pattern.
FIFO
The FIFO stores the parallel video data. When the FIFO buffer is half full, the transmitter starts to read, encode, and transmit the data.
Figure 1. Block Diagram—Mapping of 3G-SDI Level B to Dual Link HD-SDI
Internal Test Pattern Generator
3G-SDI MegaCore Function(Receiver)
Transceiver SDI Protocol Blocks
SDI Protocol Blocks
Transceiver
Transceiver
Demux
Starting Channel Number = 0
3G-SDI Level B signal
DIPSW6
20
20
20
20HD Link A
HD Link B
20
Dual link HD-SDI MegaCore Function(Transmitter)
HD-SDI Link A signal
HD-SDI Link B signal
Starting Channel Number = 8, 12
hsmc_sdi_portA
FIFO
Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design December 2010 Altera Corporation
Functional Description Page 3
Mapping of Dual Link HD-SDI to 3G-SDI Level B The following sections describe the various elements used to map the dual link HD-SDI to the 3G-SDI level B as shown in Figure 2.
.
Dual link HD-SDI ReceiverThe dual link HD-SDI receiver MegaCore function provides a dual link HD-SDI receiver interface. The dual link HD-SDI timing difference between link A and link B at the source must not exceed 40 ns (specification of SMPTE372). You must assert rst_rx when both link A and link B are ready to receive data for the first time.
Triple-Standard SDI Transmitter
The triple-standard SDI MegaCore function transmitter, inst2, is used to transmit HD signal. The DIPSW5 on the development kit is used to transmit HD Link A data stream or HD Link B data stream.
The triple-standard SDI MegaCore function transmitter, inst3, is used to transmit 3Gb signal. The DIPSW6 on the development kit is used to transmit 3Gb signal generated from the internal pattern generator or the 3Gb signal multiplexor from two receiver HD signal.
FIFO
The FIFO stores the parallel video data. When the FIFO buffer is half full, the transmitter starts to read, encode, and transmit the data.
Mux (Serial Interleave Streaming)
The multiplexer logic receives the input from two dual link HD-SDI data and streams the input into the interleaved 3G-SDI level B data.
Figure 2. Block Diagram—Mapping of Dual Link HD-SDI to 3G-SDI Level B
Dual link HD-SDI MegaCore Function(Receiver)
Transceiver
SDI Protocol Blocks
FIFO
Mux
SDI Protocol Blocks Transceiver
Transceiver FIFO
SDI Protocol Blocks
Transceiver
20
20
20
20
20
20
Starting Channel Number = 8,12
HD-dual link signal
HD-dual link signal
hsmc_sdi_portB
Triple standard SDI MegaCore Function(Transmitter)
Starting Channel Number = 0
Starting Channel Number = 4
3G-SDI signal
HD-SDI signal (link A or link B)
DIPSW5
Triple standard SDI MegaCore Function(Transmitter)
FIFO
Internal Pattern Generator
DIPSW7
December 2010 Altera Corporation Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design
Page 4 Functional Description
Data ConversionsFigure 3 and Figure 4 show the conversion of 3G-SDI Level B data to 2 HD-SDI data streams and vice versa.
.
.
Figure 3. Conversion of 3G-SDI Level B Data to 2 HD-SDI Data Streams
Figure 4. Conversion of 2 HD-SDI Data Streams to 3G-SDI Level B Data
3FFh
(C2)
Demux
3FFh
(C1)
3FFh
(Y2)
3FFh
(Y1)
000h
(C2)
000h
(C1)
000h
(Y2)
000h
(Y1)
XYZ(
C2)
XYZ(
C1)
XYZ(
Y2)
XYZ(
Y1)
LN0(
C2)
LN0(
C1)
LN0(
Y2)
LN0(
Y1)
LN1(
C2)
LN1(
C1)
LN1(
Y2)
LN1(
Y1)
3FFh
(C1)
3FFh
(Y1)
000h
(C1)
000h
(Y1)
XYZ(
C1)
XYZ(
Y1)
LN0(
C1)
LN0(
Y1)
LN1(
C1)
LN1(
Y1)
3FFh
(C2)
3FFh
(Y2)
000h
(C2)
000h
(Y2)
XYZ(
C2)
XYZ(
Y2)
LN0(
C2)
LN0(
Y2)
LN1(
C2)
LN1(
Y2)
000h
(C1)
000h
(Y1)
000h
(C2)
000h
(Y2)
3G-SDI Level B Interleaved Stream
Data Stream 1
Data Stream 2
3FFh
(C1)
3FFh
(Y1)
000h
(C1)
000h
(Y1)
XYZ(
C1)
XYZ(
Y1)
LN0(
C1)
LN0(
Y1)
LN1(
C1)
LN1(
Y1)
3FFh
(C2)
3FFh
(Y2)
000h
(C2)
000h
(Y2)
XYZ(
C2)
XYZ(
Y2)
LN0(
C2)
LN0(
Y2)
LN1(
C2)
LN1(
Y2)
000h
(C1)
000h
(Y1)
000h
(C2)
000h
(Y2)
MultiplexingData Stream 1
Data Stream 2
3G-SDI Level B Interleaved Stream
3FFh
(C2)
3FFh
(C1)
3FFh
(Y2)
3FFh
(Y1)
000h
(C2)
000h
(C1)
000h
(Y2)
000h
(Y1)
XYZ(
C2)
XYZ(
C1)
XYZ(
Y2)
XYZ(
Y1)
LN0(
C2)
LN0(
C1)
LN0(
Y2)
LN0(
Y1)
LN1(
C2)
LN1(
C1)
LN1(
Y2)
LN1(
Y1)
Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design December 2010 Altera Corporation
Functional Description Page 5
Figure 5 shows the timing diagrams of the data conversions from 3G-SDI Level B to 2 HD-SDI data streams and vice versa.
.
Figure 5. Data Conversions from 3G-SDI Level B Data to 2 HD-SDI Data Streams and Vice Versa
tx_pclktx_trs
txdata[19:10]txdata[9:0]
tx_data_type_a_bn
3FF(Y) 000(Y) XYZ(Y)000(Y)
3FF(C) 000(C) XYZ(C)000(C)
tx_pclktx_trs
txdata[19:10]txdata[9:0]
tx_data_type_a_bn
3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(Y)XYZ(C)
3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(Y)XYZ(C)
tx_pclktx_trs
txdata[19:10]txdata[9:0]
tx_data_type_a_bn
3FF(Y) 000(Y) XYZ(Y)000(Y)
3FF(C) 000(C) XYZ(C)000(C)
74.25MHzHD Link A
HD Link B74.25MHz
148.5MHz
3G Level B
HD Link B
HD Link A
Dat
a co
nver
sion
Dat
a co
nver
sion
y1 y1
Cb1 Cr1
y1
y2
Cb1
Cb2
Cr1
Cr2
y1
y2
y2 y2
Cb2 Cr2
December 2010 Altera Corporation Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design
Page 6 Getting Started
Getting StartedThis section discusses the requirements and related procedures to demonstrate the reference design with the Stratix IV GX development board. This section contains the following topics:
■ Hardware and Software Requirements
■ Setting Up the Hardware
■ Running the Reference Design
Hardware and Software RequirementsThe reference design requires the following hardware and software:
■ Stratix IV GX development board
■ Two SDI HSMC
■ SDI MegaCore function
■ Quartus® II software, version 10.0 sp1 patch 1.181
To obtain the Audio Video Development Kit, Stratix IV GX Edition, contact your local Altera representative.
Setting Up the HardwareFigure 6 shows how the Stratix IV GX development board is connected to the SDI HSMC.
.
Figure 6. Hardware Setup
HSM
C Port B
HSM
C Port A
HSM
C Port A
SDI OUT 1
SDI OUT 2
SDI OUT 1
SDI OUT 2
SDI IN 1
SDI IN 2
SDI IN 1
SDI IN 2
Stratix IV GX Development Board
Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design December 2010 Altera Corporation
Getting Started Page 7
Table 1 describes the HSMC ports that are mapped to the design instance.
Table 2 describes the function of each user-defined dual in-line package (DIP) switch control. When the switch is in the OFF position, logic 1 is selected. When the switch is in the ON position, logic 0 is selected.
Table 1. Mapping of HSMC Ports to the Design Instance
HSMC Port Design Instance Name Description
HSMC Port A
SDI OUT 1 hd_dl_tx_inst (HD Link B) Transmits lower stream of the dual link HD-SDI data[19:0].
SDI OUT 2 hd_dl_tx_inst (HD Link A) Transmits upper stream of the dual link HD-SDI data[39:20].
SDI IN 1 threeG_rx_inst0 Triple-standard receiver receives the 3G-SDI Level B signal.
SDI IN 2 threeG_rx_inst1Triple-standard receiver receives the 3G-SDI Level B signal (for loopback verification).
HSMC Port B
SDI OUT 1 tripleStd_tx_inst2 Triple-standard transmitter transmits HD stream A or stream B signals.
SDI OUT 2 tripleStd_tx_inst3Triple-standard transmitter transmits 3G-SDI Level B signal from two HD streams.
SDI IN 1 hd_dl_rx_inst (HD Link B) Receives lower stream of the dual link HD-SDI data[19:0].
SDI IN 2 hd_dl_rx_inst (HD Link A) Receives upper stream of dual link HD-SDI data[39:20].
Table 2. SW3 DIP Switch Controls
DIPSW Description
8 1= Hold reset
0= Release reset
7 1= hd_dl_tx_inst: hd txdata from the internal pattern
0= hd_dl_tx_inst: hd txdata demux from the 3gb
6 1= tripleStd_tx_inst3: 3gb txdata from the internal pattern
0= tripleStd_tx_inst3: 3gb txdata mux from hd_dl_rx_inst
5 1= tripleStd_tx_inst2: hd txdata link A
0= tripleStd_tx_inst2: hd txdata link B
4, 3,2 1 Not used
December 2010 Altera Corporation Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design
Page 8 Getting Started
Table 3 describes the function of each LED on the Stratix IV GX development board.
Table 3. LEDs on Stratix IV GX FPGA Development Board
LED Description
0 Alignment lock
HSMC port A: 3G SDI receiver inst0
1 TRS lock
HSMC port A: 3G SDI receiver inst0
2 Frame lock
HSMC port A: 3G SDI receiver inst0
3 Not used
4 Alignment lock
HSMC port A: 3G SDI receiver inst1
5 TRS lock
HSMC port A: 3G SDI receiver inst1
6 Frame lock
HSMC port A: 3G SDI receiver inst1
7 Not used
8 Alignment lock
HSMC port B: Dual link HD-SDI receiver (Link A)
9 TRS lock
HSMC port B: Dual link HD-SDI receiver (Link A)
10 Frame lock
HSMC port B: Dual link HD-SDI receiver (Link A)
11 Alignment lock
HSMC port B: Dual link HD-SDI receiver (Link B)
12 TRS lock
HSMC port B: Dual link HD-SDI receiver (Link B)
13 Frame lock
HSMC port B: Dual link HD-SDI receiver (Link B)
14 Not used
15 Dual link HD-SDI receiver
Link A and Link B is aligned
Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design December 2010 Altera Corporation
Getting Started Page 9
Figure 7 shows the orientation of the LEDs on the Stratix IV GX development board..
Figure 7. User LED on the Stratix IV FPGA Development Board
Stratix IV GX Development Board
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
FPGA
LCD Display
HSMC HSMC
User LED
December 2010 Altera Corporation Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design
Page 10 Getting Started
Running the Reference DesignTo run the reference design, follow these steps:
1. Connect two SDI HSMCs to the HSMA and HSMB ports on the FPGA development board as shown in Figure 6 on page 6.
2. Set up the HSMC port A and HSMC port B connections to map the 3G-SDI level B to the dual link HD-SDI. Connect an SDI signal analyzer to the transmitter output SDI OUT 1 port or SDI OUT 2 port as shown in Figure 8.
.
3. Connect the power supply to the board.
4. Launch the Quartus II software and compile the reference design. To compile the reference design, follow these steps:
a. On the File menu click Open Project, navigate to \<directory>\s4gxsdi.qpf, and then click Open.
b. On the Processing menu, click Start Compilation.
5. Download the Quartus II-generated SRAM object file (.sof):
a. Connect the USB-Blaster™ download cable to the board’s USB Type-B Connector.
b. On the Tools menu, click Programmer. The software automatically detects the s4gxsdi.sof file during compilation and it appears on the pop-up window. Click Start to download the Quartus II-generated file to the board. If the file does not appear in the pop-up window, click Add File, navigate to \<directory>\s4gxsdi.sof, and then click Open.
1 This design is volatile. You must reload this design each time the board is powered on.
Figure 8. 3G-SDI Level B to Dual Link HD-SDi Hardware Setup
HSMC Port BHSMC Port AHSMC Port A
SDI OUT 1
SDI OUT 2
SDI OUT 1
SDI OUT 2
SDI IN 1
SDI IN 2
SDI IN 1
SDI IN 2
Stratix IV GX Development Board
SDI Signal Analyzer
Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design December 2010 Altera Corporation
Getting Started Page 11
6. To transmit 3Gb signal (port B) using the internal pattern, set DIPSW6 = 1 and DIPSW7 = 0. Reset the hardware by controlling DIPSW8.
7. Observe the signal behavior on your signal analyzer. SDI OUT 1 port signal represents the HD stream A signal and the SDI OUT 2 port signal represents the HD stream B signal, demux from receiving 3GB signal.
..
8. Connect the dual link HD-SDI Link A signal source from the SDI OUT 2 port of the HSMA to the receiver input SDI IN 2 port of the HSMB. Connect the dual link HD-SDI Link A signal source from the SDI OUT 1 port of the HSMA to the receiver input SDI IN 1 port of the HSMB. Observe the HD dual link receiver. Link A and Link B receiver should be able to lock.
Figure 9. HD Link A and HD Link B Image
December 2010 Altera Corporation Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design
Page 12 Getting Started
9. Set up the HSMC port A and HSMC port B connections to map the dual link HD-SDI to the 3G-SDI level B. Connect the dual link HD-SDI Link A signal source from the SDI OUT 2 port of the HSMA to the receiver input SDI IN 2 port of the HSMB. Connect an SDI analyzer to the transmitter output SDI OUT 1 port or SDI OUT 2 port of the HSMB as shown in Figure 10.
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10. Repeat steps 3, 4, and 5.
11. To transmit HD dual link signal (port A) using the internal pattern, set DIPSW6 = 0 and DIPSW7 = 1. Reset the hardware by controlling DIPSW8.
12. Observe the signal behavior on your signal analyzer. SDI OUT 2 port signal represents the interleaved multiplexed 3Gb signal and SDI OUT 1 port signal represents the demultiplexed HD dual link signal.
Figure 10. 3G-SDI Level B to Dual Link HD-SDI Hardware Setup
HSM
C Port B
HSM
C Port A
HSM
C Port A
SDI OUT 1
SDI OUT 2
SDI OUT 1
SDI OUT 2
SDI IN 1
SDI IN 2
SDI IN 1
SDI IN 2
Stratix IV GX Development Board
SDI Signal Analyzer
Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design December 2010 Altera Corporation
Getting Started Page 13
13. Specify the following board settings, and observe the signal behavior. Specify DIPSW5 = 1 to control output link A or link B for SDI OUT 1 port.
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14. Connect the SDI OUT 2 port of the HSMB to the receiver input SDI IN 1 port of the HSMA. Ensure that the 3Gb signal that is transmitted from SDI OUT 2 port of the HSMB is locked by the 3G instance of SDI IN 1 port of the HSMA.
15. Observe the condition of the LEDs for the following implementations:
a. The LEDs indicate the following conditions for the 3G-SDI instance Ch0:
■ LED 0 illuminates when the receiver is word aligned.
■ LED 1 illuminates when the received line format is stable.
■ LED 2 illuminates when the receiver frame format is stable.
Figure 11. SDI_OUT1: HD Link B (if internal Pattern is Selected)
Figure 12. SDI_OUT2: HD Link A (if internal Pattern is Selected)
December 2010 Altera Corporation Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design
Page 14 Getting Started
b. The LEDs indicate the following conditions for the 3G-SDI instance Ch1:
■ LED 0 illuminates when the receiver is word aligned.
■ LED 1 illuminates when the received line format is stable.
■ LED 2 illuminates when the receiver frame format is stable.
c. The LEDs indicate the following conditions for the dual link HD-SDI receiver (Link A):
■ LED 8 illuminates when the receiver is word aligned.
■ LED 9 illuminates when the received line format is stable.
■ LED 10 illuminates when the receiver frame format is stable.
d. The LEDs indicate the following conditions for the dual link HD-SDI receiver (Link B):
■ LED 11 illuminates when the receiver is word aligned.
■ LED 12 illuminates when the received line format is stable.
■ LED 13 illuminates when the receiver frame format is stable.
Figure 13. Condition of LEDs for 3G-SDI Instance Ch0
Figure 14. Condition of LEDs for 3G-SDI Instance Ch1
Figure 15. Condition of LEDs for Dual Link HD-SDI (Link A)
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design December 2010 Altera Corporation
Conclusion Page 15
e. The LEDs indicate the following conditions when the dual link HD-SDI (Link A) receiver is carry parallel rxdata[39:20], while the HD dual link B is carry parallel radata[19:0]:
■ LED 15 illuminates when Link A and Link B of the dual link HD-SDI receiver are aligned.
ConclusionThis application note provides ways to use the SDI reference design with the Stratix IV GX development board and the SDI HSMC to perform conversions between the dual link HD-SDI and 3G-SDI.
Document Revision HistoryTable 4 shows the revision history for this document.
Figure 16. Condition of LEDs for Dual Link HD-SDI (Link B)
Figure 17. Condition of LEDs when HD-Dual Link A and Link B are Aligned
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
Table 4. Document Revision History
Date Version Changes
December 2010 1.0 Initial release.
December 2010 Altera Corporation Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design
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