AMS Methodology Kit Version 5.1.0picture.iczhiku.com/resource/eetop/whiFtzjJRpDTeXNb.pdf · 2019. 11. 11. · Run Assura DRC: Design Rule Checking _____ 54 Run Assura LVS: layout

AMS Methodology Kit Version 5.1.0.2

Analog-Driven Physical Implementation

Workshop Version 5.1.0.2

Software BOM

IC5141_ISR24 - 5.1.41.500.2.24 SOCE 4.2_USR2 (RC 5.1_USR2)

ICC11241_USR1 - 11.2.41.01 ASSURA 3.1.4_USR1

AMS Methodology Kit – Analog Driven Physical Implementation – Workshop Manual

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Cadence AMS Methodology Kit Product Version 5.1.0.2 November 2005

© 2005 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America.

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Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence's trademarks, contact the corporate legal department at the address shown above or call 800.862.4522.

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All other trademarks are the property of their respective holders.

Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence's customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information.

Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.


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Cadence AMS Methodology Kit The flow workshop you are about to take is a component of the Cadence AMS Methodology Kit. The Cadence AMS Methodology Kit is a complete front-to-back reference example that can be used to better understand a comprehensive “Advanced Custom Design Methodology”, which you can leverage for techniques and methods to apply to your own design. The Kit is composed of three primary design flows, all of which are demonstrated on the same reference design, interact and work together for a complete front-to-back solution. These include top-level simulation and analysis – “AMS Top-level Flow”, top-level physical design – “Analog Driven Physical Implementation”, and block creation – “AMS Block Creation with Migration and Reuse”.

The Reference Design used is a 10/100 Ethernet Phy, which contains approximately 30K analog transistors and 60K digital gates. The “AMS Block Creation Flow with Migration and Reuse” is the starting point, where a front-to-back example of a Sample and Hold block, which is part of a larger 6-bit ADC circuit. This includes methodologies for both initial block creation and subsequent migration and reuse. Migration and reuse are demonstrated using two methods:

♦ starting with layout migration ♦ starting with a more automated circuit sizing and layout synthesis approach

In addition to this workshop example, the Cadence AMS Methodology Kit also contains migration and reuse examples of the full 6-bit Flash ADC circuit - a bigger, more hierarchical block. The “AMS Top-level Flow” walks through the creation of a top-level simulation strategy, relying on mixed-level techniques. This includes a strategy to take advantage of

AMS Top-level Flow

Analog-Driven Physical

Implementation Flow

AMS Block Create w/ Reuse

Flow


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parasitics throughout the design process. In addition, the methodology to manage multiple power supplies through the use of inherited connections, is demonstrated. The “Analog Driven Physical Implementation Flow” provides an example of top-level physical design digital implementation of a standard cells based block – along with its subsequent integration with the “analog-driven” design. Further information, including flow and methodology whitepapers and datasheets are available at http://www.cadence.com/products/Kits/ams/index.aspx. The Cadence AMS Methodology Kit (including this workshop data) is available for distribution through your account manager, and consists of:

♦ The Ethernet PHY reference design (transistors, layouts, schematics, behavioral models and more)

♦ (3) design flows explained above, complete with step-by-step documentation, simulation plans and associated examples

♦ 6-bit Flash ADC example for reuse and migration ♦ 90 nm generic process design kit ♦ 5 days Applicability Training, where AMS experts will help map the

methodology and techniques to your design. Enjoy your flow workshop!


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About this workshop This workshop introduces a complete block authoring flow from floor-planning through digital implementation to final verification. It is designed to allow anyone with a basic knowledge of physical implementation and Cadence tools to complete the entire flow in a half day. This workshop does not replace comprehensive product training offered by Cadence. It is meant to provide an introduction to the design flow and methodology to be used when doing analog driven, mixed-signal physical implementation. There are (5) independent modules presented in this workshop:

1) Block Floorplanning using Virtuoso-XL and Virtuoso Preview 2) Digital Implementation using RTL Compiler and NanoEncounter 3) Block Power and Signal Routing using Virtuoso Chip Assembly Router 4) Physical Verification using Assura DRC and Assura LVS 5) Parasitic Extraction using Assura RCX

“Golden” versions of data are available at the start of every module. This helps make the workshop more predictable and allows you to finish on time. It will also serve as a back-up should you choose to explore an area and lose or destroy needed data.

Other Available Workshops ♦ Advanced Custom Design Methodology: AMS Block-Level Flow ♦ Advanced Custom Design Methodology: AMS Top-Level Simulation Flow ♦ Advanced Custom Design Methodology: RFIC Design Flow ♦ Advanced Custom Design Methodology: System I/C ♦ Encounter RTL Compiler ♦ SoC Encounter™ ♦ Cadence Signal and Power Integrity Closure Flow ♦ Encounter Test Solutions

Conventions ♦ What is Covered: lists the module learning objectives. ♦ In this section… describes design stage and desired outcome for the objective. ♦ Actions to be performed on your laptop will direct you to the current window

and instruct you to use an interactive (pull-down menu, pop-up menu, or bindkey) or text based command to be entered on the tool’s command line. - Multiple menu references may be listed in bold print. For example, Select

=>Nets => By List would use the banner menu Select followed by sub-menu Nets, followed by sub-menu By List.

- Mouse clicks may be defined with LMB, MMB, or RMB. These refer to left, middle, or right mouse buttons.

- Bindkeys will be listed in “” such as “f” for Window => Fit. - File or command name references will be listed in courier font.

This workshop is staffed by several Cadence Application Engineers. Make use of them whenever you have a question or a problem. That is why they are here.


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Table of Contents

Cadence AMS Methodology Kit _________________________________ 2

About this workshop __________________________________________ 5

Analog Driven Physical Implementation Flow _____________________ 8

Module 1: Block floorplanning _________________________________ 9

Testcase Overview ___________________________________________________ 10

Soft block abstract generation and area estimation ________________________ 10

Block and IO placement ______________________________________________ 17

Block modification: stretch, chop, reshape _______________________________ 20

Soft Block Pin Optimization ___________________________________________ 21

Export a block for analog implementation _______________________________ 23

Create a block abstract from layout and update floorplan __________________ 24

Export a block for digital implementation _______________________________ 25

Module 2: Digital Implementation ______________________________ 27

Introduction to RTL Compiler_________________________________________ 28

Introduction to Encounter ____________________________________________ 32

Design Import and Loading DEFs ______________________________________ 33

Silicon Virtual Prototyping____________________________________________ 35

Global Physical Synthesis _____________________________________________ 38

Clock Tree Synthesis _________________________________________________ 39

Detailed routing with NanoRoute_______________________________________ 40

Block Finishing______________________________________________________ 41

Importing Encounter Digital Block results into Virt uoso ___________________ 43

Module 3: Block power/signal routing ___________________________ 44

Autoroute block power nets ___________________________________________ 45

Interactively river route busses ________________________________________ 49

Matched length and shielded nets ______________________________________ 51

Autoroute signal nets _________________________________________________ 52

Saving and Importing the Routed Design ________________________________ 52

Module 4: Physical Verification ________________________________ 53

Run Assura DRC: Design Rule Checking ________________________________ 54

Run Assura LVS: layout vs. schematic verification ________________________ 58


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Module 5: Parasitic Extraction & Simulation _____________________ 61

Assura RCX: Extract top level routing parasitics _________________________ 62

Back-annotate RCX parasitics _________________________________________ 65


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Analog Driven Physical Implementation Flow The analog driven physical implementation flow encompasses much of the physical design process from RTL to floor-planning through tapeout. This is a schematic driven flow which leverages Virtuoso as a design and an analysis cockpit. Initial floorplanning, digital implementation, top-level routing, physical verification, and parasitic extraction and analysis are covered. Due to limited time, additional analysis capability such as Assura RF, CeltIC NDC, PacifIC, and VoltageStorm are not covered in this workshop, but may be considered for a full physical implementation flow. A task flow for physical implementation is shown in Figure 1. The tasks have been mapped to tools in Figure 2. Our workshop will make use of the tool flow with our reference design (excluding AM/S Block Implementation and VoltageStorm).


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Module 1: Block floorplanning

In this section… We will concentrate on the portion of the ADPI flow shaded in gray and labeled with bold font:

What is covered: � Testcase Overview � Soft block abstract generation and area estimation � Block and IO placement � Block modification: stretch, chop, reshape � Soft block pin optimization � Create a block abstract from layout and update

floorplan � Export a block for digital implementation


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START SOFTWARE Actions:

1) Login to workshop laptop with userid amskit and password demoman. 2) Start the software and run the following shell commands:

� cd $HOME/adpi_flow_workshop � source setup.csh Use the alias startlic to start the license: � startlic

Be sure to reset all of the workshop data: � source reset_all.csh

Use the alias cdcdb to change the directory to: /export/home/cic/amskit/adpi_flow_workshop/ether_cd b � cdcdb � icfb

Testcase Overview In this section… The testcase for this workshop is an IEEE802.3u compliant 10/100 Base Ethernet Phy design. It supports both 10Base-T and 100Base-TX applications. The MII data and management interface between Ethernet PHY and Ethernet MAC is also integrated. The design utilizes a generic 90 nm process and operates at a system clock frequency of 125 or 160 MHz. It has (6) major blocks: (5) are analog/mixed and (1) is a digital, DSP core. As our workshop begins, (4) of the analog blocks have completed layout, schematics exist for (5) analog blocks, and a synthesis area report exists for our digital DSP core. The information needed to derive a floorplan exists in the form of schematics, symbols, and abstracts. In Module 1, we will create the initial top-level floorplan, create floorplans for our (2) soft blocks, create an abstract view for the analog soft block and export the floorplan we create for the digital block.

Soft block abstract generation and area estimation In this section… you will import the gate level verilog created during RTL Compiler synthesis for the digital DSP block called top_1_port_pnr. You will then open and explore the top-level cellView called ether_VDI/ top_module1A/ schematic. From the schematic window, the Hierarchy Browser will be used to navigate the logical hierarchy of the top_module1A block, set properties to create soft block abstracts, and generate the physical hierarchy for the Virtuoso Preview floorplanner.


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Actions: 1) In the CIW, choose File => Import => Verilog… Form information may be

loaded from a previously saved template. a. Select the Load icon at the top of the Verilog In form. b. On the Load Parameters form, specify the file ./skill/ihdlEnvFile1. Click

OK. c. Click OK on the Verilog In form. d. Import Verilog progress is reported in the CIW. When VerilogIn

completes, check the log and verify the bottom of the log file says:

Checked in schematic top_1_port_pnr. End of Logfile.

2) The reference libraries displayed in the Library Manager include:

a. gpdk090, a generic 90 nm PDK b. gsclib090, a digital standard cell library designed with the gpdk090 c. ether, a design library for the ether block d. ether_VDI, a design library for our labs which includes the results of

Verilog Import for the synthesized digital block.

e. Select Library ether _VDI and Cell top_module1A. In the View column, hold down RMB over schematic and Open...


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3) The Verilog Import performed in step 1) requires the top_module1A schematic to be extracted. Use Check => Hierarchy… with the form defaults and click OK .

The top schematic of the mixed signal ether_VDI makes use of Inherited Connections, a technique for managing power and ground connections. The design block consists of (4) hard sub-blocks and (2) soft sub-blocks. The hard blocks are already laid out and will use abstract views of these blocks during floorplanning. The (2) soft blocks not yet implemented are Bias_port and top_1_port_pnr. You will define the soft blocks during this exercise and create floorplans for sub-block implementation and a floorplan ready for top-level for routing.

Hierarchy Browser In this section… the Hierarchy Browser makes use of the schematic information and maps it to a physical representation which reflects area and connectivity. In a top-down design flow, this step is done multiple times since the schematic is typically changing up until when the design is taped out. After running the Hierarchy Browser, the top-level design will have an autoLayout view created. This will have hard-block abstracts and soft-block autoAbstracts instantiated.


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Depending upon the properties defined for blocks with the Hierarchy Browser, digital blocks may also have autoLayout views created which instantiate standard cell abstracts. In a top-down flow, all blocks would typically start as soft blocks (autoAbstract) which would be shaped and have pins optimized. This information would seed the layout views with an aspect ratio and pin placement. An abstract view may be derived from the layout view. An abstract view represents a hard block because it cannot be shaped or have its pins moved. Actions:

4) In the Schematic window, switch the toolbar by choosing Tools => Floorplan/Schematics. This enables the Floorplan pull-down. Choose Floorplan => Hierarchy Browser… and click OK in the Open Hierarchy Browser form.

The Hierarchy Browser is a fast and easy method to navigate the logical hierarchy of any schematic. Instead of descending into each individual schematic component and then returning to the top level, you can use the browser to see what is in the schematic and how it is organized. If a block includes standard cells, they will be represented as a diamond with an instance count.

5) In the Hierarchy Browser form, select top_module1A. It will turn red.

Expand the hierarchy by using Hierarchy => Expand Selected. The (6) blocks previously seen in the schematic are now visible.

Creating soft block abstracts In this section… the Hierarchy Browser is used to create autoAbstracts for the soft blocks. This design will be a derivative of an already existing ether block layout. You will reuse (4) hard blocks from the old layout while creating autoAbstracts for (2) soft blocks. The hard blocks have abstracts which were derived from layout. These have fixed block size, shape, and pin locations. Only logical hierarchy exists for the (2) soft


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blocks, there are no physical layouts yet. Prior to completing the property information on the Hierarchy Browser forms, we will gather area information for the soft blocks.

6) Determining the area for Bias_port (analog block) may be done with Skill callbacks or with Virtuoso XL. In this workshop, we will make use of Virtuoso XL.

a. From the Library Manager , open ether_VDI/ Bias_port/ schematic. b. From the ether_VDI/ Bias_port/ schematic window, switch the toolbar by

choosing Tools => Design Synthesis => Layout XL. c. On the Startup Option form, select Create New and click OK . d. On the Create New File form, use the form defaults and click OK or on

the Already Exists form, click Yes to overwrite the layout view. e. In the ether_VDI/ Bias_port/ layout window, choose Design => Gen

From Source…

♦ Select all (6) Generate options

In the I/O pins section: ♦ Change the Default

from geometric to symbolic

♦ Change Layer/Master to Metal2_T

♦ Click Apply . ♦ Set Pin Label Shape

to Label In the Boundary section: ♦ Set Layer to

prBndry/ by [purpose: boundary]

♦ Set the Utilization to 65%

♦ Set the Aspect Ratio (W/H) to 3.0

♦ Set Area Calculation: to BBox Based

The completed form should look like the figure to the right. Click OK on the Layout Generation Options form.


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f. In the layout window, select the cyan rectangle (layer prBoundary, purpose boundary). What is the width? _________ What is the length? _________

g. Save ether_VDI/ Bias_port/ layout and close the window. h. Close the ether_VDI/ Bias_port/ schematic window.

7) Determining the area for top_1_port_pnr (digital block) may be done by:

♦ Estimating gate count ♦ Importing a verilog netlist from synthesis ♦ Using an area report generated during synthesis

The area report from RTL compiler is located at: ../ether_work/rc /reports/top_1_port_pnr_area.rpt

The cell area is 138181 um^2 which is 100% utilization. Since we have already imported the verilog netlist for the top_1_port_pnr block, Virtuoso Preview will be able to calculate the appropriate area which is the second option listed above.

8) Returning to the

Hierarchy Browser form, click on the top_1_port_pnr and Bias_port blocks:


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9) In the Hierarchy Browser form, click “q” to set the properties on the selected blocks. Review the Cell Name displayed on the Set Master Properties form. Populate the forms depending upon the Cell Name:

Cell Name Propeties top_1_port_pnr Select:

♦ AutoLayout and Abstract ♦ Min Aspect Ratio: 2.0 ♦ Pin Type: Metal6_T ♦ Click OK .

Bias_port Select: ♦ Abstract Only ♦ Min Aspect Ratio: 3.0 ♦ Max Aspect Ratio: 3.0 ♦ Utilization (%): 100. Recall this value already has a 65%

utilization calculated by Virtuoso XL. ♦ Area: Calculate the Bias_port area from step 5f). What value are you using? ___________ ♦ Pin Type: Metal2_T ♦ Block Type: Analog ♦ Click OK .

top_module1A Use the form defaults and click OK . 10) In the Hierarchy Browser, select

Hierarchy => Generate Physical Hierarchy . Look in the CIW for messages like those shown in the figure to the right:

11) In the Hierarchy Browser form,

Window => Close.

12) In the schematic window, click Window => Close.


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Block and IO placement In this section… you will open the ether_VDI/ top_module1A/ autoLayout cellView and use floorplanning commands to restore previous block and pin placements. Actions:

1) From the Library Manager , open ether_VDI/ top_module1A/ autoLayout.

2) Opening an autoLayout cellView automatically starts the

floorplanning environment (Tools => Virtuoso Preview). The Object Selection Window, or OSW, form is displayed. The OSW allows you to activate different floorplanning objects during this phase of the design much like the LSW does with the layout editors.

3) Initializing the floorplan allows you to initialize selected objects in the floorplan and load floorplan files. Floorplan files can contain placed or partially placed IO components, IO pins, blocks, cells, special routing, or any combination of these design objects. Initializing also allows the placement, routing, and manufacturing grids to come into the floorplan from the tech file.

In the autoLayout window, a. Choose Floorplan =>

Reinitialize b. Click on Load a Floorplan File

Specify the File Name: ../ether_work/vxl/FPfile.top c. Click OK.

When you clicked OK, all the blocks were moved from the initial design boundary and placed to the left. The Floorplan File then provided placement information for blocks and pins. Only the (2) soft blocks remain unplaced.


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4) Explore the design using bindkeys: a. Press the “f” key to fit the view. b. Press the “F” key to display all levels Note that the anlg_ctrl and top_1_port_receive blocks are rectilinear. Virtuoso Preview now supports the block placement and pin optimization on rectilinear blocks.

5) Next, we will analyze the block

connections to determine where the soft blocks should be moved to. This can be done with “flight lines” or with Analyze => Connectivity. Let’s start with “flight lines”. In the OSW, click on Net and Instance. Click on one of the soft blocks and then the “T” bindkey. Flight lines show all the connections that were originally defined in the schematic. Note that the top_1_port_pnr block has many more pins than the Bias_port

Another approach for analyzing block connections is to use Analyze => Connectivity. a. Deselect all “flight lines” by

clicking in the black space. b. In the OSW, select only Instance. c. Select all instances with the “ctrl a”

keys. d. Select the Analyze =>

Connectivity pull down menu. e. Click on Analyze. f. Select “ctrl f ” to see the

connectivity information. From this view, it is more difficult to determine where the soft blocks should be placed. Neither soft block shows strong connectivity to neighboring blocks. The largest number of connections was displayed with “flight lines” between the top_1_port_pnr block and the pre-placed, symbolic pins. Both techniques, “flight lines” and connectivity analysis, are useful for determining how blocks should be placed. g. Click Cancel on the Connectivity Display form.


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6) Based upon our connectivity analysis, move the Bias_port block to the upper right of the floorplan. Use the “m” bindkey or Edit => Move.

Before moving on to the next section, read a previously saved floorplan file. Open Floorplan => Floorplan File => Read… and specify the file named: ../ether_work/vxl/FPfile. Your floorplan should now look like this:


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Block modification: stretch, chop, reshape In this section… you will shape the digital soft block to achieve a smaller floorplan. As a floorplan matures, block reshaping will become more critical. While some blocks will be laid out smaller than originally estimated, others may grow. When soft blocks have autoLayout views, utilization information can be dynamically displayed as blocks are reshaped. The autoLayout views are created for digital soft blocks when a schematic is defined/imported. Actions:

1) Reshape the top_1_port_pnr block: a. Zoom in to the top_1_port_pnr block with RMB and use “F” to display

all levels of hierarchy. b. To stretch the top_1_port_pnr block, use Edit => Soft Blocks => Stretch

or the “ctrl S” bindkey. Stretch the top edge of the block until the utilization is 56%.

c. Clear the overlap marker with the “c” bindkey. d. Select the

top_1_port_pnr block. Chop the block to remove the overlap and to create a routing channel for top level routing. Use Edit => Soft Block => Chop or the “ctrl X ” bindkey. Select the 1st point of the chop rectangle near the red circle on the picture to the right. Select the 2nd point of the chop rectangle outside the lower right corner of the top_1_port_pnr block.

e. Deselect the top_1_port_pnr block by clicking in the black space. f. Stretch the right edge of the top_1_port_pnr block until the utilization is

about 64%. This will leave plenty of room for power routing and timing optimizations inside the digital block in Module 2.


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Soft Block Pin Optimization In this section… you will optimize the pins on the soft blocks. The pins will move around on the edges of the soft block boundaries. Their new location will shorten the routing length between all the blocks. Actions:

1) Select only the top_1_port_pnr block. Choose Edit => Soft Pins =>

Optimize/Float a. Click the selected button next to

Work On b. Click on Switch Pin Layer and

replace the layer list for Top/Bottom with Metal6 and Left/Right with Metal3.

c. Click the Optimize button at the bottom of the form

d. The messages in the CIW may be ignored for now. After making additional pin modifications, we will re-check the pin placement.

e. Cancel the Modify Soft Pins form

2) Inspect the pin locations on the top_1_port_pnr block after optimization. The pins connecting from the top_1_port_pnr block to the top-level design can be improved through the use of pin alignment. a. In the OSW, select Instance,

Net and Pin. b. Select the pins along the top

of the design above the top_1_port_pnr block. These are marked with red rectangle in the figure to the right.

c. Choose Edit => Soft Pins => Align…

d. Select the top_1_port_pnr block by clicking in an area near the yellow X as shown to the right.

e. After alignment, the nets should appear like those shown above..

3) When the newly aligned pins were moved, their pin layer did not change. In

the OSW, select only Pin. Select the area shown with the orange oval above.


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Query all pins with the “q” bindkey. Select the Common button and change the Pin Type to Metal6_T.

4) Select the top_1_port_pnr block and use Edit => Soft Pins => Pin Overlap

to confirm there are no overlapping pins on the top_1_port_pnr block.

5) Leaving the top_1_port_pnr block selected, return to the Edit => Soft Pins => Optimize/Float form. Select Fix.

6) Select only the Bias_port block. Choose Edit => Soft Pins =>

Optimize/Float a. Click the via_via button next to Pin Spacing b. Click the selected button next to Work On c. Click on Switch Pin Layer and replace the layer list for Top/Bottom with

Metal2 and Left/Right with Metal2. d. Click the Optimize button at the bottom of the form e. Look in the CIW to see that the pin optimizer ran successfully f. Cancel the Modify Soft Pins form

7) Can the pin locations on the Bias_port block be improved? The VDDRX and

GNDRX pins on the Bias_port block can be aligned with those on the top_1_port_receive block. a. In the OSW, select Instance, Net, and Pin. b. Choose Edit => Soft Pins => Align… c. Select the GNDRX and VDDRX pins on the top_1_port_receive block.

These pins are circled in yellow in the figure on the left below. d. Select the target block, Bias_port. e. Select the newly aligned GND and VDD pins on the Bias_port block.

Query the pins with “q” and resize them to be 5 um wide on Metal2_T. They should appear like the pins circled in red in the figure on the right below.


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8) Save your work by using Design => Save As. Specify the View Name pinOpt . 9) Use Window => Close and do not bother to save the cellViews listed because

you just did a save.

Export a block for analog implementation In this section… you will use the floorplan created with Virtuoso Preview to update the layout created with VXL. Actions:

1) From the Library Manager , open ether_VDI/ Bias_port/ ADPIpinOpt_autoAbstract .

2) Restore the Virtuoso Preview menus using Tools => Virtuoso Preview. Use

Floorplan => Floorplan File => Write… Click OK.

3) From the Library Manager , open ether_VDI/ Bias_port/ layout. This was the layout view previously created with VXL. Restore the Virtuoso Preview menus and use Floorplan => Floorplan File => Read… and specify a File Name of FPfile.

4) Return the toolbar to VXL with Tools => Layout XL and run Edit => Place

As In Schematic. Although less than optimal, the devices are now mapped to the same placement as what was seen with the schematic.

5) View the device connectivity with Connectivity => Show Incomplete Nets…

Click on Select All and Apply . These “flight lines” can assist in manual placement and routing. We will not actually do any custom analog layout in this workshop.

6) Close out of all open cellViews.


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Create a block abstract from layout and update floorplan In this section… you will take a completed block layout view and generate an abstract view for it. The resulting abstract view will be replaced in our top-level floorplan. This will be the most basic abstract view which can be used with VCAR. It will not contain detailed obstructions. Actions:

1) Copy ether_VDI/ Bias_port/ layout_final cellView and replace your ether_VDI/ Bias_port/ layout cellView. This is a complete layout of the Bias_port block which leveraged the pin information we obtained from Virtuoso Preview. a. From the Library Manager , open ether_VDI/ Bias_port/ layout_final. b. Use Design => Save As… c. Specify ether_VDI/ Bias_port/ layout d. Click OK . e. Use Window => Close or “ctrl w ” bindkey to close the window. f. From the Library Manager , open the ether_VDI/ Bias_port/ layout.

2) Launch the Abstract GUI:

a. Use Tools => Abstract Editor… b. Select Abstract => Create Abstract… Use the form defaults and click

OK .

2) Choose Flow => Pins and use defaults. Click on Run.

3) Choose Flow => Extract and use defaults. Click on Run.

4) Choose Flow => Abstract. We are creating a basic abstract view without detailed blockage. a. Click on the

Blockage tab. b. Select Model

wide wire obstructions

c. Click on Run.

5) Choose File => Exit. Are you sure? Yes


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6) In the Library Manager , use View => Refresh and then open ether_VDI/

Bias_port/ abstract.

7) Close ether_VDI/ Bias_port/ abstract and open ether_VDI/ top_module1A/ ADPIpinOpt.

8) Select the Bias_port block. Choose Floorplan => Replace View. Change the

To View Name to abstract. Click OK .

Will the new abstract view require a floorplan change? ______ Do the pin locations look ok? _______

Export a block for digital implementation

In this section… you will complete the steps needed to export a DEF for Encounter to use. In the previous section, the pins were optimized and put on preferred layers of Metal6 for top/bottom edges and Metal3 for right/left edges. The VDD and GND pins were placed on Metal4. These assignments were done with the consideration of the power rings and stripes we plan to implement with Encounter. The Status was set to FIXED so that the pins would not be moved by Encounter. Actions:

1) Open ether_VDI/ top_module1A/ ADPIpinOpt. All of the pins on the top_1_port_pnr block instance are on preferred layers and their status is set to FIXED .

2) Exporting a DEF with a rectilinear shape requires an autoLayout view which

needs to be in sync with the autoAbstract view. Thus far, all of our edits have been with the autoAbstract view. Select the top_1_port_pnr block and then choose Floorplan => Update AutoLayouts. Deselect Generate TDCover. This is an old methodology which does not work with Encounter. Click OK .


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3) To export the DEF, choose File => Export => DEF… from the CIW. Specify the DEF File Name to be top_1_port_pnr.def. If your form looks like the following figure, then click OK . The CIW should contain the message: DEF out completed.

4) Close out of icfb with File => Exit… in the CIW. Save all views which are currently open.

5) The resulting DEF contains a property which causes a leading “|” to get added

to all pins and nets when the design is imported back into Virtuoso Preview. For Assura compatibility, we do not want this to happen. A simple edit to the DEF solves this problem.

a. Use the same shell icfb was running in. With your favorite text editor, open

top_1_port_pnr.def and delete these (4) lines:

PROPERTYDEFINITIONS DESIGN PreviewDEF STRING "HasLeadingChar" ; END PROPERTYDEFINITIONS


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Module 2: Digital Implementation


What is covered: � Introduction to RTL Compiler � Introduction to Encounter � Import Design and DEF created with Virtuoso

Preview � Silicon Virtual Prototyping � Global Physical Synthesis � Detailed routing with NanoRoute � Block Finishing


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START SOFTWARE Actions:


� cd $HOME/adpi_flow_workshop � source setup.csh

Use the alias startlic to start the license. Only do this if the license was not previously started. � startlic

Introduction to RTL Compiler In this section… you will review how to launch RTL Compiler to generate a write_template script. We will then review the script and synthesis constraints which were used to generate the netlist for this workshop. Actions:

1) Use the alias cdrc to change the directory to: /export/home/cic/amskit/adpi_flow_workshop/ether_wo rk/rc

2) Start RTL Compiler with a VDI license by using: rc –vdi 3) From the rc prompt type:

rc:/> write_template > my.template rc:/> exit

4) Compare the my.template file from above to the script used for running RTL Compiler for this workshop. It is located at scripts/rc.tcl and is referenced in the table below:

Tcl command Explanation

include load_etc.tcl set DESIGN top_1_port_pnr set SYN_EFF medium set MAP_EFF medium set map_timing 1 set global_map_report 1 set map_fancy_names 1 set iopt_stats 1

Script constants are defined


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set SYN_PATH "." set _OUTPUTS_PATH outputs set _LOG_PATH logs set _REPORTS_PATH reports

set_attr lib_search_path \ {../../../FLOW_ETHER_CDK090/share/CDK090/gsclib090/ timing} set_attr library {slow.lib}

A target library is specified

set_attr information_level 7 / set_attr hdl_array_naming_style %s\[%d\] /

Additional attribute information is defined for reporting and naming

include ./scripts/import_rtl.tcl Include script for importing RTL Note: RTL is coming from the CDB: the same location referenced for simulation.

elaborate $DESIGN

Elaboration confirms all of the RTL references and syntax are ready for synthesis.

read_sdc {top_1_port_pnr.sdc}

SDC for this design define boundary conditions and clocks for the digital block. Some paths with crossing clock domains have been identified as false because those conditions would not exist under normal operation.

report timing -lint

Linting checks prior to synthesis can save a lot of time for a designer by identifying problems in the RTL which will impact synthesis.

if {[llength [all::all_seqs]] > 0} { define_cost_group -name I2C -weight 1 \ -design $DESIGN define_cost_group -name C2O -weight 1 \ -design $DESIGN define_cost_group -name C2C -weight 1 \ -design $DESIGN path_group -from [all::all_seqs] –to \ [all::all_seqs] -group C2C -name C2C path_group -from [all::all_seqs] –to \ [all::all_outs] -group C2O -name C2O path_group -from [all::all_inps] -to \ [all::all_seqs] -group I2C -name I2C

} define_cost_group -name I2O -weight 1 \ -design $DESIGN path_group -from [all::all_inps] -to \ [all::all_outs] -group I2O -name I2O foreach cg [find / -cost_group -null_ok *] {

report timing -cost_group $cg >> \ $_REPORTS_PATH/${DESIGN}_pretim.rpt

}

Path groups and cost groups provide additional control of where RC puts its effort during synthesis. This is largely driven by design stage and knowledge about problem areas in the design.

########################################## #Define SCAN Chain and other rules for DFT ########################################## set_attr dft_connect_scan_data_pins_during_mapping \ loopback /designs/$DESIGN

RC supports a powerful suite of Design For Test (DFT) checks and scan connection. Our RC and Encounter Test teams have worked closely to provide


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set_attr dft_connect_shift_enable_during_mapping \ tie_off /designs/$DESIGN set_attr dft_scan_map_mode tdrc_pass \ /designs/$DESIGN ############################################## #To specify that the different active edges of # scan flip-flops can be mixed along the same # scan chain, set the following attribute: ############################################# set_attr dft_mix_clock_edges_in_scan_chains \ true /designs/$DESIGN define_dft shift_enable -name SCAN_ENABLE \ -active high SCAN_ENABLE -create_port define_dft test_mode -name SCAN_MODE \ -active high SCAN_MODE -create_port define_dft scan_chain -name sc_0 \ -sdi TXD[0] -sdo RXD[0] -shared_output define_dft scan_chain -name sc_1 \ -sdi TXD[1] -sdo RXD[1] -shared_output define_dft scan_chain -name sc_2 \ -sdi TXD[2] -sdo RXD[2] -shared_output define_dft scan_chain -name sc_3 \ -sdi TXD[3] -sdo RXD[3] -shared_output define_dft scan_chain -name sc_4 \ -sdi TXD[4] -sdo RXD[4] -shared_output check_dft_rules fix_dft_violations -async_set -async_reset \ -clock -test_mode SCAN_MODE check_dft_rules

strong interoperability between these products. This design has 5 scan chains which use shared outputs and have crossover clocks. RC will add appropriate logic and connect these scan chains. RC can fix many DFT violations automatically. This can be a huge time savings, especially with legacy designs and improves observability and controllability for DFT.

set_attr lp_insert_clock_gating true / set_attr lp_clock_gating_cell \ [find / -libcell TLATNTSCAX12] /designs/${DESIGN} set_attr lp_clock_gating_test_signal \ SCAN_ENABLE /designs/${DESIGN}

Low power is critical in most designs. RC has many advanced features to address this including the ability to insert clock gating logic automatically.

#*Synthesizing to generic synthesize -to_generic -eff $SYN_EFF #*Synthesizing to gates synthesize -to_mapped -eff $MAP_EFF -no_incr foreach cg [find / -cost_group -null_ok *] { report timing -cost_group $cg > \ $_REPORTS_PATH/${DESIGN}_[basename $cg].rpt } set_compatible_test_clocks -all connect_scan_chains

Synthesis initially maps RTL to generic logic first (non-technology specific Booleans) which is followed by mapping to a target technology library. A full suite of datapath elements called ChipWare is also leveraged for this DSP core. IMPORTANT: RC is unique to the industry in that optimization for timing, area, and power is done concurrently. This provides a result which uses 5-10% less area post physical implementation when compared with our competition.


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#*Incremental Synthesis synthesize -to_mapped -eff $MAP_EFF -incr insert_io_buffers -remove_assign insert_tiehilo_cells

Some post-synthesis clean-up is needed for our schematic based flow. RC will remove the assign statements (hardwired connections) and add TIEHI/TIELO cells to our netlist. NanoEncounter does not require these steps, but it does require a uniquified netlist for timing optimization.

foreach cg [find / -cost_group -null_ok *] { report timing -cost_group $cg > \

$_REPORTS_PATH/${DESIGN}_[basename $cg].rpt } report area > $_REPORTS_PATH/${DESIGN}_area.rpt report gates> $_REPORTS_PATH/${DESIGN}_gates.rpt report dft_chains > \ $_REPORTS_PATH/${DESIGN}_dft_chains.rpt

A series of reports can be generated by RC. In this case, these include reports for timing, area, gates, DFT chains, and clock gating.

report clock_gating > $_REPORTS_PATH/${DESIGN}_ck_gating.rpt write -m > ${_OUTPUTS_PATH}/${DESIGN}_m.hvsyn write_sdc > ${_OUTPUTS_PATH}/${DESIGN}_m.sdc write_scandef > ${_OUTPUTS_PATH}/${DESIGN}_m.scanDef #* write_lec write_lec -revised \ ${_OUTPUTS_PATH}/${DESIGN}_m.hvsyn \ -unreach -dp_info puts "============================" puts "Synthesis Finished ........." date puts "============================" exit

Our synthesis script concludes by exporting the results to the output directory: hierarchical verilog, gate-level SDC, and scanDef. By keeping the netlist hierarchical, we will have more cellViews created in the CDB, but Verilog Import will run much faster due to the schematics which are easier to place and route. The scanDef file will be inputted to NanoEncounter for scan reordering. A Conformal script is also generated for running logical equivalency checking. The gate-level netlist produced by RC was previously confirmed to match the RTL.


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Floorplanning Icons

Pull-Down Menus

Toolbar Icons

Auto Query of Objects

Design Views

Design Display Area

Display colors

Introduction to Encounter In this section… you will launch and explore the Encounter GUI. This will be the cockpit for the physical implementation of the digital block in our design. All commands are tcl based and captured in the encounter.cmd file. Encounter may also be run without the GUI by using encounter -nogui Actions:

1) Use the alias cdne to change the directory to: /export/home/cic/amskit/adpi_flow_workshop/ether_wo rk/ne

2) Start NanoEncounter with a VDI license by using: encounter –vdi

The xterm window used to launch Encounter will serve as the command line and log window.

3) Familiarize yourself with the Encounter GUI by viewing the functions on the pull-down menus. Move the mouse over the encounter menu widgets located immediately under the Encounter GUI. These are shortcuts to the Encounter menu items. The function of the short cut is highlighted when the mouse is over the tool bar widget.


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4) There are (3) modes for viewing a design. The Design Views icons appear on the upper-right of the Encounter GUI. We will use each of these views as we progress through the Silicon Virtual Prototyping flow.

5) Online documentation and Help is available through several methods: a. Click on the Help button in the upper right corner of the Encounter

window to view the Encounter documentation in an internet browser. b. Click on the Help button on a form to view the related help. c. To see syntax information about a specific Encounter command, type the

following command in the Encounter console: help command_name d. To see the entire list of Encounter commands and their syntax, type the

following command in the Encounter console: help. The information is written to the encounter.log file.

e. To see the complete information about an Encounter command, type the following command in the Encounter console: man command_name

6) Design => Preferences => Binding Key form displays the bindkey settings

which may also be user customized. Alternatively, bindkeys can be displayed by typing “b”. The default binding keys are consistent with Cadence Virtuoso™ products.

Design Import and Loading DEFs In this section… you will use a previously saved configuration file to import the design. The config file has information about library and design files needed for a timing closure flow using NanoEncounter. You will also load the DEF from Virtuoso Preview which contains physical floorplan information and a ScanDEF from RTL Compiler which contains scan ordering information. Actions:

Floor Plan view

Connections appear as fly lines when an object is selected. This view is used for moving or viewing floorplan objects such as guides and fences.

Amoeba view

Routed interconnections can be displayed by double-clicking a module or block. This view is used mainly after placement to see the amoeba shapes created by the module boundaries in the placement.

Physical view

The actual routed interconnect for specific nets can be viewed by zooming to a small area after Trial Route is completed. This view is used for detailed implementation and analysis after placement and routing. Use the Floor Plan view until after the design has been placed.


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1) Open the Design Import form by selecting Design => Design Import… or by

clicking on the Design Import icon which is just below the Design pull down.

2) Populate the form using the Load button at the bottom of the Design Import

Form. Navigate the file manager to find the file named : scripts/top_1_port_pnr.conf

3) Review the form contents and the tabs for Design, Core Spec Defaults, Timing

and Power. File locations for netlist, libraries, technology data, and design constraints are captured along with many defaults.

4) Click OK. When Design Import is complete, the Encounter GUI will report the design status to be In Memory .

5) Load the DEF created by Virtuoso Preview by selecting Design => Load =>

DEF …

6) Navigate the file manager up to the ne directory and select the file named: top_1_port_pnr.def

7) Click Open

8) The scanDef created by RTL Compiler uses DEF format to describe the scan

connections created for automatic test pattern generation (ATPG). After placement, the scan chains may be reorder to reduce routing congestion.

Select Design => Load => DEF … Navigate the file manager up to the ether_work directory and down to the rc/outputs directory. Change the Files of Type: field to All Files (*) to select the file named: top_1_port_pnr_m.scanDef . Click Open.

9) Select the Floorplan View icon to show the floorplan view in the Encounter user interface. Use the floorplan view until the design has been placed.

10) Use bindkey “Z” to zoom out to view more of the design.

♦ Pink objects on the left side of the core area are top-level, hierarchical instances represented as module guides. These can be grouped or ungrouped and used for constraining placement.

♦ Fly-lines are displayed when an object is selected and Net visibility is turned on in All Color/General Color Control – (thin button under All Colors.)


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Silicon Virtual Prototyping In this section… you will learn how to explore the design using the GUI, run a prototyping flow, and do some what-if analysis on the floorplan. Silicon Virtual Prototyping uses fast engines for routing and extraction which enable early analysis about how the floorplan is effecting routing congestion and timing.

POWER PLANNING In this section… you will run a tcl script which was captured using menus found under Floorplan => Custom Power Planning. The tcl script also makes use of Encounter database access commands to manipulate the row definitions in the floorplan for a rectilinear block. In the upcoming Encounter 5.2 release, these row based manipulations will no longer be needed. Actions:

1) The terminal window used to launch encounter acts as a shell where tcl commands and scripts may be launched. Return to the encounter shell and type: source scripts/power.tcl. This script will also export the LEF which contains the power routes for use with VCAR.

2) In the Floorplan View, the power routing is visible. Select All Colors to

display the color and pattern assignments for each object type. You can change colors and patterns by clicking on the colored square next to an object and then selecting a new color and pattern from the selections.

PLACEMENT In this section… you will run placeDesign, a super command which makes use of timing and scan information. When used with medium or high effort, the result is compliant with routing requirements. The resulting placement will be analyzed with the Amoeba view. In some designs, this analysis could lead to additional floorplanning to address congestion or timing issues. The guides would be annotated to the floorplan using Floorplan => Generate FP Guide… The placeDesign command makes use of amoebaPlace, a quadratic placement algorithm which also leverages the logical hierarchy defined in the netlist. Actions:

3) Open the placement form with Place => Place… Select all (4) of the Options listed: Run Timing Driven Placement, Reorder Scan Connection, Include Pre-Place Optimization, and Include In-Place Optimization. Click OK .

4) According to the Encounter GUI, what is the design status? _______________


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5) Select the Amoeba View icon to view how the logical hierarchy has been placed. There are (2) major logical blocks outlined: i_dsp_top and i_top_digital.

6) Select module i_dsp_top . Use bindkey “G” (ungroup) to graphically move

down the hierarchy. Deselect i_dsp_top with <LMB> outside of the block boundary. Note a level of hierarchy below i_dsp_top is now displayed.

Successively using “G” will visually flatten another layer of logical hierarchy. Moving back up the hierarchy can be done with“g”. This can also be done with

the Hierarchy Down and Up icons:

ROUTING In this section… you will run trialRoute, a fast, grid-based router used for prototyping. TrialRoute predicts routing congestion and routing layer assignments, but does not deliver a DRC clean route required for manufacturing. In a prototyping flow, trialRoute may also be used to determine how many layers of routing are required to successfully route a block or chip. Actions:

7) Open the trialRoute form with Route => TrialRoute… Change the max. route layer from 9 to 3. Click OK


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8) To review the congestion, select All Colors. On the bottom of the Color Preferences form, select Load Pref. Navigate the file browser to select the file scripts/cong.pref.tcl and click Open. Back on the Color Preferences form, click Update Display and return to the Encounter GUI. Note the thermal map which looks similar to the figure below:

9) Return to the Color Preferences form and select Use Default to return to the default settings.

10) Another method for reviewing congestion is to review the encounter.log file

displayed in the Encounter console window. Switch to the Encounter console window and scroll up to find Phase 1f, the last pass of trialRoute. Overflow numbers in excess of 0.5% are considered unroutable for 3 layer metal designs. The Congestion distribution shows how congestion is distributed across the gcells.

11) For the remainder of the workshop, we want all applications to use a maximum

of 6 layers of metal for routing. While in the Encounter console window and type: setMaxRouteLayer 6

TIMING In this section… you will run timeDesign. TimeDesign runs trialRoute, extraction and timing analysis on placed design. The results will be analyzed with Timing Debug tool. Actions:

12) Open the Timing Analysis form with Timing => Timing Analysis… Use the form defaults. Click OK . This will cause timeDesign –preCts to be run.


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13) Open the Timing Debug interface with Timing => Debug Timing. Specify

the Violation File by clicking on the icon located in the lower right of the Encounter GUI. Navigate down to the timingReports directory and select top_1_port_pnr_preCTS_all.tarpt . Click Open.

14) Click Display.

What is the timing slack for the worst case failing path? _________

15) Close the Timing Debug GUI with the icon.

Global Physical Synthesis In this section… you will review the capabilities of Global Physical Synthesis. During placement, we ran In-Place Optimization, another name for Global Physical Synthesis. GPS is a series of optimizations which include buffer/inverter pair deletion, resizing, buffering, critical path re-synthesis, and fixed timing design rule violations. This closed timing prior to running CTS. We will continue to monitor our timing throughout the remainder of the flow and run GPS if and when it needed.


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Many of today’s mixed signal designs are challenged with meeting system timing requirements. Encounter Global Physical Synthesis uses a wire-centric methodology which provides timing optimization at multiple stages of physical implementation. TrialRoute, a fast engine for routing, and FE extraction provide excellent correlation with sign-off engines. Results of this analysis enable GPS to make basic and complex netlist optimizations achieve setup and hold times. This optimization process is done before and after clock tree synthesis and again after routing with NanoRoute. When combined with Silicon Virtual Prototyping, Global Physical Synthesis provides the results required for high-performance designs. Low-power optimization techniques such as clock gating are addressed in synthesis and with clock tree synthesis. Libraries enabled with multi-VT to help address timing vs. power trade-offs may be used with NanoEncounter. The challenges of managing voltage islands are also automated.

Clock Tree Synthesis In this section… you will run clockDesign, a new super command which generates the clock tree synthesis constraints from the SDC and runs CTS. Timing for both setup and hold will be reviewed and closed using GPS. Actions:

1) Return to the Encounter console and type clockDesign . It’s that easy!

While CTS is running, review the clock tree specification written to the working directory. It is called top_1_port_pnr.ctstch. How many clocks are specified? __________

What is the setup timing at the conclusion of clockDesign? WNS ________ TNS _________ Violating Paths __________

2) If there are any timing violations, then run Timing => Optimization … Since

CTS has already been run, select Post-Cts, and click OK on the Timing Optimization form.

What is the setup timing at the conclusion of Timing Optimization? WNS ________ TNS _________ Violating Paths __________


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Detailed routing with NanoRoute In this section… you will run NanoRoute, a global and detailed, graph-based router. For designs which are more than 3 layers of metal, NanoRoute is recommended. Use WRoute when routing designs with 3 layers of metal or less. The router selection will become transparent to the user in the next release. NanoRoute concurrently optimizes for congestion, timing, and signal integrity which results in less time being spent on analysis and repair during the final design stages. Additional net constraints may also be applied such as layer restrictions, weight, shielding, non-default rules, and pattern style. In this design, we will reserve additional routing tracks on either side of the clock nets. Actions:

1) Open the NanoRoute/Attributes for with Route => NanoRoute/Attribute… Select Net Type(s): and Clock Nets. Change Spacing from ASIS to 1. Click OK . This will add an empty track around all clock nets.

2) Open the NanoRoute form with Route => NanoRoute…

b. Select Insert Diodes, specify Diode Cell Name to be ANTENNA c. Select Timing Driven d. Select SI Driven e. Click OK

While NanoRoute runs, take a 5 minute break

3) Use Timing => Timing Analysis… with Post-Route selected to determine

What is the setup timing at the conclusion of NanoRoute? WNS ________ TNS _________ Violating Paths __________

4) Determine if timing is closed using the tcl command timeDesign –postRoute.

If timing is not closed, then run the tcl command optDesign –postRoute. 5) Save your design using Design => Save Design… Use the form defaults and

click on Save.


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Block Finishing In this section… you will complete the steps needed to finish the block layout for tapeout.

Add filler cells In this section… you will add filler cells. The filler cells in the gsclib090 library are used to bridge the Nwell gaps between standard cell instances. If filler cells contain metal shapes, they need to be added prior to running detailed routing. Actions:

1) Open Place => Filler => Add Filler… Click on Select and Add all 7 filler cells listed to the Selectable Cells List. Close the Select Filler Cells form.

2) Click OK on the Add Filler form.

Add metal fill In this section… you will add metal fill using Encounter. Encounter is aware of timing and reduces intra-layer cross coupling. For designs using LEF 5.6, MACRO DENSITY is useful for managing metal fill over large blocks. While metal fill may also be added with Assura, the Encounter capabilities are very useful for digital designs which are timing critical. Actions:

3) Open Route => Metal Fill => Setup… The default information is provided in the LEF; however values may be overwritten with this form. Click Cancel.

4) Open Route => Metal Fill => Add… Deselect layers M7, M8, and M9 since

our design only routed with 6 metal layers. Click OK.

5) Click OK on the Add Metal Fill form.

Run verifyConnectivity, verifyGeometry, and verifyProcessAntenna In this section… you will run the Encounter equivalent to DRC, LVS, and antenna checks. These checks are based upon LEF so they are not as accurate as using GDSII; however they run much faster. If the technology LEF matches the DRC rules and the macro LEF (abstract) matches the layout for all referenced macros, the verify commands are an excellent indication of what will be seen with Assura. Actions:

6) Open Verify => Verify Connectivity. This is the Encounter version of LVS. Select Connectivity Loop and click Ok. Were there any violations reported? ________


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7) Open Verify => Verify Geometry. This is the Encounter version of DRC. Use the form defaults and click Ok. Were there any violations reported? _________

8) Open Verify => Verify Process Antenna. Use the form defaults and click Ok.

In addition to a report, this step creates a block LEF which includes antenna information. This LEF is used in a hierarchical flow.

Export Design In this section… you will run a tcl script to save off all of the files needed for Virtuoso, Assura, and AMS Simulation. In the future, OA will be used to transfer the DEF information. We will not be using Encounter to export GDSII since that data already resides in Virtuoso and can be re-mastered with Virtuoso. Note: Virtuoso 5.1.41 supports LEF and DEF version 5.5. By default, NanoEncounter will write LEF and DEF version 5.6. The Encounter variable dbgLefDefOutVersion is used to specify version 5.5 in the script below. Actions:

1) In the Encounter command window, type source scripts/VDI_export.tcl.The script saves hierarchical verilog, LEF 5.5, DEF 5.5, SPEF, and SDF and looks like:

set dbgLefDefOutVersion 5.5 set design top_1_port_pnr set step postRoute saveDesign $step.enc -def exec mv $design.lef $step.enc.dat/$design.lef exec mv $design.antenna.lef $step.enc.dat/$design.a ntenna.lef extractRC rcOut -spef $step.enc.dat/$design.spef.gz

delayCal -sdf $step.enc.dat/$design.sdf


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Importing Encounter Digital Block results into Virtuoso In this section… you will import the hierarchical verilog, LEF 5.5, and DEF 5.5 back into Virtuoso. Once the DEF is imported, the abstract views will be replaced with layout views. Actions:

1) Use the alias cdcdb to return the current directory to: /export/home/cic/amskit/adpi_flow_workshop/ether_cd b

2) Start icfb and open ether_VDI/ top_module1A/ ADPIpinOpt. 3) Although file import may appear complex, it can be captured with (8)

parameters. The “F12” bindkey will pop-up the following form:

4) This form replaces File => Import => Verilog…, File => Import => DEF…,

File => Import => LEF…, and Floorplan => Replace View… It assumes the Verilog, LEF, and DEF are all in the Encounter Saved Directory.


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Module 3: Block power/signal routing


What is covered: � Autoroute block power nets � Interactively river route busses � Matched length and shielded nets � Autoroute signal nets


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START SOFTWARE Please, OMIT this part if you have already started icfb. Actions:


� cd $HOME/adpi_flow_workshop � source setup.csh Use the alias startlic to start the license. Only do this if the license was not previously started. � startlic


Autoroute block power nets In this section… you will use Virtuoso Chip Assembly Router (VCAR) to route the top-level power nets. VCAR is a gridless, shape-based routing environment. It is a proven custom routing technology that has been used in production for the last 10 years. It contains interactive placement, interactive routing, global routing and detail routing using robust analog-centric constraints and rules. It uses a rip up and retry routing algorithm and is LVS and DRC correct by construction.


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START VCAR SESSION Actions:

1) From the Library Manager , open the ether_VDI/ top_module1A/ ADPItoVCAR cellView. This cellView has abstract views swapped in for the newly hardened soft blocks.

2) Switch the toolbar using Tools

=> Layout.

3) Choose Routing => Export to Router. The form should be pre-populated as shown to the right:

4) Click OK to display the VCAR

GUI.


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AUTOROUTING POWER NETS In this section… you will run VCAR with scripts called “do” files which can be captured from session logs called “did” files or by using Edit => Rules Did File... This portion of the workshop will rely on do files to run commands and set routing variables and net and class constraints. . Actions:

5) In the VCAR Command: window, specify: do ../ether_work/vcar/power.do and press Enter.

The power.do file includes setup info and rules for net widths and tapering. These could have been defined with the GUI, but were captured from previous scripts and “did” files. The widths defined are based upon previously successful routes, but could be changed if a tool such as VoltageStorm determined there was an IR drop or electromigration problem. The script makes use of break points. When a break point is reached, a Continue button will appear where the Idle button is displayed on the figure


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above. It is used to move the script forward after a break point specified in the do file.

6) The first break point shows a report of wire widths for power and ground nets

are specified in the power.do file. Review the widths which have been specified and then Close the report window.

7) Click the Continue button. The power routing is complete. The 1st zoomed in area shows the connections to the Bias_port pins. Recall that these pins had been moved to align with the pins in the top_1_port_receive block during pin optimization.

8) Click the Continue button.

The 2nd zoomed in area shows the connections to the top_1_port_pnr pins. Notice the O over the pins indicates the wire has been protected or fixed. To further inspect the connections, use the RMB to zoom in, “Z” to zoom out, and “f” to fit the block in the GUI.

9) Click the Measure Mode icon. Click on one of the power wires in the zoom area. The Measure window displays and gives you the net name and width.

What is the net name? ________ How wide is the wire? __________ Is the width measured the same as what was specified in the power.do file? ___


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Interactively river route busses In this section… you will interactively route a bus. Actions:

1) In the VCAR Command: window, specify: do ../ether_work/vcar/buss.do and press Enter.

2) There are (2) busses selected. Use the RMB to zoom in to the area circled in

yellow in the figure on the left below.

3) Use the LMB to select the highlighted pins as shown in the figure on the right below.

4) Drag the cursor to the left about half way into the channel as shown in the

figure on the left below. Click the LMB and then drag the cursor down. Zoom out until you can see where the buss will make another jog to the left as shown in the figure on the top right below.


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5) To change layers while making the left turn, click the LMB to start the turn. Hit the spacebar. The Switch to Layer form shown at the right will be displayed. From layer Metal2, you can switch to Metal1 or to Metal3. The buss will now appear as shown above on the lower left.

6) Move the buss to the left, and click LMB when the mouse is close

to the endpoints. See figure on the lower left above.

7) Click LMB and RMB and a pop-up with Finish Route will appear. Finish Route automatically calls the autorouter to finish the bus for you.

8) Click the Continue button to protect the buss route.


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Matched length and shielded nets In this section… you will route a buss as matched length and observe the serpentine routing. The selected buss had poorly aligned pins and required the route lengths to match. This example will be followed with a net which will be routed with shielding between 2 of its 3 connections. Actions:

1) In the VCAR Command: window, specify: do ../ether_work/vcar/match_shield.do and press Enter.

2) “flight lines” on the selected buss are

displayed. Click the Continue button.

3) The Rules Report shows the diff_match rules applied to the selected buss. Review the report and Close the window. When the route is complete, note the serpentine routing used to match the wire lengths shown in the figure to the right.

4) Click the Continue button. The

Rules Report shows the from_to rules applied to the selected net. This is a 3 pin net, but the rule requires only one segment of the net to be shielded. Review the report and Close the window.

5) The 1st zoom window shows the start point of the from_to net. Click the

Continue button to view the 2nd zoom window. The from_to net ends and continues on to the 3rd point without shielding the net.


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Autoroute signal nets In this section… you will finish auto-routing the block using the global and detail routers. Actions:

1) Choose Autoroute => Global Route => Local Layer Direction.

2) Select the Layer Panel button and click OK .

3) In the VCAR Command: window, type groute 3;route 4;clean 2 and press Enter. Wait for the routing to finish. The Pause icon will change into an Idle when the routing is complete 100%.

Note: If you get pop-ups warning about blocked pins, click Yes to proceed with detailed routing. How many Unconnects: are reported? _______ How many Conflicts: are reported? _________

4) Review the conflicts with the View => Visit… menu. On the Conflicts tab,

click on Length. One of the diff_match nets did not meet our length specification after detailed routing.

Saving and Importing the Routed Design In this section… you will save the VCAR session file and import the routing back into Virtuoso. Actions:

1) In the VCAR GUI, Choose File => Quit. Click the Save and Quit button to Exit. If the top_module1A.ses file exists, click Yes to replace it.

2) Returning to icfb and the ether_VDI/ top_module1A/ ADPItoVCAR

window, import the routed database using Routing => Import from Router… Change the view from ADPItoVCAR to routed. This makes it easier to recognize the design status for this block in the Library Manager .

3) Close the ether_VDI/ top_module1A/ ADPItoVCAR window with Window

=> Close or the “ctrl w ” bindkey.


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Module 4: Physical Verification


What is covered: � Run Assura DRC: Design Rule Checking � Interactive layout edits to repair DRCs � Run Assura LVS: layout vs. schematic verification


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Run Assura DRC: Design Rule Checking In this section…you will run Design Rule Checks (DRC) on the cell view you routed with VCAR to check and to fix any spacing and construction violations that may have been introduced during routing. Checking is performed hierarchically, as block design may just be starting. As blocks complete, you can verify inside the blocks and manage the hierarchical stopping points as the full design continues to evolve. Actions:

1) From the Library Manager , open the ether_VDI/ top_module1B/ routed cellView. The lower level cells are abstract views -- only metal obstructions and pins are defined.

2) Switch the toolbar by using Tools => Layout. Click on the Assura menu to

examine the choices: ♦ Open run… – Used when you have a completed DRC or LVS run to open

and use ♦ Technology… – Defines Assura technology directory choices. Your

starting directory should have a file named assura_tech.lib in which you defined technology directory choices. DRC is the choice used in this section. Even if you don’t define an Assura Technology, you can still fill out the Run DRC/LVS forms using explicit paths to the required files

♦ Rule Sets… – Builds different rule sets in the same technology directory. ♦ Setup – Sets up DRC/LVS/RCX run options and remote job submission ♦ Run DRC… – Runs a DRC (Design Rule Check) verification


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♦ Run altPSM… – Runs a Phase Shift Mask (PSM) run to create and correct PSM features. Has the same function as Run DRC….

♦ Run LVS… – Runs an LVS (Layout vs. Schematic) comparison ♦ Open ELW – Open the Error Layer Window. Opening or running a new

DRC enables this choice ♦ Open VLW – Open the Verification Layer Window. The Assura run

generates these layers when it runs the rule file. The layers are not part of your original design database. These are useful when developing and debugging rule files. If the VLW is closed, this selection opens and iconifies the window. If the VLW is iconified or hidden behind other windows, this selection brings it to the front.

3) Choose Assura => Run

DRC. The cell information is already filled out.

4) At the top of the Run

Assura DRC form, click on Load State. Select the state called ether_top. The Assura DRC form should like the figure to the right. Click OK.

5) Save all of the open

cellViews. If an existing run exists, select Yes to overwrite the files. A Progress form displays. For longer runs, you may want to view the log as the run progresses.

6) When the DRC run completes, you

can view the results. Don’t be fooled by the run completing SUCCESSFULLY! This only means it completed and is not an indication of DRC violations. Click Yes.


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7) An Error Layer Window is displayed which summarizes all DRC violations found in the design. Step through the violations in the by selecting a violation

with icons and then use icons to increment through the list of errors in the Error Layer Window.

a. The 1st violation, psubstrate_StampErrorFlow, occurs because our routed

view does not contain psubstrate contacts. b. The 2nd and 3rd violations for MetalX area must be >= 0.8 um are due to

missing connections on pins which were not connected in the schematic. These will be resolved when the abstract views are remastered with layout views. Further investigation should be done with the schematic or with LVS to conclude these missed connections are intentional.

c. The following results are typical for this design and are related to the

complex via rules for this technology. These violations could potentially be addressed by modifying the vcar do files or by making manual DRC changes. In the workshop, you will make the layout edits and rerun DRC.

d. An example of the remaining violations, MetalX must connect to MetalY

with >= 4 ViaX, is shown in the figure on the left on the next page. The fix is to select the via and to replace it with a 2x2 via in the same location. In some cases, it may be necessary to move the via to avoid a short created with the larger via. See the figure on the right on the next page.

a. Switch the tool bar to Tools => Layout b. Select the offending via and query it with <q>. On the Edit Instance

Properties form, change the cellName from VIAx_2CUT_H to VIAx_2X2CUT and change the viewName from symbolic to layout. Click <OK>.

c. Move the selected via down so that it is enclosed by the pin using <m>.

d. Stretch the connecting wire by selecting <s> and shifting it to the bottom edge of the via.


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e. Select the Metal3 path that is covered by the DRC rectangle and delete it.

8) Fix all remaining violations using this via replacement technique. 9) In the layout window, LMB choose Assura => Close Run to exit the DRC

session. 10) Rerun DRC with Assura => Run DRC… Click OK . Save the listed cellViews

by clicking OK . Click OK on the Overwrite existing data? form. This time there should only be 2 types of DRC violations: psubstrate_StampErrorFloat and MetalX area must be >= 0.8 um. As previously noted, these errors will be resolved when DRC is run with abstract views remastered with layout views.


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Run Assura LVS: layout vs. schematic verification In this section… you will re-master all the sub-block abstracts with layout views and use interactive Assura LVS to compare the cellView routed using VCAR with the schematics.

REMASTER INSTANCES Actions:

1) Using the ether_VDI/ top_module1B/ routed cellView, choose Design => Save As to copy the cellView to ether_VDI/ top_module1B/ layout. Use “ctrl w ” to close the ether_VDI/ top_module1B/ routed cellView.

2) From the Library Manager , open ether_VDI/ top_module1B/ layout.

3) Select Tools => Layout. Choose Design => Remaster Instances to swap out

all the block abstracts for the block layout views. Type abstract in the ViewName under Search For and layout in the ViewName under Update To. Click OK

4) Click “F” in the layout window to display all levels. Wait a few seconds for

the cellView to update.

RUN ASSURA LVS Actions:

1) In the layout window, choose Assura => Run LVS. The cell information is already filled out.

2) At the top of the Run Assura LVS form, click on Load State. Select the choice

ether_bbox. Then click OK . This sets the technology file to be used and selects black box LVS for top level layout versus schematic check. LVS will only check down to the ports of the blocks because of the ?blackBoxCell list provided in the avParameters section.


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3) Click OK to run the LVS job. A Progress form like the one shown to the left

and below is displayed.

4) A message box like the one below informs you when the LVS job is complete.


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5) The Error Layer Window is displayed because the psubstrate and nwell connections are inside the black boxes which were not extracted in this run. These errors are resolved when running a full LVS extraction.

6) Click Yes to view the results of this run .The LVS debug form also states that

the Schematic and Layout match. If LVS errors exist, a list of cell mismatches displays on the left side.

7) Click Extract and a message states that “No extraction warnings nor errors were detected”.

8) Choose File => Quit Debug Environment


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Module 5: Parasitic Extraction & Simulation


What is covered: � Assura RCX: Extract top level routing parasitics � Back-annotate RCX parasitics and probe schematic


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Assura RCX: Extract top level routing parasitics In this section… you will run a full parasitic resistance and capacitance extraction and create an av_extracted view to be used for parasitic analysis. Assura RCX analysis tools will be used to investigate the parasitics. Top-level routing parasitics can be introduced into simulation and synthesis very early in a top-down design flow. Early detection of excessive parasitics may need to be addressed with a routing, floor-planning, schematic, or perhaps even an architecture changes. Although this workshop flow had completed block layouts, the work we have done with soft blocks shows how much physical implementation can be done without lower level blocks. The AMS Top-Level Simulation Workshop covers simulation with parasitics in greater detail. Actions:

1) From the Library Manager , open the ether_VDI/ top_module1B/ layout cellView.

2) Open up the LVS run with Assura => Open Run. Click OK to open an

existing clean LVS run from the last section. You will need to close the Error Layer Window form with File => Close ELW.


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3) The av_extracted view is

used to store a representation of the circuit and layout parasitics. You can then use this view to analyze the parasitics and, ultimately, to run a simulation. In the layout window, click Assura => Run RCX.

4) At the top of the form, click Load

State. Pick ether_bbox as the state and click OK on the Load State form. This populates the Assura Parasitic Extraction Run Form. Notice there are 6 tabs across the top. In the output section of the setup tab, you generate an Extracted View. This is a representation of the top cell and is named, as the default.


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5) Click the Extraction tab. RC is the extraction mode, cap extraction will be type Coupled for all block nets and will use GND as a reference node. Make sure the Extraction Mode is set to Full Chip All Nets. It should appear the same as the one to the right.

6) Click on the Netlisting tab. We

are using the standard parasitics capacitor and resistor model. The options for parasitic cap and parasitic res are set to “include as comment”. Otherwise, RCX will add process-based res and cap model names such as “cmodel” and “rmodel” in database of the av_extracted view. The form should appear like the one in the lower right.

7) Click OK to run the RCX job. A

Progress form will be displayed like the one below and like those seen with other Assura steps.

8) Click the Watch Log File button while RCX is

running. When RCX finishes, the end of the log file contains a summary of parasitic devices extracted Use File => Close Window when you finish looking at the log file.

9) The Assura RCX Run form

displays when the job completes successfully. Close the Assura RCX Run form. RCX successfully output an av_extracted view.

10) In the layout window, choose

Assura => Close Run. Choose Window => Close to close the layout window


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Back-annotate RCX parasitics In this section… you will use the av_extracted view, generated with Assura RCX in the last section, to back-annotate the extracted parasitics into the schematic view. Actions:

1) From the Library Manager , open the ether_VDI/ top_module1B/ av_extracted cellView. Note that only the top-level nets were extracted. This is because we used the black box LVS run to limit RCX extraction.

2) From the Library Manager , open the ether_VDI/ top_module1B/ schematic

cellView in edit mode.

3) In the av_extracted window, switch the toolbar by using Tools =>Parasitics.

4) In the av_extracted view, click Parasitics => Setup. The Setup Parasitics form comes up. This form shows the Extracted Cellview and the Schematic Cellview that will be used. Click OK.

5) In the av_extracted view, click

Parasitics => Options. Select Backannotate values R and C from the av_extracted view to the schematic view. Click OK.

6) In the schematic view, switch the

toolbar by using Tools =>Parasitics. Click Parasitics => Show Parasitics to see the backannotation as shown in the figure to the right.

7) In the schematic view, click Parasitics

=> Report Parasitics => All Nets. Review the full list of parasitics for the design. Which signal net has the largest total capacitance? ____________

8) In the schematic view, use Edit =>

Search => Find… to locate the net identified in step 7). See the example form below:


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9) In the schematic view, use Parasitics => Report Parasitics => Net for the net

identified in step 7). Step 8) should have zoomed close to the desired net to be selected so that it can be selected. Select the net after clicking OK on the form.

10) Using the Pararasitics for Net Report generated in step 9), you can determine

parasitic contributions from coupled nets and resistance. The Headers may be used to sort data. Select a device as shown in the example below and then look at the av_extracted window to see the corresponding device.

11) To learn more about how to use the av_extracted view in simulation, please attend the AMS Top-Level Simulation Flow workshop.

This concludes today’s session of the Analog Driven Physical Implementation Workshop.

Thank you for your participation.

AMS Methodology Kit Version 5.1.0picture.iczhiku.com/resource/eetop/whiFtzjJRpDTeXNb.pdf · 2019. 11. 11. · Run Assura DRC: Design Rule Checking _____ 54 Run Assura LVS: layout

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