Alvise Bagolini a , Maurizio Boscardin a , Gian-Franco Dalla Betta b , Gabriele Giacomini a , Francesca Mattedi a , Marco Povoli b , Nicola Zorzi a a Fondazione Bruno Kessler (FBK-CMM) Italy b INFN and University of Trento, Italy Production of 3D silicon pixel sensors at FBK for the ATLAS IBL
Production of 3D silicon pixel sensors at FBK for the ATLAS IBL. Alvise Bagolini a , Maurizio Boscardin a , Gian -Franco Dalla Betta b , Gabriele Giacomini a , Francesca Mattedi a , Marco Povoli b , Nicola Zorzi a. a Fondazione Bruno Kessler (FBK-CMM) Italy - PowerPoint PPT Presentation
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Alvise Bagolinia, Maurizio Boscardin a, Gian-Franco Dalla Bettab, Gabriele Giacominia, Francesca Mattedia, Marco Povolib, Nicola Zorzia
a Fondazione Bruno Kessler (FBK-CMM) Italyb INFN and University of Trento, Italy
Production of 3D silicon pixel sensors at FBK for the ATLAS IBL
3D silicon pixel sensor productionThe layout has been developed in the in the framework of the ATLAS 3D Sensor Collaboration
• FE-I4 (8x)
• FE-I3 (9x)
• CMS (3x)
• test structures
3D_DDTC with passing-through columns technology was used for the first production oriented to the ATLAS insertable B-Layer
dead area of 200 mm
Ohmic Side
Junction side
50 µm
125 µm
FE-I4 sensor 80 x 336 pixels
Layout details of a FE_I4 sensor
• Column depth equal to the wafer thickness, etched from both sides
• Full double side process• Surface isolation with p-spray
on both sides• No support wafer• Columns (~12 µm diam.) are
“empty”, doped by thermal diffusion and passivated by SiO2
• Edge protection in order to improve the mechanical yield
t
p+ col.
n+ col.
p-spray
edge protection
p-sub
3D-DTC with passing through columns
• Optimization of DRIE recipe for holes with higher aspect ratio in order to improve the uniformity of the etch rate throughout the process.
• Optimization of edge protection in order to • increase the mechanical yield after DRIE etching • reduce the wafer bowing and consequently the leakage
current
Main technological aspects
Optimize DRIE recipe for holes with higher aspect ratio
Etch stop for DRIE etching
≈ 12 µm
≈ 10 µm
≈ 234 µm≈ 11 µm
≈ 5 µm
208 µm
Optimize edge protectionMechanical fragility of wafers manly due to a cracks on the wafer edge caused by D-RIE etch step:
Need a special edge protection during DRIE etching (electrostatic clamping) to prevent the creation of cracks that could cause the breakage during the processing.
Need a special care during processing
Mechanical yield with the optimized edge protection: