-
Taking, S., MacFarlane, D. and Wasige, E. (2011) AlN/GaN-based
MOS-HEMT technology: processing and device results. Active and
Passive Electronic Components, 2011 (821305). ISSN 0882-7516.
http://eprints.gla.ac.uk/54418 Deposited on: 02 August 2011
Enlighten – Research publications by members of the University
of Glasgow http://eprints.gla.ac.uk
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Hindawi Publishing CorporationActive and Passive Electronic
ComponentsVolume 2011, Article ID 821305, 7
pagesdoi:10.1155/2011/821305
Research Article
AlN/GaN-Based MOS-HEMT Technology:Processing and Device
Results
S. Taking, D. MacFarlane, and E. Wasige
High Frequency Electronics Group, School of Engineering,
University of Glasgow, Glasgow G12 8LT, UK
Correspondence should be addressed to S. Taking,
[email protected]
Received 1 October 2010; Accepted 6 December 2010
Academic Editor: David Moran
Copyright © 2011 S. Taking et al. This is an open access article
distributed under the Creative Commons Attribution License,which
permits unrestricted use, distribution, and reproduction in any
medium, provided the original work is properly cited.
Process development of AlN/GaN MOS-HEMTs is presented, along
with issues and problems concerning the fabrication processes.The
developed technology uses thermally grown Al2O3 as a gate
dielectric and surface passivation for devices.
Significantimprovement in device performance was observed using the
following techniques: (1) Ohmic contact optimisation using Al
wetetch prior to Ohmic metal deposition and (2) mesa sidewall
passivation. DC and RF performance of the fabricated devices will
bepresented and discussed in this paper.
1. Introduction
The search for improved high power and high frequencyperformance
has called attention to the most recent devel-opment in aluminium
nitride/gallium nitride- (AlN/GaN-)based high electron mobility
transistors (HEMTs) whichtarget future microwave power devices. Key
properties ofthis material system are high 2DEG sheet carrier
concen-tration at the heterojunction interface, high carrier
electronvelocity, and large electric breakdown field, and so
superiorperformance compared to conventional AlGaN/GaN devicescould
be achieved. With improvements in material growthand processing
techniques, record performances made in thismaterial system include
2DEG sheet carrier concentrationover 3 × 1013 cm−2 with very low
sheet resistance, Rsh,
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2 Active and Passive Electronic Components
Ohmic Ohmic
Contactto 2 DEG
1 nm GaN3 nm AIN
3.8 μm GaN 2 DEG
Figure 1: Optimised TLM processing summary for unprotectedand
unpassivated AlN/GaN HEMT samples. Processing includes (a)sample
cleaning with acetone, isopropanol, and deionised water,
(b)deoxidation, (c) Ohmic metallisation, (d) Ohmic annealing, and
(e)TLM measurements.
OhmicAl2O3 Al2O3 Al2O3
Ohmic
Contactto 2 DEG
1 nm GaN3 nm AIN
3.8 μm GaN 2 DEG
Figure 2: Optimised TLM processing summary for protected
andpassivated AlN/GaN MOS-HEMT samples. Processing includes(a)
sample cleaning with only deionised water and deoxidation,(b) 2 nm
Al deposition, (c) etching Al from Ohmic contact regions,(d)
thermal oxidation of Al, (e) Ohmic metallisation, (f)
Ohmicannealing, and (g) TLM measurements.
transconductance, GMAX, which results in the enhancementof the
current gain cutoff frequency, fT , as well as maximumfrequency of
oscillation, fMAX, of the devices. For thesereasons, Ohmic contact
optimisation processing for HEMTand MOS-HEMT in the AlN/GaN
material systems is crucialto achieving good device performance.
Details of the Ohmiccontact process optimisation were reported in
[9] and aresummarised here.
Ohmic contacts on both protected (with 2 nm evapo-rated Al which
is later oxidised to form Al2O3) and unpro-tected (as grown)
AlN/GaN samples were fabricated andcharacterised. Figure 1 shows
the optimised transmissionline method (TLM) processing summary for
unprotectedand unpassivated AlN/GaN HEMT samples while Figure
2shows the optimised TLM processing summary for protectedand
passivated AlN/GaN MOS-HEMT samples. A summaryof the optimised RC
and Rsh values on HEMT and MOS-HEMT is shown in Table 1. The sheet
resistance of theprotected sample (159Ω/�) is about one third that
ofthe unprotected one (450Ω/�). Clearly, protection of thesamples
during processing is the key to good performance.On the other hand,
the TLM results of unprotected andunpassivated samples exhibited
very low contact resistancesfor this material system with an
average value of 0.31Ω·mm.This result provides an indication of how
Ohmic contactsmay be processed for a protected sample.
By employing the structure in Figure 2 for TLMprocessing,
optimisation of wet etching using 16H3PO4 :HNO3 : 2H2O Al etch
solution prior to Ohmic metallisationproduced very low contact
resistance as well as very low sheetresistance as reported in [9].
Figure 3 shows the measuredI-V characteristics on 5 μm TLM gap
spacing of annealedOhmic contacts under different Al etch times
prior to Ohmic
0
20
Cu
rren
t(m
A)
40
60
80
100
0 1
B4: etch Al 1 minB1: etch Al 10 sB2: etch Al 20 s
B3: etch Al 40 sB5: etch Al 2 mins
Voltage (V)
2 3
Figure 3: Current-voltage (I-V) characteristics on 5 μm TLM
gapspacing of annealed Ohmic contacts under different Al etch
timesprior to Ohmic metal deposition.
Table 1: Summary of results for the optimised RC and Rsh values
onHEMT and MOS-HEMT samples in the AlN/GaN material system.
Sample Description RC, Ω·mm Rsh, Ω/�
AUnprotected and unpassivated(HEMT)
0.31 480
B2Protected and passivated(MOS-HEMT)
0.49 159
metal deposition. The processing methods for sample B2,on which
Al was etched for 20 secs gave the best I-V plotas compared to
other etching times. The average values ofRC and Rsh for this
sample were 0.49Ω·mm and 159Ω/�,respectively. By using the correct
Al etch time, it seems thatthe top surface of the semiconductor is
etched leaving agood clean surface for metallisation. However, if
the samplewas left longer in the etchant the contact resistance
risesindicating that further undesirable reactions may be
takingplace. Figure 4 shows the measured contact resistance RC
incomparison with other published work for AlN/GaN-baseddevices. It
is clear that the adopted approach here results inone of the lowest
contact resistance values for this materialsystem.
2.2. Gate Wrap-Around MOS-HEMT Optimisation. A gatewrap-around
layout technique [10], where the gate electrodeencircles the drain
as shown in Figure 5, was employed forprocess development and
optimisation on AlN/GaN HEMTstructures. This technique consists
only of Ohmic and gatemetallisation, eliminating the mesa isolation
step. Duringprocess development, 10 mm× 10 mm samples cleaved froma
2-inch wafer were used. Device fabrication starts withstandard
sample cleaning using acetone, isopropanol, anddeionised water. The
optimised Ohmic contact processing
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Active and Passive Electronic Components 3
0.4
0.8
Rc′
(Ω.m
m)
1.2
1.6
2
600 675 750 825 900
[7]
[3]
[15]
[16]
[13]
[this paper], [14][12]
Annealing temperature (◦C)
Figure 4: Comparison of Ohmic contact resistance, RC, on
AlN/GaN-based devices as a function of annealing temperatures
fromvarious publications.
300 μm
50 μmS G D
Figure 5: SEM micrograph of completed gate wrap-around MOS-HEMT
layout. Inset: Device with LSD = 6μm and LG = 3μm.
in Figure 1 was employed for fabrication of unprotectedand
unpassivated AlN/GaN HEMT devices. Deoxidation wasdone on the Ohmic
contact regions by HCl : 4H2O solutionprior to Ohmic metal
deposition. Ohmic metal contacts wereformed by evaporation of
Ti/Al/Ni/Au, followed by a lift-offprocess, and then annealing at
800◦C for 30 secs. Thereafter,gate metal contacts were formed by
evaporation of Ni/Au andfollowed by lift-off process.
AlN/GaN structures are known to be very sensitive toprocessing
liquids, and so unprotected and unpassivatedAlGaN/GaN HEMTs (from
same/similar growth conditions)were also processed and fabricated
to provide comparativedata. DC measurements were done by contacting
the probeneedles directly on top of the source (S), drain (D),
andgate (G) structures. All measurements were made at
roomtemperature using Agilent’s B1500A Semiconductor Param-eter
Analyzer. Figure 6(a) shows the IDS-VDS characteristicsof
fabricated unprotected and unpassivated 3 μm × 100 μmdevices on
AlGaN/GaN HEMT structure. Devices made onthis material system
exhibited good gate control of draincurrents up to a gate bias of 1
V and achieved a maximumdrain current of ∼800 mA/mm. The devices
also showedboth good pinch-off and good saturation characteristics.
Onthe other hand, devices made on AlN/GaN HEMT structure
0
200
I DS
(mA
/mm
)
400
600
800 VGS = 1 V to −5 VStep 1 V
0 2 4 6 8 10
VDS (V)
(a)
0
40
I DS
(mA
/mm
)
80VGS = 5 V to −1 VStep 1 V
0 2 4
Excessive gate current
6 8 10
VDS (V)
(b)
Figure 6: IDS-VDS characteristics of fabricated unprotected
andunpassivated with 3 μm × 100 μm device (a) AlGaN/GaN HEMTand (b)
AlN/GaN HEMT.
exhibited very high leakage currents, did not pinchoff, andthe
drain current was very low as shown in Figure 6(b).
These results, together with the TLM results describedin the
previous subsection, showed that there were someissues with
processing of AlN/GaN HEMT structure whichare not seen in AlGaN/GaN
HEMTs. Exposure to differentprocessing chemicals such as resist
developer and solventssolutions could help reduce the Ohmic contact
resistancebut at the same time this may have led to the
degradationof the quality of the AlN/GaN epilayer structures.
Similarobservations were made by Fan et al. [11] on the formationof
low Ohmic contact on n-GaN materials, where reducedOhmic contact
resistance was caused by the damage of theRIE process employed
prior to deposition of the Ohmiccontact metallisation. The devices
however suffered fromsurface sensitivity and high leakage currents.
It is thereforenecessary to protect the AlN/GaN epitaxial layers
duringdevice processing.
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4 Active and Passive Electronic Components
1 nm GaN3 nm AlN
3.8 μm GaN 2 DEG
(a)
2 nm Al1 nm GaN3 nm AlN
3.8 μm GaN 2 DEG
(b)
S D
1 nm GaNAl2O3Al2O3 Al2O3
3 nm AlN3.8 μm GaN 2 DEG
(c)
1 nm GaNAl2O3Al2O3 Al2O3
3 nm AlN
3.8 μm GaN 2 DEG
(d)
S DG
1 nm GaNAl2O3Al2O3 Al2O3
3 nm AlN3.8 μm GaN 2 DEG
(e)
Figure 7: Process flow for fabrication of protected and
passivatedAlN/GaN MOS-HEMTs using the gate wrap-around
technique.Processing includes (a) sample cleaning and deoxidation,
(b) 2 nmAl deposition, (c) etching Ohmic regions and thermal
oxidationof Al, (d) Ohmic metallisation and annealing, and (e)
gatemetallisation and device measurements.
A new process for the fabrication AlN/GaN-based deviceswas
therefore developed. It involved employing thermallygrown Al2O3 for
protection of the very sensitive AlN epilayerfrom exposure to
liquid chemicals during processing [6]as earlier described for TLM
experiments (Figure 2). ThisAl2O3, which is formed by thermal
oxidation of evaporatedAl, acts as a surface passivate and as a
gate dielectric for thetransistors. Figure 7 shows the process flow
for fabrication ofprotected and passivated AlN/GaN MOS-HEMT using
thegate wrap-around technique.
To further directly explore the impact of Ohmic
contactsoptimisation on device performance, devices were
fabricatedin which the etching time of the Al in Ohmic contact
regionwas varied. Figure 8 shows the typical IDS-VDS
characteristicsof fabricated 3 μm × 100 μm gate AlN/GaN
MOS-HEMTdevices with different etching times, 10 secs and 20 secs.
Itis clear that a 20-sec Al etch has a significant impact onthe
device performance with the drain current at zero gatevoltage
(IDSS) more than double that of a device in whichthe etching time
was 10 secs. Compared to similar resultsfor the AlN/GaN HEMT
(unprotected and unpassivateddevice in Figure 6(b)) on the same
epilayer structure, theseresults show that protecting and
passivating the AlN/GaNlayers during processing yield AlN/GaN
MOS-HEMT withfar superior and excellent transistor characteristics
[6].
2.3. Mesa AlN/GaN MOS-HEMT Optimisation. The devel-oped process
technology was extended to realise AlN/GaNMOS-HEMTs using the
conventional mesa isolation tech-nique for devices. The process
flow is similar to that forthe gate wrap-around devices (Figure 7)
but with additionalmesa isolation and the bond pad steps. Figure 9
shows
0
400
I DS
(mA
/mm
)
800
1200
0 2 4 6 8 10
20 s Al etch10 s Al etch
VDS (V)
Figure 8: IDS against VDS characteristics of fabricated 3 μm
×100 μm gate AlN/GaN MOS-HEMT devices with different etchingtimes
using the simplified gate wrap-around method. The devicesare biased
from VGS = +3 V to −4 V with step size of 1 V.
GateAl2O3
1 nm GaN3 nm AlN
Unpassivatedmesa sidewall
edge
3.8 μm GaN2 DEG
(a)
GateAl2O3
1 nm GaN3 nm AlN
Passivated mesasidewall edge
3.8 μm GaN2 DEG
(b)
Gate
Source
5 μmMesa sidewall edge
Drain
(c)
Figure 9: Schematics cross-section of fabricated MOS-HEMT
(a)without mesa sidewalls edge passivation, (b) with mesa
sidewallsedge passivation, and (c) top-view SEM micrograph of
completedtwo-finger 2.5 μm gate length device.
the schematic cross-section of fabricated MOS-HEMT with(a)
unpassivated and (b) passivated mesa sidewalls, respec-tively.
Figure 9(c) shows the topview SEM micrograph ofcompleted two-finger
2.5 μm gate length device.
-
Active and Passive Electronic Components 5
0
100
200
I DS
(mA
/mm
)
300
400
500
0 2 4 6 8 10
Devices do not fully pinch-off
WG = 2× 300 μmWG = 2× 400 μm
VDS (V)
Figure 10: IDS against VDS characteristics of fabricated
two-finger3 μm gate length AlN/GaN MOS-HEMT mesa devices with
unopti-mised etching time (Al etch for 10 secs). The devices had no
mesasidewall passivation and were biased from VGS = +3 V to −4 V
witha step size of 1 V.
3. Characterisation, Results, and Discussion
Initially, mesa devices were fabricated without mesa
sidewallpassivation and with an unoptimised Ohmic contact
process.Figure 10 shows typical IDS-VDS characteristics of a 3 μm
gatelength AlN/GaN MOS-HEMT device made this way. Thedevices
exhibited high knee voltages (high Ohmic contactresistance) and
very high leakage currents. The reason forthe high leakage currents
seemed to be the contact betweenthe gate metal and the exposed mesa
sidewalls edge asillustrated in Figure 9(a). To solve this problem,
the deviceswere passivated with an additional layer of thermally
grownAl2O3 on the mesa sidewalls edge as shown in Figure
9(b).Significant improvement in the DC characteristics of
thefabricated devices using this new process was observed.
Themeasured IDS-VDS characteristics and the device
transcon-ductance versus gate voltage are shown in Figure 11.
Thedrain current and transconductance are observed to decreasewith
gate width. This is attributed to selfheating effects.
The small signal RF performance of this device was alsomeasured
(not shown here). A unity current gain cutofffrequency, fT , and
power gain cutoff frequency, fMAX, of2.8 and 7.9 GHz were obtained
for a two-finger 2.5 μm ×100 μm device, respectively, for a device
biased at VDS = 4 Vand VGS = −1 V. Devices with gate length of 0.2
μm and0.5 μm were also fabricated using the processing with
mesasidewalls passivation [17]. Excellent DC and RF performancewas
observed from the fabricated device as shown inFigure 12. fT and
fMAX of 50 GHz and 40 GHz, respectively,were achieved for the 0.2
μm devices, and of 20 GHz and30 GHz, respectively, for the 0.5 μm
devices. The DC andRF measurements were made at room temperature
usingthe Agilent’s B1500A Semiconductor Parameter Analyzerand
E8361A PNA Network Analyzer, respectively. Each
0
400
I DS
(mA
/mm
)
800
0 2 4 6 8 10
WG = 2× 100 μmWG = 2× 200 μm
VDS (V)
(a)
0
100
Gm
(mS/
mm
)
200
−6 −4 −2 0
GmIDS
VGS (V)
WG = 2× 100 μm
WG = 2× 200 μm 0
300
I DS
(mA
/mm
)
600
(b)
Figure 11: (a) IDS against VDS and (b) Gm against VGS
character-istics of fabricated two-finger 2.5 μm gate length
AlN/GaN MOS-HEMT devices with optimised 20 s of etching time with
passivatedmesa sidewalls. The devices are biased from VGS = +3 V to
−4 Vwith step size of 1 V.
10 mm × 10 mm sample had approximately 70 devices, andthe
variation in device performance on a sample was under5%. Two
different samples from neighbouring parts of awafer had comparable
device characteristics indicating goodwafer uniformity and
reproducibility of the process.
4. Conclusion
The processing of AlN/GaN-based HEMTs has beendescribed and
discussed. The sensitivity of the AlN/GaNepitaxial layer structure
necessitated the introduction ofspecial processing requirements and
the use of thermally
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6 Active and Passive Electronic Components
0
400
800
I DS
(mA
/mm
)
1200
1600
0 2 4 6 8 10
VGS = 3 V to −6 VStep 1 V
LG = 0.2 μmLG = 0.5 μm
VDS (V)
(a)
0
10
20
Gai
n(d
B)
30
40
1 10 100
LG =0.5 μmfT = 20 GHzfmax = 30 GHz
LG =0.2 μmfT = 50 GHzfmax = 40 GHz
fTfmax
Frequency (GHz)
(b)
Figure 12: (a) IDS against VDS characteristics of fabricated
two-finger 100 μm gate width AlN/GaN MOS-HEMT with gate lengthsof
0.2 μm and 0.5 μm, (b) the small-signal RF performances. Thedevices
are biased at VGS = −2.5 V and VDS = 10 V.
grown Al2O3 as a gate dielectric and device
passivation.Excellent DC and RF characteristics on AlN/GaN
MOS-HEMTs were achieved but further reduction in the Ohmiccontact
resistance is still required before the full potentialof this
material system can be realised. The achieved resultsindicate the
potential of AlN/GaN MOS-HEMT technologyfor high frequency and high
power applications.
Acknowledgment
The authors would like to thank staff at the James
WattNanofabrication Centre (JWNC), University of Glasgow,
forsupporting and assisting this work.
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