Alloying conducting channels for reliable neuromorphic ...10.1038... · by its pixel values (e.g. 0-19, 20-39, etc.). The average values of the pixel groups were calculated for each

Lettershttps://doi.org/10.1038/s41565-020-0694-5

Alloying conducting channels for reliable neuromorphic computingHanwool Yeon1,2,9, Peng Lin1,2,9, Chanyeol Choi   2,3,9, Scott H. Tan1,2, Yongmo Park1,2, Doyoon Lee1,2, Jaeyong Lee1,2, Feng Xu4, Bin Gao   4, Huaqiang Wu   4, He Qian4, Yifan Nie5, Seyoung Kim6,7 and Jeehwan Kim   1,2,8 ✉

1Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA. 2Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA, USA. 3Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA. 4Institute of Microelectronics, Tsinghua University, Beijing, China. 5Materials Science Division, Lawrence Berkeley National Laboratory, Berkeley, CA, USA. 6IBM T. J. Watson Research Center, Yorktown Heights, NY, USA. 7Department of Materials Science and Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South Korea. 8Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA. 9These authors contributed equally: Hanwool Yeon, Peng Lin, Chanyeol Choi. ✉e-mail: [email protected]

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NATure NANoTeCHNoLoGY | www.nature.com/naturenanotechnology

Alloying conducting channels for reliable neuromorphic computing

Hanwool Yeon, Peng Lin, Chanyeol Choi, Scott H. Tan, Yongmo Park, Doyoon Lee, Jaeyong

Lee, Feng Xu, Bin Gao, Huaqiang Wu, He Qian, Yifan Nie, Seyoung Kim, and Jeehwan Kim

This PDF file includes:

Supplementary Figures 1-21

Supplementary Table 1-2

Supplementary Note 1. DFT and KMC simulation for conduction channel formation

Supplementary Note 2. Design considerations for array fabrication with Si electrode

Supplementary Note 3. Array operation at reduced conductance ranges

Supplementary Note 4. Analysis of the impact of line resistance and sneak paths in alloy

memristor arrays

Figure S1. Phase diagram of metal-silicon. a, Ag-Si1. b, Ti-Si2, c, Cr-Si3. d, Ni-Si4. e, Cu-

Si5. Except for Ag, silicide formation is thermodynamically preferred for Ti, Cr, Ni, and Cu.

Figure S2. DC Switching uniformity of Ag memristors. Temporal variation in set voltage

(a) and on/off conductance (b) of Ag device as shown in Fig. 1a in the manuscript. Spatial

variation in set voltage (c) and on-off conductance (d). Each batch contains ≥5 devices tested

under the same DC operating condition (compliance current, 5 mA. >100 DC cycles per 1

device). The standard-deviation-to-mean (Δ/µ) of set voltage and on/off ratio were extracted

as 16.2% and 156.2% for batch 1 and 18.7% and 189.7% for batch 2, respectively.

Figure S3. Phase diagram of metal-silver. a, Ti-Ag6. b, Cr-Ag7. c, Ni-Ag8. d, Cu-Ag9. Ti

forms intermetallic compounds with Ag, indicating that attraction force exists between Ti and

Ag. Although Cr, Ni, and Cu form eutectic system with Ag, a miscible region exist at Ag-rich

phase in Cu-Ag alloy. Thus, Cu-Ag can form thermodynamically stable mixed compound (i.e.,

solid solution), whereas repulsion force occurs at Cr-Ag and Ni-Ag regardless of a mixing ratio

and a mixing temperature.

Figure S4. Metal diffusivity in Si. a, Diffusion barrier height of Ti10, Cr11, Ni12, Cu13, and

Ag14. b, Arrhenius plot of the metal diffusivity. Diffusion of Cu, Ni, or Cr is faster than Ag,

whereas Ti is the slowest metal.

Figure S5. Interfacial energy and relaxed structures of Ag-Cu layer on Si switching

medium. As depicted in the schematic (left), when we closely look at the interface of metal

cluster and Si medium, there are three possible cases as described: (1) pure Ag, (2) Ag-Cu

alloy, (3) pure Cu. The introduction of Cu results in a decrease of interfacial energy and the

interfacial energy of pure Ag clusters is 55 meV Å-2 higher than pure Cu clusters. This indicates

that an external pressure to Ag-Cu clusters is reduced by lower interfacial energy compared to

pure Ag clusters and alloying Cu with Ag can enhance the thermodynamic stability of Ag-

based conduction channel in Si switching medium. The details of simulation are included in

Supplementary Note 1.1.

Figure S6. Switching dynamics based on alloying conduction channel. Forming (left),

reset (middle), and set (right) states were captured from Supplementary Video 1. In this

simulation, we observe the conduction channel in Si switching medium formed by mixed Ag

and Cu atoms. Actual alloying has been considered inside a switching medium during forming

with incoming uniform mixture of Ag/Cu atoms. For the initial state, we considered the atomic

fraction of Ag and Cu and their activation energy for cation dissolution from anode. 1 s state

of forming process is the stage where Ag and Cu atoms start dissolving into the Si switching

medium based on their activation energy. Also, during reset/set processes, Ag clusters are

dominantly dissolved/rejuvenated while Cu clusters mostly remain. These residual Cu atoms

can be the origin of backbone of the conduction channel and enhance the switching uniformity

and the stability of conductance states. The details of the results are explained in Supplementary

Note 1.2 and the simulation conditions and parameters are included in Supplementary Note 1.3

and Supplementary Table 1, respectively.

Figure S7. Flowchart of KMC simulation

Set up the resistance network

Calculate the electric potential and

current

Calculate the temperature distribution

Calculate the probability of microscopic

process

Decide which process in this iteration

Update the atoms and ions configuration

and update the resistance network

Finish? End

Random number

Y N

Figure S8. Spatial variation of Ag-Cu memristors. Cumulative probability of (a) set voltage

and (b) on-off conductance (read voltage, 0.6 V). Each batch contains ≥5 devices tested under

the same DC operating condition (compliance current, 5 mA. >100 DC cycles per 1 device).

The standard-deviation-to-mean (Δ/µ) of set voltage and on/off ratio were extracted as 5.1%

and 49.4% for batch 1 and 4.9% and 47.1% for batch 2, respectively.

Figure S9. Typical forming process and following reset process of pure Ag devices (a) and

Ag-Cu alloy devices (b). Note that high forming voltage (>10 V), that can induce permanent

breakdown of the devices and low device yield accordingly, is undesirable for memristor

crossbar array operation15,16. Forming voltage of Ag and Ag-Cu devices is around 3.7 V, 1~2

V higher than set voltage (c). We believe that this difference is allowable for the array operation

that is strongly supported by high yield (~100%) of Si memristor crossbar array.

Figure S10. Retention test with raised temperature for 1 h. At room temperature (a) and

85 °C (b), conductance levels (over 10 µS) were stable, although the lower conductance levels

could not be secured because of poor stability and increased off-state conductance by thermal

excitation of free carriers from p+-Si layer, respectively. However, as temperature increased to

120 °C (c), conductance was decayed gradually which is similar with retention behaviors of

pure Ag devices at room temperature.

Figure S11. Ambient moisture effect on memristive performance of Ag-Cu devices. DC

switching (a), the corresponding on & off-state conductance (b), and retention properties (c)

as a function of percentage of relative humidity (%RH) at room temperature. As moisture

(H2O) in a switching medium play important roles in redox-based switching dynamics, ambient

moisture level can influence the switching performance of redox-based memristors17–19.

However, Ag-Cu devices shows similar switching characteristics and retention properties,

although humidity level was changed from 12 to 60%RH. This stable behavior could be

attributed to passivation layers in the device that suppressing migration of H2O into Si

switching medium: Cr20,21 and silicon nitride22–24 layers, known as effective materials for

blocking of water molecules/ions penetration (i.e., anti-corrosion), cover Ag-Cu active metal

and Si switching medium, respectively (See Methods in the main manuscript.).

Figure S12. ANL and G contrast from temporal and spatial variations of analog

switching. 5-cycles of 50 potentiation and 50 depression pulses are applied for conductance

update from 10 Si memeristor devices each with three different active metals (a) Ag-Cu alloy,

(b) pure Ag, and (c) Ag-Ni alloy. Pulse condition: Potentiation (50 ns, 4.8 V, n = 50),

Depression (50 ns, -2.9 V, n = 50), Vread (1 V, 1 ms).

Figure S13. Endurance of Ag-Cu alloyed device. Pulsed voltage stresses (PVS) test is

performed under a square pulse condition (non-sinusoidal periodic waveform) on small device

cells (< 25 µm2). Each pulse cycle is composed of potentiation process and depression process.

While potentiation process (VP) is carried out with 50 pulses of 4.5 V (amplitude), 50 ns

(duration), depression process (VD) is conducted with 50 pulses of -2.8 V (amplitude), 50 ns

(duration). Data points of ON (red dots) and OFF (black dots) states are collected at a power

of 2 DC cycles (2n, n = 0 to 24) with read voltage (0.5 V). During the entire PVS test (> 109

pulses), the device secure high on/off ratio (> 100), which is fairly higher than 5 (considered

as device failure)25,26. DC condition: set (4 V), reset (-3.2 V), and compliance current (5 mA).

Figure S14. Change in conductance (ΔG) as a function of pulse amplitude and duration.

Nanosecond pulse measurement is carried out for conductance change (ΔG). We set the initial

conductance to 10-6 S at read voltage 1 V. (a) Conductance change with various square pulse

voltage amplitudes (V = 2, 3, 4, and 5). Inset in (a) shows the pulse condition for conductance

measurement. (b) Conductance change with various square pulse durations at nanosecond level

with 4 V nanosecond pules. Inset (left) presents the conductance change with ultrashort pulses

(10 ns, 30 ns, and 50 ns with 5 V nanosecond pulses). Inset (right) in (b) shows the pulse

condition for conductance. 5 µm x 5 µm size cell is used for both cases.

Figure S15. 512-steps analog potentiation and depression (512P/512D). 3-cycles of 512

potentiation and 512 depression pulses are applied for conductance update in AgCu alloy Si

memristor device. Pulse condition: Potentiation (200 ns, 3.7 V, n = 512), Depression (200 ns,

-2.75 V, n = 512), Vread (1 V, 200 ns).

Figure S16. Statistical analysis of the retention measurement for all the image pixels

shown in Fig. 4d. Pixels in the 256-level grayscale images are evenly divided into 13 groups

by its pixel values (e.g. 0-19, 20-39, etc.). The average values of the pixel groups were

calculated for each time step and for each alloy device including (a) Ag, (b) Ag-Ni and (c) Ag-

Cu. The left y-axis of the figures represents the grayscale image values mapped from the

conductance values, while the right y-axis shows the actual conductance of the device.

Figure S17. I-V characteristics of the Ag-Cu memristor with different compliance

current. The device can be stably programmed with compliance current below 100 μA.

Figure S18. SPICE simulation setup. (a) IV characteristics of Ag-Cu behavioral model

compared to measured device performance (b) A modified Ag-Cu model with lower OFF state

conductance. (c) Schematics of the 1/2V and 1/3V write scheme and ground read scheme that

have been used in array operation and SPICE simulation.

Figure S19. SPICE simulation for write process. (a) Voltage delivery maps of Ag-Cu arrays

with different line resistances and biasing schemes. Source terminal bias of 3V is applied from

left and bottom terminals. Color gradients indicate reduced voltage biases applied across device

junctions in the 32 × 32 array. (b) Simulation of write process to deliver 3V to worst-case cells

in arrays, i.e. furthest cell to the source such as top right cell in (a). Arrays with different

dimensions were evaluated. The green and blue lines are extracted voltages biases applied at

the half-selected cell that is closest to the source. Write disturb occurs when the voltage bias of

half-selected cell exceeds the writing threshold (e.g. 3V). The simulations were carried out for

three different device conditions, namely original Ag-Cu model, modified Ag-Cu model and

Ag-Cu model that only uses lower 10% of conductance ranges. Using better device model or

reducing conductance ranges of Ag-Cu memristor yield improved scalability for write process.

Figure S20. SPICE simulation for read process. (a) Average read error from each column

in 32 × 32 arrays. The read error is defined as the differences between the inferred device

conductance based on the TIA readout and the actual device conductance. The simulation

results showed increasing reading errors for cells that were further away from the source,

induced by line resistance. Three different device conditions as were used in write simulation

were also studied here. Limiting device conductance was found to be helpful in reducing the

impact from line resistance. (b) Simulation of read error in 1 × 32 array with the same wire

resistance as in (a) to rule out the impact from sneak paths. The simulations yielded comparable

results from (a). (c) The read error differences between (a) and (b) were calculated and showed

very minor differences, indicating the line resistance is the dominating factors during read

process with ground read scheme. (d) Read error simulation during read process in different

array sizes using Ag-Cu device model with the limited (lower) conductance range.

Figure S21. SPICE simulation for computing. (a) Simulated multiply-accumulate (MAC)

error from each column in 32 × 32 arrays. The calculated MAC value of input voltage vectors

and the programmed devices’ conductance (values inferred from TIAs) are compared with the

actual MAC output from the array. (b) Simulation of MAC error in different array sizes using

different device conditions.

Supplementary Table 1. Summary of KMC simulation parameters

Process Cu Ea value (eV) Ag Ea value (eV)

Cation dissolution from anode

(Cu+ and Ag+) 0.5227,28 0.827,28

Cation diffusion in Si (Cu+ and

Ag+) 0.4313 1.1513

Cation reduction at nucleation

site 0.45 0.5

Ag-Cu cluster growth 0.55 0.65

Atom oxidation from Ag-Cu

cluster

0.98, 1.08, 1.18, 1.5

respectively related to the

atom with 1, 2, 3, 4 bonds

1.0, 1.1, 1.2, 1.5 respectively

related to the atom with 1, 2,

3, 4 bonds

Atom oxidation from

nucleation site 1.45 1.25

Supplementary Table 2. Summary of simulation parameters

Parameters Values

Line Resistance 0.1Ω, 1Ω, 10Ω (cell-to-cell)

Array Dimensions 8 × 8, 16 × 16, 32 × 32, 64 × 64, 96 × 96, 128 × 128

I/O biasing

schemes

Write: 1/3 V, 1/2 V,

Read/VMM: Ground

Array Weight

Distributions Device states ∈ U(0,1) or U(0,1/10) (normalized)

Selected Device

Weights 0, 1/2, 1 or 0, 1/20, 1/10 (normalized)

Supplementary Note 1. DFT and KMC simulation for conduction channel formation

1.1. DFT calculation of stability of the interface between metal clusters and Si medium

When metallic clusters are formed in a solid electrolyte, extra pressure (ΔP) is applied

on the clusters due to the surface tension29,30. Δp is given approximately by Δp = 2 γ /r, where

γ is the interfacial energy and r is the radius of the clusters. Thus, metal clusters can be ruptured

by the extra pressure and the interfacial energy should be minimized to enhance

thermodynamic stability of metal clusters. Ag clusters has been utilized to demonstrate volatile

resistive switching devices (called diffusive memristor) rooted on high interfacial energy of

Ag/switching medium31. This is in line with our results that pure Ag drives unstable

conductance weight elucidated by thermodynamic immiscibility of Ag in Si. As a first-order

approximation, the interfacial energy between Si surface and metal (alloy) layers were

investigated using DFT calculation with Vienna ab-initio Simulation Package (VASP). The

valence electrons were expanded into projected augmented waves, with a cut-off energy of 450

eV. Perdew-Burke-Ernzerh of method is used to describe the exchange-correlation effect. The

convergence criteria for electronic and ionic calculations were 10-6 eV and 10-5 eV,

respectively. To minimize the lattice mismatch, the Si-metal interface was constructed with

2x2 Si-3x3 Cu, 3x3 Si-4x4 Ag, with bi-axial strain of 0.4% and -1.5% exerted on the metal

layers, respectively. Integration over the first Brillouin zone was performed on a 4x4x1

Monkhorst-Pack mesh. The interfacial energy between Si and metal layer (γint) is defined as

follows: γint = (Esystem - ESi - Emetal)/A - γSi - γmetal, where ESi is the energy of silicon substrate,

Emetal is the total energy of metal (alloy) layer, Esystem is the total energy of metal/Si stacked

system, A is the interface area, γSi is the surface energy of Si, and γmetal is the surface energy of

metal, respectively32,33. Two types of Cu-Ag alloying scenarios over Si surface are examined:

(1) Si in contact with metal layers (Ag and Cu) and (2) Si contact with full Cu-Ag

stoichiometric mixture (Si/Cu-Ag). Supplementary Fig 5 shows the interfacial energy between

metal layer and Si switching medium. Incorporation of Cu into Ag clusters decreases interfacial

energy, which indicates that alloying Ag with Cu enhances the stability of Ag-based conduction

channel by a reduction of the surface tension. As a result, it leads to uniform and reliable

switching with symmetric analog weight update.

1.2. KMC simulation for conduction channel formation

Figure S6 shows captured images of KMC simulation results of (1) Forming, (2) reset,

and (3) set processes. Continuous simulation results can be found in Supplementary Video 1.

And details of the simulation conditions and parameters are included in Supplementary Note

1.3.

(1) Forming process

When positive bias is applied, anodic oxidation occurs at active metal and metal cations migrate

into Si matrix. During a migration, cations are reduced and metallic clusters are formed at Si

bulk (i.e., conduction channel formation), not on the surface of the inert electrode due to poor

ionic conductivity of Si matrix34 as shown in 3s captured image. As mobility of Cu is

comparable to Ag or even faster, Cu and Ag form metallic clusters simultaneously. A stability

of metallic clusters is determined by Si matrix/metal clusters interfacial energy29,35. Whether

dominant phase of clusters of Cu is a silicide or not, attractive interfacial interaction between

Si and Cu drives thermodynamically stable clusters. But by the same token, Ag clusters are

unstable in Si matrix. Our DC sweep results strongly suggest that Cu-based conduction channel

is too stable to drive resistive switching. Therefore, the number of Cu-based clusters should be

minimized to prevent irreversible breakdown and Ag clusters should act as a dominant

component of the conduction channel. Cu clusters can act as nucleation promoters of Ag

clusters, because Cu enhances thermodynamic stability of Ag in Si.

(2) Reset

As negative bias is applied, Joule-heating-assisted electrochemical oxidation occurs at the

conduction channel36. When the conduction channel is solely composed of Ag, the channel is

easily dissolved because of the thermodynamic instability: high Ag/Si interfacial energy

facilitates the shrinkage of Ag clusters in addition to thermo-electrochemical stresses. In Ag

alloying channel, Ag clusters are dominantly dissolved and clusters of Cu are nearly maintained

at Si matrix (7 s captured image). Residual clusters of Cu can be the origin of stable off-state

conductance level.

(3) Set

Due to stochastic nature of channel re-formation, Ag devices show non-uniform SET

performance. In the case of Ag-Cu alloy memristors, however, as Ag clusters are re-formed

around clusters of Cu─act as the backbone of the conduction channels─uniform switching is

enabled.

1.3. Configuration of KMC simulation

As electrochemical metallization (ECM) RRAM, our KMC simulation contains

various physical and chemical processes including: (1) Ag+/Cu+ cation dissolution from the

anode (dissolution), (2) Ag+/Cu+ cation diffusion in the dislocated Si (diffusion), (3) Ag+/Cu+

cation reduction at the nucleation site (electro-crystallization), (4) Ag-Cu cluster growth from

a single nucleation atom (metal clustering), and (5) Ag/Cu atom oxidation from Ag-Cu cluster

and Ag/Cu atom oxidation from the nucleation site (oxidation). All reduction, oxidation, and

diffusion rates are expressed as P = f ∙ exp(-Ea/kBT), where f is the vibration frequency, Ea is

the activation energy that depends on each process, kB is Boltzmann constant, and T is the

temperature. All relevant parameters are listed in the Supplementary Table 1.

The activation energy barrier for cation dissolution from anode is evaluated according to

Ref 27,28. The cation diffusion in Si is referred from Ref13. The cation reduction and oxidation

activation energies at nucleation site are estimated by the computational method. When the

metal-Si bonding energy is larger, the reduction is more likely to occur while the oxidation is

harder to happen30. This indicates that the activation energy of Cu for reduction is low and

those of Ag for reduction is high. The Ag-Cu cluster growth activation energy is estimated by

thermodynamic nucleation model. In classical nucleation model based on equilibrium

thermodynamics31, both homogeneous and heterogeneous nucleation are mainly governed by

Gibbs free energy (ΔG) associated with the surface energy of cluster (Φ) as expressed as ΔG =

Φ –Δµ, where Δµ represents super-saturation which indicates the electrochemical potential

difference between metal cations and fixed metal atoms in cluster. Since Δµ is proportional to

bonding energy, Cu is estimated to have lower activation energy for cluster growth than Ag 32.

And other parameters for diffusion or redox activity energy barrier are evaluated according to

the DFT calculation. The activity energy associated with the oxidation process from the Ag-

Cu cluster is dependent on the bonds number connected to the atom. Higher activation energy

is required for the oxidation of cluster atom with more connected bonds. When an external

voltage is applied, Ea can be modified in both physical and chemical process. The diffusion

barrier is lowered along the electrical field direction, which drives cation migration from anode

to cathode. For the redox reaction, Ea for the forward and reverse transitions can be described

as –αqη and (1- α)qη, where α is typically 0.5 and η represents the electrochemical

overpotential30,37. To simulate the above microscopic process, a random resistor network based

on the percolation theory is introduced38,39. In this model, the resistance value of the bond

connecting Ag/Cu metal atom site is the lowest denoted by 𝑟𝑙𝑚𝑒𝑡𝑎𝑙, and the resistance value of

the Si-Si bond is the highest denoted by 𝑟ℎ𝑏𝑢𝑙𝑘. The resistance value of the bond connecting

Ag/Cu atom and Si atom falls in between 𝑟𝑙𝑚𝑒𝑡𝑎𝑙 and 𝑟ℎ

𝑏𝑢𝑙𝑘. All the I-V characteristic of the

resistance obeys ohmic behavior. As a result, the electric potential distribution is obtained from

the Kirchhoff equation, and the temperature distribution is given by the Fourier heat equation:

𝐶𝑑𝑇

𝑑𝑡= ∇(𝑘 ∙ ∇𝑇) + 𝑄 (S1)

where C is the heat capacity per unit volume of Si bulk, k is the thermal conductivity of Si bulk

and Q is the Joule heat power density. Based on the electric potential distribution and local

temperature distribution, all microscopic processes are calculated. The KMC simulation

flowchart is shown in the Supplementary Fig. 7.

Supplementary Note 2. Design considerations for array fabrication with Si electrode

Our alloy memristor array used single crystal Si electrode, which offers good switching

performance and high device yield. However, the Si electrode is more resistive than metal to

be used as long interconnects. It is critical to ensure low line resistance for large array

operations (see supplementary Note 4 for more details).

To mitigate this problem, a modified crossbar layout for our alloy memristor array was

used, as schematically illustrated in Extended Data Fig. 4. Specifically, a metal capping layer

of 100 nm thick Ti/Au layer was deposited on top of the long p+ Si bottom electrodes in the

array to reduce the line resistance (see Methods). As a result, we were able to achieve 1.5 Ω

cell-to-cell line resistance, which suffice the operations of our 32 x 32 arrays. This approach

could be even more useful in dense design with 10 nm features where nanometer silicon line

patterns would be highly resistive. The use of this particular layout requires a bit larger area

(~6-8 F2 cell), but it is still a dense design that comes with many performance benefits. The

layout could be further optimized when using more sophisticated foundry process. Meanwhile,

other engineering efforts such as reducing devices’ conductance ranges, as shown in

Supplementary Note 4, could be helpful to compensate large line resistance, in particularly for

nano-scale arrays.

Meanwhile, the epitaxial grown p+ Si bottom electrode used in this work is not a

mandatory requirement for the alloy memristor. Other types of single crystal p+ Si film with

matching doping concentration can also be used as bottom electrode. For example, we have

fabricated devices from as-received p+ Si wafer and showed identical performance. We chose

the high temperature epitaxial deposition method for the p+ Si layer deposition because it was

the most convenient way available for us to deposit specific p+ Si layer on top of the SOI wafer

with different doping concentration for the device layer. The process can be replaced by any

Front-End-Of-Line (FEOL) compatible doping method such as ion implantation. As a result,

the fabrication process of our memristor is compatible for integration with the CMOS circuits,

which is required for a fully integrated system.

Supplementary Note 3. Array operation at reduced conductance ranges

While large dynamic ranges could mean more resolvable states for computing, the high current

during programming will consume significant amount of power. To handle this issue, we

decided to use only the lower conductance ranges for array operations.

Supplementary Fig. 17 shows the DC characterization of our device with varying

current compliance. The device can be stably programmed below 100 μA while securing

enough operation window. Operating devices in the limited conductance range can still achieve

a good programmability for computing, as demonstrated by the consistent analog switching

behavior shown in Fig. 3 and highly reliable array demonstrations shown in Fig. 4. The reduced

programming current/power could be beneficial for future on-chip memory and computing

applications. Our SPICE simulation (see Supplementary Note 4) also suggests that

implementing low device conductance in arrays is more advantageous in dealing with the sneak

path and line resistance issues. Nonetheless, the actual conductance ranges can still be

optimized further since low device conductance and less dynamic range may introduce higher

latencies and affect the MAC accuracies due to non-ideal circuit conditions such as input

offsets of the readout circuitry and thermal noises.

Supplementary Note 4. Analysis of the impact of line resistance and sneak paths in alloy

memristor arrays

The performance of alloy memristors in large-scale arrays was evaluated by SPICE (Simulation

Program with Integrated Circuit Emphasis) simulation using the behavioral device model of

Ag-Cu memristor. Supplementary Fig. 18a shows the I-V characteristics of the measured

device (gray color) and the SPICE model (red color). Additional device models and conditions

were also employed in the study. First, a device model with similar I-V characteristics of Ag-

Cu memristor but lower OFF state conductance was modified from the Ag-Cu model (i.e. lower

mean conductance and higher On/Off ratio), the IV-plot of the modified model is shown in

Supplementary Fig. 18b. On the contrary, we also studied the scenario where the devices were

only operated at their lower 10% of full conductance ranges (i.e. lower mean conductance and

lower On/Off ratio). In addition to different device models, different line resistances of the

electrodes, different array dimensions and different I/O biasing schemes were also applied to

evaluate their impacts during the Write, Read and Multiply-Accumulate (MAC) operations.

The parameters used in simulations are summarized in Supplementary Table 2.

We first evaluated the array performance during Write operation. Due to the presence

of sneak paths and nonzero line resistances, the voltage bias across the device junction could

largely deviate from the voltage bias applied between the selected row/column source

terminals, causing reduced voltage delivery efficiency, defined as:

Voltage delivery efficiency = Vjunction(i,j) / Vsource = Vjunction(i,j) / (Vrow(i) – Vcolumn(j))

Simulation of Write process was carried out by programming all devices in a 32 × 32

Ag-Cu memristor array to a randomly generated weight distribution. The Write process was

done in sequence for all devices and the row/column source terminals were properly biased

following either 1/3V scheme or 1/2V scheme (as schematically illustrated in Supplementary

Fig. 18c). The actual voltage biases across the selected device junctions were extracted and

used to plot the voltage delivery map, as shown in Supplementary Fig. 19a. Color gradient

observed in the figures indicates noticeable voltage drop across the arrays. The simulation

results suggest that lower line resistance is critical to ensure a good array programming

capability. The existence of non-zero line resistance would not only cause a direct voltage drop

over the electrodes, but also severely affect the biasing accuracy of 1/3V and 1/2V schemes,

thus compromising their effectiveness in suppressing sneak current. Some impact of sneak

paths was also simulated as shown in the color fluctuation associated with the randomly-

generated conductance map for 1/3V and 1/2V schemes.

Because of the reduced voltage delivery efficiency, higher source voltages are required

to compensate the voltage drop. The increasing source voltage biases would also induce larger

voltage biases across those half-selected cells (cells that share at least one electrode with the

selected cell). The write disturbance happens when any half-selected cell receives voltage bias

becoming larger than the switching threshold and being accidentally programmed. To

quantitatively analyze the scalability of Ag-Cu array, we simulated the Write process with

different array dimensions, aiming to deliver 3V (the set threshold of the device) to the worst-

case cell. The junction voltages of selected cell (furthest to the source) and the first half-selected

cell (closest to the source with minimum voltage drop) were extracted from each simulation.

Supplementary Fig. 19b shows the plots of actual junction voltages of selected cell and first

half-selected cell over different array dimensions. We denote the write failure as when the

voltage bias of the first half-selected cell exceeds the selected cell. Our simulation shows that

based on current array conditions, Ag-Cu memristor arrays with dimensions up to 64 × 64 can

be operated with enough margins below potential write failure. To further improve the array

scalability, memristors with low conductance would be preferred, this could be done either

through device engineering to build more resistive memristors, or by limiting the conductance

of the memristors to its lower conductance range. To confirm our assumption, further

simulations were carried out by using either the modified Ag-Cu model with low off state

conductance (high ON/OFF ratio and lower mean conductance) or only the lower 10%

conductance range of existing Ag-Cu model (low On/Off ratio and lower mean conductance).

As shown in Supplementary Fig. 19b, both simulations show the reduced write disturbances,

regardless of On/Off ratio, which suggests that the high contrast between the line resistance

and device resistance is essential to achieve a robust programming in passive selector-less

arrays.

In the meantime, a simulation based on “Ground” read scheme was also carried out to

evaluate the array performance during Read and MAC processes. The “Ground” read scheme

is the practical method to suppress the sneak path current and was employed here for reading

and computing. The schematic of the “ground” scheme is shown in Supplementary Fig. 18c.

Because all the columns were grounded and hold the same voltage potential, the leakage current

flew between the columns were greatly suppressed. However, the successful operation of

ground read scheme will still require low line resistance so that the ground biases can be

accurately applied to all the cells in the array. In this simulation, the line resistance of 1 Ω was

used, which was close to our real array conditions. The read accuracy of the alloy array was

studied by evaluating the read errors from all cells in the 32 × 32 array, as shown in

Supplementary Fig. 20a. The simulated read process was done by applying a read voltage (i.e.

1V) row-by-row to the array. At each read cycle, the conductance of the devices on the selected

row can be inferred and estimated by the column output current. The estimated and the actual

conductance of the devices were compared to calculate the error percentage. Supplementary

Fig. 20a shows the average read error of each column in the 32 × 32 array with different device

models. The simulation results show that the read error increases when the columns are further

away from the source, which results from the line resistance. Employing device models with

low Off state conductance or limiting the conductance range are helpful to reduce the read

error. On the other hand, we further evaluated the effectiveness of ground scheme in

suppressing the sneak path current. This is studied by further simulate the read operation in a

1 × 32 array with same row and column line resistance to the 32 × 32 array, as shown in

Supplementary Fig. 20b. The absolute difference in error percentage between the 32 × 32 array

and 1 × 32 array were calculated and plotted in Supplementary Fig. 20c, showing very minor

differences. The results suggested that in our read process, the nonzero line resistance of

electrode is the major reason for read error. Therefore, reducing line resistance or using low

device conductance are preferred methods to improve reading accuracies, especially in large

arrays. The read errors from a different array size in the preferred low conductance range of

Ag-Cu memristor were further simulated and shown in Supplementary Fig. 20d.

Finally, we evaluated the computing accuracy when multiply-accumulate (MAC)

operations were performed. The MAC operation involves applying arbitrary voltage vectors to

the array and is multiplied by the programmed conductance map of array. However, due to the

substantial impact from the line resistance, the programmed conductance of each cell is

deviated from the target conductance, which generates the MAC error. We defined the MAC

error as the difference between the MAC values sensed from the peripheral output and the

target MAC values calculated based on the input voltage amplitudes and the targeted

conductance values of the devices. It is worth noting that the target conductance here should

be the conductance value sensed from the peripherals during the programming stage, not the

true conductance value of the cell. Supplementary Fig. 21a shows the simulated MAC errors

in 32 × 32 array. Our simulation shows that employing devices with low Off state conductance

or using low conductance strategy are both effective ways to achieve a high accuracy

computing. The average MAC error over different array sizes are further simulated and shown

in Supplementary Fig. 21b. Based on our simulation results, larger array implementations may

be possible, but would require extensive optimizations of the operating conditions, such as

reducing line resistance, using more resilient 1/3V biasing scheme and utilizing low

conductance range. Improving device and array fabrication process is also important to expand

the array size and/or improve the computing accuracy.

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