AL460-Data Sheet-1.0-20090811

AL460 Full HD FIFO Memory

Datasheet

Version 1.0

©2007~2009 by AverLogic Technologies, Corp.

INFORMATION FURNISHED BY AVERLOGIC IS BELIEVED TO BE ACCURATE AND RELIABLE. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY AVERLOGIC FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIE S T HAT M AY RES U LT FROM ITS US E . N O LIC EN SE IS GRAN T ED BY I M P L I C A T I O N O R O T H E R W I S E U N D E R A N Y P A T E N T O R P A T E N T R I G H T S OF AVERLOGIC.

Doc Number: 1-D-PMK262-0001

AL460 Full HD FIFO

©2007~2009 Copyright by AverLogic Technologies, Corp. Version 1.0 2

Amendments

Revise Date Contents Page

08.07.01 Preliminary version 0.01

09.06.04 Revised Reference design schematic: XIN = 14.31818 MHz; CSEL[1:0] = VDD33

09.08.06 Revised Pin definitions: Pin 98 = ROINV; Pin 99 =ROEN.

Disclaimer THE CONTENTS OF THIS DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE. AVERLOGIC TECHNOLOGIES RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. AVERLOGIC DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. CUSTOMERS ARE ADVISED TO CONSULT WITH AVERLOGIC OR ITS COMMERCIAL DISTRIBUTORS BEFORE ORDERING.

AL460 Full HD FIFO


Table of Contents

1 GENERAL DESCRIPTION__________________________________________________ 4 2 FEATURES _______________________________________________________________ 4 3 APPLICATIONS ___________________________________________________________ 5 4 FUNCTION BLOCK DIAGRAM _____________________________________________ 5 5 ORDERING INFORMATION________________________________________________ 6 6 PIN DIAGRAM____________________________________________________________ 6

6.1 Pin Description____________________________________________________________________6 6.2 Pin Diagram ______________________________________________________________________9

7 ELECTRICAL CHARACTERISTICS ________________________________________ 10 7.1 Absolute Maximum Ratings under Free-Air Temperature _________________________10 7.2 Recommended Operating Conditions _____________________________________________10 7.3 DC Characteristics _______________________________________________________________10 7.4 AC Characteristics _______________________________________________________________11 7.5 Timing Diagrams_________________________________________________________________13

8 FUNCTION DESCRIPTION _______________________________________________ 20 8.1 Power-On-Reset & Initialization __________________________________________________20 8.2 WRST, RRST Reset Operation ____________________________________________________21 8.3 Control Signals Polarity Select ___________________________________________________21 8.4 FIFO Write Operation ____________________________________________________________21 8.5 FIFO Read Operation_____________________________________________________________22

9 APPLICATION NOTE _____________________________________________________ 23 9.1 One Field Delay Line (The Old Data Read)________________________________________23 9.2 Two Frame Mode_________________________________________________________________24

10 Mechanical Drawing – 128-PIN LQFP ____________________________________ 27 10.1 14x14x1.4mm 128-Pin LQFP Package _________________________________________27

11 DESIGN NOTES _________________________________________________________ 29 11.1 The AL460 Reference Schematic_______________________________________________29 11.2 General PCB Design Guideline _________________________________________________30

AL460 Full HD FIFO


1 GENERAL DESCRIPTION The AL460 consists of 128-Mbits of memory density and can be configured as an 8M x 16-bit FIFO (first in first out) at maximum R/W operating speed of 150 MHz. The full HD FIFO can be used in a wide range of applications such as multimedia, video capture systems and many other varieties of video data buffering applications. The size and high-speed data access allow full HD video frame capture up to 1080p resolutions. The AverLogic AL460 FIFO memory provides completely independent input and output ports. The built-in address and pointer control circuits provide a straightforward bus interface to sequentially read/write memory that can reduce inter-chip design efforts. The AL460 uses high performance process technologies with extended controller functions (write mask, read skip etc.); it allows easy operation of non-linearity FIFO read/write for use in broadcasting systems, security systems, cameras and many other applications. The AL460 is designed and manufactured using state-of-the-art technologies with low power consumption AC characteristics (2.5V & 3.3V power supply) facilitating high performance and high quality applications. The chip is available in LQFP 128-pin with exposed die pad package; the small footprint allows product designers to keep board real estate to a minimum.

2 FEATURES • 128-Mbit density, 8M x 16-bit configuration

• Supports video NTSC, PAL and HDTV up to 1080p resolution

• Independent 16-bit read/write operations (different I/O data rates acceptable) at a maximum speed of 150 MHz

• High speed synchronous sequential access

• Input/Output enable control

• Polarity Selectable

• 2.5V& 3.3V power supply

• Standard 128-pin LQFP with exposed die pad package

AL460 Full HD FIFO


3 APPLICATIONS • HD video capture and editing systems

• Switcher or format converter boxes

• Video capture or editing systems

• Video data buffering for security systems

• Scan rate converters

• TBC (Time Base Correction) systems

• Frame synchronizers

• Digital video cameras

• Hard disk cache memory

• Buffer for communication systems

• 1080p video data stream buffering

4 FUNCTION BLOCK DIAGRAM The internal structure of each AL460 consists of Input/Output buffers, Write Data Registers, Read Data Registers and main 8M x 16-bit memory cell array and state-of-the-art logic design that takes care of addressing and controlling the read/write data.

5 ORDERING INFORMATION

Part number Speed Grade Package Power Supply Status

AL460A-7-PBF 150 MHz LQFP-128 +2.5V & +3.3 V 2009

AL460A-13-PBF 75 MHz LQFP-128 +2.5V & +3.3 V 2009

Note: AverLogic Technologies PB-free products employ special PB-free material sets; molding compounds/die that attach materials and 100% matte tin plate termination finish do not use materials containing PBB, PBDE or red phosphorus for green-product chips. AverLogic's PB-free products are MSL classified at PB-free peak reflow temperatures that meet or exceed the PB-free requirements of IPC/JEDEC J Std-020C."

6 PIN DIAGRAM

6.1 Pin Description Write Bus Signals

Pin name Pin number I/O type

Description

DI[15:0] 58, 56~51, 49~46, 44~41, 39

I 16-bit data inputs; synchronized with the WCLK clock. Data is acquired at the rising edge of WCLK clock.

WEN 37 I WEN is the write enable signal that controls the 16-bit input data write and write pointer operation

IE 36 I IE is the data input enable signal that controls the enabling/ disabling of the 16-bit data input pins. The internal write address pointer is always incremented at the rising edge of WCLK by enabling WEN regardless of the IE level.

WCLK 38 I WCLK is the write clock input pin. The write data input is synchronized with this clock.

WRST 35 I The WRST is the write rest signal that resets the write address pointer to 0.

WFSEL 34 I Write Frame select pin in Two Frame Mode (TFEN = H): 0: Frame 0 1: Frame 1

*Note: For the polarity definition of all write control signals (WEN, IE and WRST), please refer to the PLRTY pin definition and “Memory Operation” section for details.

Read Bus Signals Pin name Pin number I/O

type Description

DO[15:0] 102, 104~107, 109~111, 113~115, 117~120, 122

O 16-bit data outputs; synchronized with the RCLK clock. Data is output at the rising edge of the RCLK clock.

REN 125 I REN is the read enable signal that controls the 16-bit output data read and read pointer operation.

OE 126 I OE is the data input enable signal that controls the enabling/ disabling of the 16-bit data output pins. The internal read address pointer is always incremented at the rising edge of RCLK by enabling REN regardless of the OE level.

RCLK 124 I RCLK is the read clock input pin. The read data output is synchronized with this clock.

RCLKO 123 O RCLK loop-out clock ROEN 99 I ROEN is the “enable” signal for RCLKO output clock ROINV 98 I RCLK loop-out clock inverts control signal RRST 127 I The RRST is the read reset signal that resets the read address

pointer to 0. RFSEL 128 I Read Frame select pin in Two Frame Mode (TFEN = H):

0: Frame 0 1: Frame 1

*Note: For the polarity definition of all read control signals (REN, OE, RRST,), please refer to PLRTY pin definition and “Memory Operation” section for details. The active states for the loop-out read clock control signals, ROEN and ROINV are also determined by PLRTY pin definitions: active “High” when PLRTY is “GND”, active “Low” when PLRTY is “VDD”.

Power/Ground Signals


Description

VD25M 3, 5, 7, 11, 13, 17, 19, 21, 76, 78, 80, 84, 86, 90, 92, 94

- 2.5V ± 5% power supply for internal memory

VD25 9, 15, 23, 50, 74, 82, 88, 112

- 2.5V ± 5% power supply for internal control logic

PLL25 70 - 2.5V ± 5% power supply for internal PLL PLLGND 71 - PLL GND VD33 40, 57, 103, 121 - 3.3V ± 10% I/O power supply GND 4, 6, 8, 10, 12, 14, 16, 18,

20, 22, 24, 45, 59~63, 73, 75, 77, 79, 81, 83, 85, 87,

GND

89, 91, 93, 95, 97, 100, 101, 108, 116

Miscellaneous Signals


Description

RSTN 32 I Global reset (active Low) PLRTY 33 I Select active polarity of the control signals including

WEN, REN, WRST, RRST, IE, OE, ROEN and ROINV (total of 8 signals) PLRTY = VD33, active low. PLRTY = GND, active high. Note: during memory operation, the pin must be permanently connected to VD33 or GND. If PLRTY level is changed during memory operation, memory data is not guaranteed.

XIN 67 I Crystal input XOUT 68 O Crystal output CSEL[1:0] 65, 66 I Crystal input frequency select pins

“00” - 11.059200 MHz “01” - 20.000000 MHz “10” - 24.576000 MHz “11” – 14.318180 MHz

* Minimum crystal frequency accuracy: ±100 ppm VREF 72 AI Reference voltage input

* Please refer to “External decoupling circuit” application note for details

VREF2 25 AI Reference voltage input 2 * Please refer to “External decoupling circuit” application

note for details TFEN 96 I Two frame mode enable:

“0” – Standard FIFO Mode “1” – Two Frame Mode

TEST 1 I Test pin (pull-down for normal operation) SCAN 2 I Scan mode Enable (pull-down for normal operation) NC 26~31, 64, 69 - No connect

6.2 Pin Diagram

7 ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings under Free-Air Temperature

(Excessive ratings are harmful to the lifetime of the product. These are guidelines that are not yet tested.)

Parameter Rating Unit

VD33 3.3V I/O Supply Voltage -0.3 ~ +4.5 V

VD25M 2.5V Memory Voltage -0.3 ~ +3.4 V

VD25 2.5V Core Voltage -0.3 ~ +3.4 V

PLL25 2.5V PLL Voltage -0.3 ~ +3.4 V

VP Pin Voltage -0.3 ~ +(VD33 + 0.3) V

IO Output Current -20 ~ +20 mA

TAMB Ambient Op. Temperature 0 ~ +70 °C

Tstg Storage temperature -40 ~ +125 °C

7.2 Recommended Operating Conditions

Parameter Min Typ Max Unit

VD33 3.3V I/O Supply Voltage 3.0 3.3 3.6 V

VD25M 2.5V Memory Voltage 2.37 2.5 2.63 V

VD25 2.5V Core Voltage 2.37 2.5 2.63 V

PLL25 2.5V PLL Voltage 2.37 2.5 2.63 V

VIH High Level Input Voltage 0.7VD33 - VD33 V

VIL Low Level Input Voltage 0 - 0.3VD33 V

7.3 DC Characteristics

(VD33 = 3.3V, VD25M = VD25 = PLL25 = 2.5V; TAMB = 0 to 70°C)

Parameter Min Typ Max Unit

IDD33 Operating Current 100 mA

IDD25 Operating Current 185 mA

IDD25M Operating Current 78 mA

* Operating condition: WCLK = RCLK = 150 MHz; Data toggle rate = 20 MHz

IDD33 Operating Current TBA mA

IDD25 Operating Current TBA mA

IDD25M Operating Current TBA mA

* Operating condition: WCLK = RCLK = 75 MHz; Data toggle rate = 20 MHz

ISB33 Standby Current 4 mA

ISB25 Standby Current 80 mA

ISB25M Standby Current 25 mA

* Standby condition: WCLK = RCLK = 0 MHz

VOH Hi-level Output Voltage VD33-0.4 V

VOL Lo-level Output Voltage 0.4 V

ILI Input Leakage Current (No pull-up or pull-down)

-10 +10 μA

ILO Output Leakage Current (No pull-up or pull-down)

-10 +10 μA

RL Input Pull-up/Pull-down Resistance 60 KΩ

7.4 AC Characteristics

(VDD = 3.3V, Vss=0V, TAMB = 0 to 70°C) 150 MHZ 75 MHz (TBA) Unit

Parameter Min Max Min Max ns

TWC WCLK Cycle Time 6.6 - ns

TWPH WCLK High Pulse Width 2.6 - ns

TWPL WCLK Low Pulse Width 2.6 - ns

TRC RCLK Cycle Time 6.6 - ns

TRPH RCLK High Pulse Width 2.6 - ns

TRPL RCLK Low Pulse Width 2.6 - ns

TAC Access Time 3.0 8.0 ns

TOH Output Hold Time ns

THZ Output High-Z Setup Time ns

TLZ Output Low-Z Setup Time ns

TWRS WRST Setup Time 0.5 - ns

TWRH WRST Hold Time 2.5 - ns

TRRS RRST Setup Time 0.5 - ns

TRRH RRST Hold Time 2.5 - ns

TDS Input Data Setup Time 0.5 - ns

TDH Input Data Hold Time 2.5 - ns

TWES WEN Setup Time 0.5 - ns

TWEH WEN Hold Time 2.5 - ns

TWPW WEN Pulse Width 3.0 - ns

TRES REN Setup Time 0.5 - ns

TREH REN Hold Time 2.5 - ns

TRPW REN Pulse Width 3.0 - ns

TIES IE Setup Time 0.5 - ns

TIEH IE Hold Time 2.5 - ns

TIPW IE Pulse Width 3.0 - ns

TOES OE Setup Time 0.5 - ns

TOEH OE Hold Time 2.5 - ns

TOPW OE Pulse Width 3.0 - ns

TTR Transition Time ns

CI Input Capacitance ns

CO Output Capacitance ns

Note: The read address needs to be at least 1,536 cycles after write address to guarantee new data

read.

7.5 Timing Diagrams

cycle n Reset cycle (s) cycle 0 cycle 1

WCLK

WRST

DI15~0

Write Cycle Timing (Write Reset)

TTR

TWRS TWRH

n-1 n 0 1

TDS TDH

/PLRTY=VDD , WEN= "L" , IE= "L"

cycle n cycle n+1 Disable cycle (s)

WCLK

WEN

DI15~0 n-1 n

TDS TDH

Write Cycle Timing (Write Enable)

TWPH

TWPL

TWES TWEHTWC

n+1 n+2

TWPW

cycle n+2

/PLRTY=VDD ,IE="L" ,WRST="H"

RCLK

RRST

DO15~0 n-1 n

TOH

Read Cycle Timing (Read Reset)

TRPH

TRPL

0 1


TRRS TRRH

TAC

0

/PLRTY=VDD ,REN= "L" ,OE= "L"


WCLK

WEN

DI15~0 n-1 n

TDS TDH

Write Cycle Timing (WEN, WRST)

TWPH

TWPL

TWES TWEH

TWC

n+1 1

TWPW

cycle 0

TWRS TWRH

WRST

0

cycle 1

/PLRTY=VDD ,IE="L"


RCLK

REN

DO15~0 n-1 n

Read Cycle Timing (Read Enable)

TRPH

TRPL

TRES TREHTRC

n+1

TRPW

TOH

TAC

n+2

cycle n+2

/PLRTY=VDD ,OE="L" ,RRST="H"


RCLK

REN

DO15~0 n-1 n

Read Cycle Timing (REN, RRST)

TRPH

TRPL

TRES TREH

TRC

n+1

TRPW

TOH

TAC

0

TRRS TRRH

RRST

cycle 0

/PLRTY=VDD ,OE="L"

cycle n cycle n+1 cycle n+3

RCLK

OE

DO15~0 n-1 n

Read Cycle Timing (Output Enable)

TRPH

TRPL

TOES TOEHTRC

n+1

TOPW

TOH

TAC

cycle n+2

Hi-Z

cycle n+4

n+4

THZ TLZ

/PLRTY=VDD ,REN="L" ,RRST="H"


WCLK

WRST

DI15~0

Write Cycle Timing (Write Reset)

TTR

TWRS TWRH

n-1 n 0 1

TDS TDH

/PLRTY=GND, WEN= "H", IE= "H"


W CLK

W EN

DI15~0 n-1 n

TDS TDH

W rite Cycle Timing (W E, W RST)

TWPH

TW PL

TW ES TW EH

TWC

n+1 1

TWPW

cycle 0

TWRS TW RH

W RST

0

cycle 1

/PLRTY=GND, IE="H"


WCLK

WEN

DI15~0 n-1 n

TDS TDH

Write Cycle Timing (Write Enable)

TWPH

TWPL

TWES TWEHTWC

n+1 n+2

TWPW

cycle n+2

/PLRTY=GND, IE="H", WRST="L"

RCLK

RRST

DO15~0 n-1 n

TOH

Read Cycle Timing (Read Reset)

TRPH

TRPL

0 1


TRRS TRRH

TAC

0

/PLRTY=GND, REN= "H", OE= "H"


WCLK

IE

DI15~0 n-1 n

Write Cycle Timing (Input Enable)

TWPH

TWPL

TIES TIEHTWC

n+1

TIPW

TIH

cycle n+2 cycle n+4

n+4

/PLRTY=GND, WEN="H", WRST="L"


RCLK

OE

DO15~0 n-1 n

Read Cycle Timing (Output Enable)

TRPH

TRPL

TOES TOEHTRC

n+1

TOPW

TOH

TAC

cycle n+2

Hi-Z

cycle n+4

n+4

THZ TLZ

/PLRTY=GND, REN="H", RRST="L"


RCLK

REN

DO15~0 n-1 n

Read Cycle Timing (REN, RRST)

TRPH

TRPL

TRES TREH

TRC

n+1

TRPW

TOH

TAC

0

TRRS TRRH

RRST

cycle 0

/PLRTY=GND, OE="H"

8 FUNCTION DESCRIPTION

8.1 Power-On-Reset & Initialization During system power-up, a power-on-reset is required for successful initialization of FIFO internal logic. After deactivation of its reset state, wait for Tdelay_min (2 ms) before applying any operations to ensure the FIFO is in the normal operating state. Apply a valid reset pulse of WRST and RRST after power-on-reset to guarantee Read/Write operations start at a known address (address point at zero). The following diagrams illustrate global reset and R/W reset timings at power-up with polarity equals VDD and GND

8.2 WRST, RRST Reset Operation The reset signal can be given at any time regardless of the WEN, REN and OE status. However, they still need to meet the setup time and hold time requirements with reference to the clock input. When the reset signal is provided during disabled cycles, the reset operation is not executed until cycles are enabled again.

8.3 Control Signals Polarity Select The AL460 provides the option for operating polarity on controlling signals. With this feature the application design can benefit by matching up the operation polarity between the AL460 and an existing interfacing device without additional glue logic. The operating polarity of control signals WEN, REN, WRST, RRST, IE and OE are controlled by the PLRTY signal. When PLRTY is pulled high, all 6 signals will be active low. When PLRTY is pulled low, all 6 signals will be active high.

8.4 FIFO Write Operation In the FIFO write operation, 16 bits of write data are input in synchronization with the WCLK clock. The FIFO write operation is determined by WRST, WEN, IE and WCLK signals and the combination of these signals can produce different write results. The PLRTY signal determines the activated polarity of these control signals. The following tables describe the WRITE functions under different operating polarities.

PLRTY = VDD WRST WEN IE WCLK Function

L - - ↑ Write reset. The write pointer is reset to zero.

H L L ↑ Normal Write operation. H L H ↑ Write address pointer increases, but no new data will be

written to memory. Old data is retained in memory. (Write mask function)

H H - ↑ Write operation stopped. Write address pointer is also stopped.

PLRTY = GND WRST WEN IE WCLK Function

H - - ↑ Write reset. The write pointer is reset to zero.

L H H ↑ Normal Write operation. L H L ↑ Write address pointer increases, but no new data will be

written to memory. Old data is retained in memory. (Write mask function)

L L - ↑ Write operation stopped. Write address pointer is also stopped.

8.5 FIFO Read Operation

In the FIFO read operation, 16 bits of read data are available in synchronization with the RCLK clock. The access time is stipulated from the rising edge of the RCLK clock. To ensure a valid data read, a minimum of 1.5 Kbyte data write has to occur before any read operations. The FIFO read operation is determined by RRST, REN, OE and RCLK signals; the combination of these signals could produce varying read results. The PLRTY signal could decide the activated polarity of these control signals. The following tables describe the READ functions under different operating polarities. PLRTY = VDD

RRST REN OE RCLK Function L L L ↑ Read reset. The read pointer is reset to zero.

Data in the address 0 is output. L L H ↑ Read reset. The read pointer is reset to zero.

Output is high impedance. L H L ↑ Read address pointer is stopped. Output data is held. Read

address pointer will be reset to zero and data in the address 0 is output after RE goes low.

L H H ↑ Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and output is high impedance after RE goes low.

H L L ↑ Normal Read operation. H L H ↑ Read address pointer increases. Output is high impedance.

(Data skipping function) H H L ↑ Read address pointer is stopped. Output data is held. H H H ↑ Read operation stopped. Read address pointer is stopped.

Output is high impedance.

PLRTY = GND

RRST REN OE RCLK Function H H H ↑ Read reset. The read pointer is reset to zero.

Data in the address 0 is output. H H L ↑ Read reset. The read pointer is reset to zero.

Output is high impedance. H L H ↑ Read address pointer is stopped. Output data is held. Read

address pointer will be reset to zero and data in the address 0 is output after REN goes low.

H L L ↑ Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and output is high impedance after REN goes low.

L H H ↑ Normal Read operation. L H L ↑ Read address pointer increases. Output is high impedance.

(Data skipping function) L L H ↑ Read address pointer is stopped. Output data is held. L L L ↑ Read operation stopped. Read address pointer is stopped. Output

is high impedance.

9 APPLICATION NOTE

9.1 One Field Delay Line (The Old Data Read) As the design shown in the diagram, by applying the reset every 1-field cycle (with the common signal for WRST and RRST) and a constant read/write operation (with all WEN, REN, IE and OE tied to active status), “1 field delay line” timing is shown in the timing chart below. When the difference

between the write address and the read address is 0 (the read address and the write address are the same), the old field data are read as shown in the timing chart.

RCLKW CLK

/RRST/W RST

DI1[15~0] 0

AL460 1 Field Delay Line Tim ing Diagram

1 n

cycle 0 cycle 1 cycle n

DO1[15~0]

0

0

Field m Field m + 1

1

1

cycle 0

tAC

Data of field m

cycle 1

/PLRTY = VDD

9.2 Two Frame Mode Two Frame buffering mechanism enables AL460 to store two complete frames simultaneously. This advantage makes it possible to process two separated frames in parallel for enhancing performance. In standard FIFO mode, the whole memory space is utilized as single block for sequential data R/W. Once Two Frame Mode is enabled (TFEN = VDD), AL460 will be configured into two 4M x 16-bit memory blocks as Frame 0 & Frame 1. Then the user can use these two separated blocks in parallel.

AL460 1 Field Delay Line Diagram

16-bit Input 16-bit Output DI[15:0]

AL460

WEN

WCLK

DO[15:0]

REN

RCLK

Reset

Clock

OE

RRSTWRST

IE

While data in one frame is being read, the other can be written with a new set of data. Read/Write of a desired frame is allocated via R/W frame select pins. The R/W frame selection and control manipulation are illustrated in the following diagrams.

9.3 External Decoupling Circuit To ensure the proper operation of internal memory, an external decoupling circuit must be implemented.

10 Mechanical Drawing – 128-PIN LQFP

10.1 14x14x1.4mm 128-Pin LQFP Package

11 DESIGN NOTES

11.1 The AL460 Reference Schematic

C6

0.1uF

C7

0.1uF

C8

0.1uF

C9

0.1uF

C10

0.1uF

C11

0.1uF

C12

0.1uF

C13

0.1uF

C14

0.1uF

D

VDD33

RP10 15ohmx41234 5

678

C1

0.1uF

C20.1uF

VD

D25

VD

D25

128LQFP

VD

D25

DI[15]DI[14]DI[13]DI[12]DI[11]DI[10]DI[9]DI[8]

DI[7]DI[6]

DI[4]DI[5]

DI[3]DI[2]DI[1]DI[0]

D

C16

33pF

R1 1M

D

X1

14.31818MhzC1533pF

+CP1

10uF/16V

R3 15ohmTWO_FRAME_EN

R9 15ohmRD_FRAME_SEL

R7 15ohm

VD

D25

R8 15ohm

WR_FRAME_SEL

PLRTY

RP3 15ohmx41234 5

678

RP5 15ohmx41234 5

678

VD

D25

DR4 15ohm

C331nF

VD

D25

R5 15ohm

R61

4.7K

VDD33

AL460_RSTN

CSEL[0]

D

D

VDD33

VDD33

CSEL[1]

C34

0.1uFD

D

D D DD D

VDD25

C3

0.1uF

D

D

RP7 15ohmx41234 5

678

RP9 15ohmx41234 5

678

D

VDD33

VDD25_DDR

VDD25

TEST

VDD33

GND

SCAN_EN

C32

0.1uF

C30

0.1uF

C29

0.1uF

C28

0.1uF

C22

0.1uF

C23

0.1uF

C24

0.1uF

C25

0.1uF

C26

0.1uF

C27

0.1uF

C31

0.1uF

VDD33VDD25

R60 15ohmR59 15ohm

U2AL460

1TE

ST

SCA

N2

VD25

M3

VD25

M5

GN

D4

GN

D6

GND59

DI[15]58

VD3357

DI[14] 56

DI[13]55

DI[12]54

DI[11]53

DI[10] 52

DI[9]51

VD2550

DI[8] 49

DI[7]48

DI[6]47

DI[5]46

GND 45

DI[4]44

DI[3]43

DI[2]42

DI[1]41

VD3340

DI[0]39

WCLK 38

WEN37

IE36

WRST35

WFSEL34

PLRTY33

VD

25M

76G

ND

75V

D25

74G

ND

73V

RE

F72

PLL

GN

D71

PLL2

570

NC

69XO

UT

68X

IN67

CS

EL[0

]66

CS

EL[1

]65

VD25

M7

GN

D8

VD25

9G

ND

10VD

25M

11G

ND

12VD

25M

13G

ND

14VD

2515

GN

D16

VD25

M17

GN

D18

VD25

M19

GN

D20

VD25

M21

GN

D22

VD25

23G

ND

24VR

EF2

25N

C26

NC

27N

C28

NC

29N

C30

NC

31R

ST

N32

GND60GND61

NC64

GND 63

GND62

VD

25M

78G

ND

77

VD

25M

80G

ND

79

VD

2582

GN

D81

VD

25M

84G

ND

83

VD

25M

90G

ND

89V

D25

88G

ND

87V

D25

M86

GN

D85

VD

25M

94G

ND

93V

D25

M92

GN

D91

TF

EN

96 95G

ND

GND97

ROINV98

ROEN99

GND100

GND101

DO[15]102

VD33103

DO[14]104

DO[13]105

DO[12]106

DO[11]107

GND108

DO[10]109

DO[9]110

DO[8]111

VD25112

DO[7]113

DO[6]114

DO[5]115

GND116

DO[4]117

DO[3]118

DO[2]119

DO[1]120

VD33121

DO[0]122

RCLKO123

RCLK124

REN125

OE126

RRST127

RFSEL128

R58 15ohmR57 15ohm

C180.1uF

D D

C190.1uF

D

C200.1uF

C210.1uF

D

DO[15]DO[14]DO[13]DO[12]

DO[9]DO[10]

DO[8]

DO[11]

DO[4]

DO[7]

DO[5]DO[6]

RCLKO_ENRCLKO_INV

DO[1]DO[2]

DO[0]

DO[3]

OE

RCLK_OUT

REN

RRST

RCLK

VDD25_DDR

R6 15ohm

+C17

10uF/16VD

D

+C35

10uF/16VC36

0.1uFC37

0.1uFD D

RP12 15ohmx41234 5

678

D

IE

WCLKWEN

WRST

VDD25

L17 BEAD1 2

L18 BEAD1 2

L2

BEAD/DIP1 2

RP4 15ohmx41234 5

678

RP6 15ohmx41234 5

678

L1

BEAD/DIP1 2

C4

0.1uF

C5

0.1uF

RP8 15ohmx41234 5

678

11.2 General PCB Design Guideline The AL460 is available in 128-pin LQFP with thermal exposed die pad package. It has a rectangular metallic terminal exposed on the bottom surface of the package body. The corresponding PCB lands need to be designed to fit well within the PCB assembly process capabilities. The actual manufacturing capability, SMT process, and product specification need to be considered in addition to Averlogic’s guideline for optimizing PCB design.

PCB Thermal Pad Design

For enhanced thermal, electrical, and board level performance, the exposed pad on the package must be soldered to the PCB using a corresponding thermal pad on the board. The key effort is to guarantee reliable solder joints by matching the land pattern to the AL460 terminal pattern. The package cross section is illustrated in the figure in the Section, “Cross Section and Thermal Land Pattern” (below). ♦ The thermal pad should be the approximate size of the exposed pad on the LQFP E-PAD package;

using die pad size as the maximum thermal pad size is recommended, and should be solder mask defined.

♦ Land pattern design for lead attachment on the PCB should be the same as the conventional, non-

thermally/electrically enhanced packages. ♦ To maximize the electrical and thermal performance, connecting thermal pad to inner and/or

bottom ground planes of the PCB by vias is required. ♦ The thermal vias should connect to the internal ground plane with complete connection around the

entire circumference of the plated through hole. The designer should ensure electrical correctness when connecting copper planes to the thermal pad.

♦ Vias with diameters with 0.3 mm or less, and 1 mm via spacing are recommended. ♦ The number of vias should be application specified and dependent upon power dissipation and

electrical conductivity requirements. The thermal and electrical analysis is recommended to determine the minimum number needed.

♦ To avoid device failure due to overheating, the heat flow path through the PCB should be

unobstructed. Do not place large or high power consumption components on the reverse side of PCB board that overlaps with the AL460A footprint.

Solder Masking Consideration

There are two basic types of solder pads used, ♦ Solder Mask defined style (SMD): The copper metal pad is larger than the solder mask opening

above this pad. Thus the pad area is defined by the opening in the solder mask.

♦ Non-Solder mask defined style (NSMD): around each copper metal pad there is solder mask clearance. Dimensions and tolerances of the solder mask clearance have to be specified, such that no overlapping of the solder pad by the solder mask occurs

The NSDM pads are recommended over SMD pads due to the tighter tolerance on copper etching compared to solder masking. NSDM also provides a larger copper pad area and allows the solder to anchor to the edges of the copper pads thus providing improved solder joint reliability.

Cross Section and Thermal Land Pattern

Grounding

Analog and digital circuits are separated within the AL460 chip. To minimize system noise and prevent digital system noise from entering the analog portion, a common ground plane for all devices, including the AL460, is recommended. All the connections to the ground plan should have a very short lead. The ground plane should be solid, not cross-hatched.

Power Planes

The analog portion of the AL460 and any associated analog circuitry should have their own power plane, referred to as the analog power plane (PLL25). The analog power plane should be connected to the digital power plane (VDD25) at a single point through a low resistance ferrite bead. The digital power plane should provide power to all digital logic on the PCB board, and the analog power plane should provide power to all of the AL460 analog power pins and relevant analog circuitry. The digital power plane should not be placed under the AL460 chip, the voltage reference or other analog circuitry. Capacitive coupling of digital power supply noise from this layer to the AL460 and its related analog circuitry can degrade signal integrity.

Bottom View and Cross Section of E-PAD LQFP-128

Power Supply Decoupling

Power supply connection pins should be individually decoupled. The decoupling capacitors should be placed as close as possible to the AL460. The ground connection of the capacitor should go straight to the ground plane through a via placed immediately adjacent to the pad. Ideally, the ground connection should be through 2 vias, one placed on either side of the pad. For the best results, use 0.1µF ceramic chip capacitors. Lead lengths should be minimized. The power pins should be connected to the bypass capacitors before being connected to the power planes. 22µF capacitors should also be used between the AL460 power planes and the ground planes to control low-frequency power ripple.

Digital Signal and Clock Interconnect

Digital signals to the AL460 should be isolated as much as possible from other analog circuitry. These signals should not overlap the analog power plane. If this is not possible, coupling can be minimized by routing the digital signal at a 90 degree angle across the analog signals. The 16-bit digital input bus, DI, should have the same trace length; it also applies to DO, the output digital bus. The high frequency clock reference or crystal should be handled carefully. Jitter and noise on the clock will degrade the data integrity. Keep the clock paths to the AL460 as short as possible to reduce the amount of noise picked up.

CONTACT INFORMATION

Averlogic Technologies Corp. E-mail: [email protected]

URL: http://www.averlogic.com.tw

Averlogic Technologies, Inc. E-mail: [email protected]

URL: http://www.averlogic.com

AL460-Data Sheet-1.0-20090811

Documents

averlogic al460 fifo

averlogic technologies

pin diagram

pin description

patent rights of averlogic

roinv pin

pin lqfp package

hd fifo table of contents1