EE260: Digital Design, Spring 2018 4/8/18 Chapter 11: Counters and Registers 1 EE 260: Introduction to Digital Design Counters and Registers Yao Zheng Department of Electrical Engineering University of Hawaiʻi at Mānoa Counters § Introduction: Counters § Asynchronous (Ripple) Counters § Asynchronous Counters with MOD number < 2 n § Asynchronous Down Counters § Cascading Asynchronous Counters § Synchronous (Parallel) Counters § Up/Down Synchronous Counters § Designing Synchronous Counters § Decoding A Counter § Counters with Parallel Load Agenda Registers § Introduction: Registers v Simple Registers v Registers with Parallel Load § Using Registers to implement Sequential Circuits § Shift Registers v Serial In/Serial Out Shift Registers v Serial In/Parallel Out Shift Registers v Parallel In/Serial Out Shift Registers v Parallel In/Parallel Out Shift Registers § Bidirectional Shift Registers § An Application – Serial Addition § Shift Register Counters v Ring Counters v Johnson Counters § Random - Access Memory (RAM) Agenda Introduction: Counters § Counters are circuits that cycle through a specified number of states. § Two types of counters: v synchronous (parallel) counters v asynchronous (ripple) counters § Ripple counters allow some flip - flop outputs to be used as a source of clock for other flip - flops. § Synchronous counters apply the same clock to all flip - flops. Asynchronous (Ripple) Counters § Asynchronous counters : the flip - flops do not change states at exactly the same time as they do not have a common clock pulse. § Also known as ripple counters , as the input clock pulse “ripples” through the counter – cumulative delay is a drawback. § n flip - flops ® a MOD (modulus) 2 n counter. (Note: A MOD - x counter cycles through x states.) § Output of the last flip - flop (MSB) divides the input clock frequency by the MOD number of the counter, hence a counter is also a frequency divider . Asynchronous (Ripple) Counters § Example: 2 - bit ripple binary counter. § Output of one flip - flop is connected to the clock input of the next more - significant flip - flop. K J K J HIGH Q0 Q1 Q0 FF1 FF0 CLK C C Timing diagram 00 ® 01 ® 10 ® 11 ® 00 ... 4 3 2 1 CLK Q0 Q0 Q1 1 1 1 1 0 0 0 0 0 0
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Agenda Digital Design CountersandRegisters · §Using Registers to implement Sequential Circuits ... or JK flip-flops with identical J,K inputs). ... 4-bit synchronous binary counter.
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EE260: Digital Design, Spring 2018 4/8/18
Chapter 11: Counters and Registers 1
EE 260: Introduction toDigital Design
Counters and Registers
Yao ZhengDepartment of Electrical Engineering
University of Hawaiʻi at Mānoa
Counters
§ Introduction: Counters
§ Asynchronous (Ripple) Counters
§ Asynchronous Counters with MOD number < 2n
§ Asynchronous Down Counters
§ Cascading Asynchronous Counters
§ Synchronous (Parallel) Counters
§ Up/Down Synchronous Counters
§ Designing Synchronous Counters
§ Decoding A Counter
§ Counters with Parallel Load
Agenda
Registers
§ Introduction: Registersv Simple Registersv Registers with Parallel Load
§ Using Registers to implement Sequential Circuits
§ Shift Registersv Serial In/Serial Out Shift Registersv Serial In/Parallel Out Shift Registersv Parallel In/Serial Out Shift Registersv Parallel In/Parallel Out Shift Registers
§ Bidirectional Shift Registers
§ An Application – Serial Addition
§ Shift Register Countersv Ring Countersv Johnson Counters
§ Random-Access Memory (RAM)
Agenda Introduction: Counters§ Counters are circuits that cycle through a
specified number of states.§ Two types of counters:
§ States may be skipped resulting in a truncated sequence.
§ Technique: force counter to recycle before going through all of the states in the binary sequence.
§ Example: Given the following circuit, determine the counting sequence (and hence the modulus no.)
K
JQ
QCLK
CLRK
JQ
QCLK
CLRK
JQ
QCLK
CLR
C B A
BC
All J, Kinputs are 1 (HIGH).
Asyn. Counters with MOD no. < 2n
§ Example (cont’d):
K
JQ
QCLK
CLRK
JQ
QCLK
CLRK
JQ
QCLK
CLR
C B A
BC
All J, Kinputs are 1 (HIGH).
A
B
1 2
C
NANDOutput
10
3 4 5 6 7 8 9 10 11 12Clock MOD-6 counter
produced by clearing (a MOD-8 binary counter) when count of six (110) occurs.
Asyn. Counters with MOD no. < 2n
§ Example (cont’d): Counting sequence of circuit (in CBA order).
A
BC
NANDOutput
10
1 2 3 4 5 6 7 8 9 10 11 12Clock
111 000001
110
101100
010
011
Temporary state Counter is a MOD-6
counter.
000
100
010
110
001
101
000
100
EE260: Digital Design, Spring 2018 4/8/18
Chapter 11: Counters and Registers 3
Asyn. Counters with MOD no. < 2n
§ Exercise: How to construct an asynchronous MOD-5 counter? MOD-7 counter? MOD-12 counter?
§ Question: The following is a MOD-? counter?
K
JQ
QCLR
C B A
CDEF All J = K = 1.
K
JQ
QCLR
K
JQ
QCLR
K
JQ
QCLR
K
JQ
QCLR
K
JQ
QCLR
DEF
Asyn. Counters with MOD no. < 2n
§ Decade counters (or BCD counters) are counters with 10 states (modulus-10) in their sequence. They are commonly used in daily life (e.g.: utility meters, odometers, etc.).
§ Design an asynchronous decade counter.
D
CLK
HIGH
K
J
C
CLR
Q
K
J
C
CLR
QC
K
J
C
CLR
QB
K
J
C
CLR
QA
(A.C)'
Asyn. Counters with MOD no. < 2n
§ Asynchronous decade/BCD counter (cont’d).
D
C
1 2
B
NAND output
3 4 5 6 7 8 9 10Clock
11
A
D
CLK
HIGH
K
JC
CLR
Q
K
JC
CLR
QC
K
JC
CLR
QB
K
JC
CLR
QA (A.C)'
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
Asynchronous Down Counters§ So far we are dealing with up counters. Down
counters, on the other hand, count downward from a maximum value to zero, and repeat.
§ Example: A 3-bit binary (MOD-23) down counter.
K
J
K
J Q1Q0
CCK
JC
Q2
CLK
1
Q
Q'
Q
Q'
Q
Q'
Q
Q'
3-bit binary up counter
3-bit binary down counter
1
K
J
K
J Q1Q0
CCK
JC
Q2
CLKQ
Q'
Q
Q'
Q
Q'
Q
Q'
Asynchronous Down Counters§ Example: Ax 3-bit binary (MOD-8) down counter.
4321CLK
Q0
Q1
1 1
1 0
0
0 1
0 0
0
8765
1 10 0
1 01 0
Q2 1 10 1 1 0 00 0
001000
111
010
011100
110
101
1
K
J
K
J Q1Q0
CCK
JC
Q2
CLKQ
Q'
Q
Q'
Q
Q'
Q
Q'
Cascading Asynchronous Counters§ Larger asynchronous (ripple) counter can be
constructed by cascading smaller ripple counters.§ Connect last-stage output of one counter to the
clock input of next counter so as to achieve higher-modulus operation.
§ Example: A modulus-32 ripple counter constructed from a modulus-4 counter and a modulus-8 counter.
K
J
K
J
Q1Q0
CCCLKQ
Q'
Q
Q'
Q
Q' K
J
K
J
Q3Q2
CCK
JC
Q4
Q
Q'
Q
Q'
Q
Q'
Q
Q'
Modulus-4 counter Modulus-8 counter
EE260: Digital Design, Spring 2018 4/8/18
Chapter 11: Counters and Registers 4
Cascading Asynchronous Counters§ Example: A 6-bit binary counter (counts from 0 to
Designing Synchronous Counters§ Covered in Lecture #12.§ Example: A 3-bit Gray code
counter (using JK flip-flops).
100000
001
101
111110
011
010
Present Next Flip-flopstate state inputs
Q2 Q1 Q0 Q2+ Q1+ Q0+ JQ2 KQ2 JQ1 KQ1 JQ0 KQ00 0 0 0 0 1 0 X 0 X 1 X0 0 1 0 1 1 0 X 1 X X 00 1 0 1 1 0 1 X X 0 0 X0 1 1 0 1 0 0 X X 0 X 11 0 0 0 0 0 X 1 0 X 0 X1 0 1 1 0 0 X 0 0 X X 11 1 0 1 1 1 X 0 X 0 1 X1 1 1 1 0 1 X 0 X 1 X 0
Decoding A Counter§ Decoding a counter involves determining which
state in the sequence the counter is in.§ Differentiate between active-HIGH and active-LOW
decoding.§ Active-HIGH decoding: output HIGH if the counter is
in the state concerned.§ Active-LOW decoding: output LOW if the counter is
in the state concerned.
Decoding A Counter§ Example: MOD-8 ripple counter (active-HIGH
decoding).
A'B'C'
1 2 3 4 5 6 7 8 9Clock
HIGH only on count of ABC = 000
A'B'C
HIGH only on count of ABC = 001
A'BC'
HIGH only on count of ABC = 010
100
ABC
HIGH only on count of ABC = 111
...
EE260: Digital Design, Spring 2018 4/8/18
Chapter 11: Counters and Registers 7
Decoding A Counter§ Example: To detect that a MOD-8 counter is in state
0 (000) or state 1 (001).
A'B'
1 2 3 4 5 6 7 8 9Clock
HIGH only on count of ABC = 000 or ABC = 001
100
§ Example: To detect that a MOD-8 counter is in the odd states (states 1, 3, 5 or 7), simply use C.
C
1 2 3 4 5 6 7 8 9Clock
HIGH only on count of odd states
100
A'B'C'A'B'C
Counters with Parallel Load§ Counters could be augmented with
parallel load capability for the following purposes:vTo start at a different statevTo count a different sequencevAs more sophisticated register with
increment/decrement functionality.
Counters with Parallel Load§ Different ways of getting a MOD-6 counter:
Count = 1Load = 0CPI4 I3 I2 I1
Count = 1Clear = 1CP
A4 A3 A2 A1
Inputs = 0
Load
(a) Binary states 0,1,2,3,4,5.
I4 I3 I2 I1
A4 A3 A2 A1
Inputs have no effect
Clear
(b) Binary states 0,1,2,3,4,5.
I4 I3 I2 I1
Count = 1Clear = 1CP
A4 A3 A2 A1
0 0 1 1
Load
(d) Binary states 3,4,5,6,7,8.
I4 I3 I2 I1
Count = 1Clear = 1CP
A4 A3 A2 A1
1 0 1 0
Load
Carry-out
(c) Binary states 10,11,12,13,14,15.
Counters with Parallel Load§ 4-bit counter with
parallel load.Clear CP Load Count Function
0 X X X Clear to 01 X 0 0 No change1 1 X Load inputs1 0 1 Next state
Introduction: Registers§ An n-bit register has a group of n flip-flops
and some logic gates and is capable of storing n bits of information.
§ The flip-flops store the information while the gates control when and how new information is transferred into the register.
§ Some functions of register:v retrieve data from registervstore/load new data into register (serial or parallel)vshift the data within register (left or right)
Simple Registers§ No external gates.§ Example: A 4-bit register. A new 4-bit data is
loaded every clock cycle.
A3
CP
A1 A0
DQ
DQ Q
D
A2
DQ
I3 I1 I0I2
EE260: Digital Design, Spring 2018 4/8/18
Chapter 11: Counters and Registers 8
Registers With Parallel Load§ Instead of loading the register at every clock
pulse, we may want to control when to load.§ Loading a register: transfer new information
into the register. Requires a load control input.
§ Parallel loading: all bits are loaded simultaneously.
Registers With Parallel Load
A0
CLK
D Q
Load
I0
A1D Q
A2D Q
A3D Q
CLEAR
I1
I2
I3
Load'.A0 + Load. I0
Using Registers to implement Sequential Circuits
§ A sequential circuit may consist of a register(memory) and a combinational circuit.
Register Combin-ational circuit
Clock
Inputs Outputs
Next-state value
§ The external inputs and present states of the register determine the next states of the register and the external outputs, through the combinational circuit.
§ The combinational circuit may be implemented by any of the methods covered in MSI components and Programmable Logic Devices.
Using Registers to implement Sequential Circuits
§ Example 1:A1
+ = S m(4,6) = A1.x'A2
+ = S m(1,2,5,6) = A2.x' + A2'.x = A2 Å xy = S m(3,7) = A2.x
Shift Registers§ Another function of a register, besides
storage, is to provide for data movements.§ Each stage (flip-flop) in a shift register
represents one bit of storage, and the shifting capability of a register permits the movement of data from stage to stage within the register, or into or out of the register upon application of clock pulses.
EE260: Digital Design, Spring 2018 4/8/18
Chapter 11: Counters and Registers 9
Shift Registers§ Basic data movement in shift registers (four
bits are used for illustration).Data in Data out
(a) Serial in/shift right/serial out
Data inData out
(b) Serial in/shift left/serial out
Data in
Data out
(c) Parallel in/serial outData out
Data in
(d) Serial in/parallel outData out
Data in
(e) Parallel in / parallel out
(f) Rotate right (g) Rotate left
Serial In/Serial Out Shift Registers§ Accepts data serially – one bit at a time
– and also produces output serially.
Q0
CLK
D
C
QQ1 Q2 Q3Serial data
inputSerial data outputD
C
Q D
C
Q D
C
Q
Serial In/Serial Out Shift Registers§ Application: Serial transfer of data from one
register to another.
Shift register A Shift register BSI SISO SO
ClockShift control
CP
Wordtime
T1 T2 T3 T4CP
Clock
Shift control
Serial In/Serial Out Shift Registers§ Serial-transfer example.
Timing Pulse Shift register A Shift register B Serial output of BInitial value 1 0 1 1 0 0 1 0 0