Unit 5: Constraining I/O Paths 5-1 PrimeTime: Introduction to Static Timing Analysis 5-1 Constraining I/O paths PrimeTime: Introduction to Static Timing Analysis Synopsys 34000-000-S16 Agenda: Day Two DAY 2 I/O Paths and Exceptions Lab Unit Introduction to Timing Models (QTM) 7 8 Specifying Timing Exceptions 6 Constraining I/O Interface Paths 5 Summary 9 Performing STA Customer Support 10
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Unit 5: Constraining I/O Paths5-1PrimeTime: Introduction to Static Timing Analysis
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Constraining I/O pathsPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Agenda: Day Two
DAY2222 I/O Paths and Exceptions LabUnit
Introduction to Timing Models (QTM)7
8
Specifying Timing Exceptions6
Constraining I/O Interface Paths5
Summary9
Performing STA
Customer Support10
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Unit Objectives
After completing this unit, you should be able to:
� Constrain the input and output (I/O) timing paths for single and multiple non-ideal clocks
� Determine when and how to use a Virtual clock
� Define common base period of synchronous multiple clocks
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The Inputs and Outputs of PrimeTime
Reports
PrimeTime
Technology Libraries
SDFTiming
Models in .db format
Gate-LevelNetlist Constraints Exceptions
SetupFile
Log,Script Files
Our Focus
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Five Step Static Timing Analysis Flow
READREAD
CONSTRAINCONSTRAIN
EXCEPTIONSEXCEPTIONS
CHECKCHECK
ANALYZEANALYZEOur Focus
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Constrain Input and Output Timing Paths
In Unit-4, Path X was constrained bycreate_clock
D QFF4
T
D QFF3
M
B
Clock source
D Q D Q
Clk
Current_Design
FF1 FF2N S
u1u2 u3
u4
A
Network latencySource latency
Clock source
I/O Paths N & S are still unconstrained!
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Input Arrival Time
The_Current_Design
ND Q
Clk
MD Q
TClk-q TM TNTSETUP
Next edge captures data
External Logic
(Input Delay)(TClk-q + TM) (TN + TSETUP)
Clk
A
Launch edge triggers
data
A
Clk
Valid new data
To meet the setup time of our flop:Tclk-q + Tm + Tn + Tsetup < Clock period
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You specifyhow much time
is used byexternal logic.
PT calculateshow much time
is left for theinternal logic.
Launch Edge
1.5
delay ofexternal
logic
time leftfor
internallogic
Capture Edge
Constraining Input Paths
� set_input_delay -max
� Describes the maximum arrival time of external data with respect to a launching clock and an input port
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Test for Understanding
CHIP1CHIP1_CORE
BoardCHIP2
BLOCK2A
Clk
J = .1
CHIP2_COREPort Out1
EXTERNALPATH
DELAY = 2
INTERNALPATH DELAY
CLOCK NETWORK DELAY2
tu = 0.35
tsutsl1 = 0.5
tsl2 = 0.7
tn1 = 0.25
tn2 = 0.5
Your task is to constrain the input timing path(s) in CHIP2_CORE in the context shown above. Use the legend for the terms and the command template provided to you in the Notes section. There is a single clock Clk that controls 2 chips on a board. Your focus is on CHIP2_CORE.
Legend:Clk is 200 MHz Clock with a Jitter (J) = 0.1 and a maximum skew within each chip (tu) = 0.35CHIP1_CORE: Source Latency (tsl1) = 0.5, Network latency (tn1) = 0.25CHIP2_CORE: Source latency (tsl2) = 0.7, Network latency (tn2) = 0.5, Cell name driving CHIP2_CORE is is mux007NOTE1: Make reasonable assumptions for parameters not suppliedNOTE2: You do not have to use all the constraints below. You can, however, use additional constraints.create_clock ______________________________________________________________set_clock_latency __________________________________________________________set_clock_latency –source –early _____________________________________________set_clock_latency –source -late ______________________________________________set_clock_uncertainty ______________________________________________________set_input_delay __________________________________________________________set_driving_cell __________________________________________________________
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Verify or Remove I/O Constraints
report_port -verbose:Returns all constraints and environment placed on all the input and output ports (delay, load, driving cell).
remove_capacitance:Removes capacitance load placed by set_load command
remove_driving_cell:Removes driving cell placed by set_driving_cell
remove_input_delay:Removes input delay constraints from specified ports
remove_output_delay:Removes output delay constraints from specified ports
Note that to remove the capacitance placed by the set_load command you should use the remove_capacitance command.
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Synchronous Multiple Clock Designs
What is different?A: Multiple clock sources � All derived from the same clock source � Some clocks do not have a corresponding clock port
on our design� Multiple constraints on a single port
CLKA
CLKCCLKBCLKE
CLKDD Q D Q
The_Current_Design
FF2 FF3N X S
What do you do now?
Clocks are said to be synchronous if they are derived from the SAME clock source.
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Answer: Use Virtual Clocks!
What are virtual clocks?
A: Clocks in the environment of the design that:� Are defined as clock objects � Do not clock any sequential devices within the current_design
� Serve as references for input or output delays
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Creating a Virtual Clock
How do you create a virtual clock?
A: It is the same as defining a clock, but you do not specify a clock pin or port:
� You must name your virtual clock, since there is no clock port for the virtual clock
create_clock -name VCLK -period 5.00
No source pin or port!Must be named
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Method for Synchronous Multiple Clocks
Method is the same as that for single clock designs: 1. Define the clock(s), using virtual clocks if necessary2. Specify I/O delays relative to the clock(s):
• PrimeTime will determine which clock imposes the most restrictive constraint on the design by finding Base Period
CLKA
(33 Mhz)
CLKC(50 Mhz) CLKE
(100 Mhz)
CLKD(75 Mhz)D
The_Current_Design
FF2 FF3
N X S
300 MHz
CLKA
CLKD
÷9
÷4
Q D Q
CLKE÷3
÷6 CLKC
Base Period is the Lowest Common Multiple (LCM) of all the clock periods involved. In the above example there are 2 base periods:
For the Input paths: Base period = LCM (20, 30) = 60 nsFor the output paths: Base period = LCM (20, 1000/75, 10) = 40 ns
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NOTE: Do NOT use “13.3” as the clock period for CLKD when you cannot correctly represent it using finite decimals. Use “1000.0/75”. Also, do NOT use “1000/75”, the result will be truncated to integer 13.
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Example Waveforms
For the example shown, output logic cloud of The_Current_Design must meet:
tS < 10 - 4.5
CLKC
CLKD
CLKE
÷4300MHz CLKC
CLKD÷6÷3
CLKE0 10 20 30 40
tS < 6.6 - 2.5AND
6.6
10
26.613.3
What is the Base period?
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Recommendation: Keep the base period smaller than 10 * (the smallest clock period) whenever possible.
� By definition, all clocks used with PT are synchronous:� You can not create asynchronous clocks with create_clock
� PT will determine every possible data launch/data capture time, and perform STA to the most conservative constraint
� This can be very time consuming, when � difference in periods between multiple clocks is large� base period is too large
Hints for Multiple Clock Designs
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Test For Understanding
1. Given 4 synchronous clock periods of: 3, 5, 20, 25 ns:
A) What is the Base period? ______________________________
B) Does this Base period follow our Recommendation, i.e. Tbase < 10 * min (periods)? ___________________________
C) How would this affect the runtime for PT? _______________________________
2. Does it make sense to specify source and network latency for a virtual clock?
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Summary of I/O Path Constraints
set IN_EX_CLK [remove_from_collection \
[all_inputs] [get_ports Clk]]
set LOAD [load_of ssc_core_slow/AN2/A]
set_input_delay -max 1.0 -clock Clk $IN_EX_CLK
set_driving_cell -lib_cell FD2 -pin Q $IN_EX_CLK
set_output_delay -max 2.0 -clock Clk [all_outp]
set_load $LOAD [all_outputs]
redirect io.rpt {report_lib ssc_core_slow}
redirect -append io.rpt {report_port -verbose}
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Lab Overview
� Given a design specification you will constrain all the I/O paths in the design
� You will ensure that all timing paths in the design have been constrained using check_timing
� You will generate timing reports for the longest I/O paths and interpret the effects of your applied I/O constraints
� You will vary the input driving cell, output load and observe their effects on the timing paths
LAB
60 min
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Appendix
Constraining I/O for Hold Time check
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When to Check for Hold Violations
� Small Violations:� Post layout: Check all hold-time violations using best case
operating conditions post-layout because� The clock tree is not in place until after layout� They often disappear when net parasitics are annotated
� Large Violations:� Pre-Layouit: Check only using the worst case operating
conditions for any large hold-time violations pre-layout
My design has met setup requirements.Is it a good time to check for hold?
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Constrain for Hold Time: Input Paths
D Q D Q D Q
QB
D Q
QB
Clk
TO_BE_SYNTHESIZED
FF1 FF2 FF3 FF4M N X S T
set_input_delay -min describes the fastest arrivaltime of the external logic on the input ports.
If FF2 has THOLD = 1ns:What is the min delay allowed for N?
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Constrain for Hold Time: Output Paths
D Q D Q D Q
QB
D Q
QB
Clk
TO_BE_SYNTHESIZED
FF1 FF2 FF3 FF4M N X S T
� set_output_delay -min :� Describes the hold time requirement of the external logic on the
output ports
0.3ns 0.5nsHold TimeRequirement
If FF has THOLD = 0.5ns and TT = 0.3ns:What is the min output delay?
If logic cloud T uses 0.3 ns, you need to have a minimum delay for FF3 (Clk->Q) plus logic cloud S of 0.2 ns in order not to violate the hold time requirement on FF4.
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