Affiah Digital Electronics

CHAPTER ONE

NUMBER SYSTEM AND CODES

INTRODUCTION Number are fundamental to the function and use of computer at all levels

starting from the digital logic level and progressing through the applications level. Numbers are used in arithmetic operation, computer instructions are stored as a series of numbers, it may also be used as codes for letters and special symbols. The collection of unique digits that the computer represent is one component of its number system. Number Systems in use Symbolic number system uses Roman numerals (I = 1, V = 5, X = 10, L = 50, C = 100, D = 500 and M = 1000) still used in some watches. The Weighted position system includes the following; The Decimal system is the most commonly used and Decimal numbers are based on Indian numerals and Radix used is 10. Other weighted position systems are the binary numbers which are most extensively used the Binary system uses radix 2, the octal system which uses radix 8 and the hexa-decimal system which uses radix 16.

1.1 STRUCTURE OF NUMBER SYSTEMS Most modern computers use the binary number system, which has only two digits, 0 and 1. this system is chosen because a computer must be able to represent each digit in some unique manner. Since there are many electronic devices that can represent two unique states: open - closed, high - low, right - left or on - off, binary system is the best for computers. The existence of an area of mathematics know as Boolean algebra, which deals specifically with binary numbers this provides a firm theoretical foundation for the development of computer components. We are acquainted with two different number systems, the Roman and Arabic, each digit in the Roman System always means the same thing e.g. III represents a value three and iv means one less than five but still represents one. The Arabic system differs from the Roman because the locati6ri of Digits to each other is important as well as the position. The number III considered above will represent one hundred and one in th Arabic system which gives a different interpretation altogether when compared with the Roman System. A special zero is needed to indicate positions that are not holding another digit, e.g. the number five hundred and seven (507) will appear as fifty seven (57) without Zero. Each position has a weight or value that depends on the base (or radix) of the number systems. The radix of a number is the same as the base of the decimal number system. For any given radix the minimum number of characters which deals specially with binary numbers is another reason for choosing binary system that can be found in any given combination is equal to the radix.

1 Digital Systems. An Introductory Perspective.

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Examples (i) Radix 10 :. 0, 1,2,3,4,5,6, 7, 8, 9 (ii) Radix 8 : - 0, 1,2,3,4, 5, 6, 7 (iii) Radix 2 :- 0, 1 (iv) Radix 16 :- 0, 1,2,3,4, 5, 6, 7, 8, 9, A, B, C, D, E, F.

We use the decimal, or base 10 system in our day to day lives. The Arabic type number system have as many unique digits, including zero, as magnitude of base, but there is never a single digit equal to the base. Number system .

1.2 NUMBER SYSTEM1.2a Binary System

The binary system is generally employed in digital. equipment in order to simplify circuit design. As the binary system is based on powers of two there are only two digits 0 and 1. this implies that the equipment recognizes only two states as stated in section 1.1. The position of a 1- digit in a binary number determines its weighting value, example; a 4 - digit binary number 1111 has the following meaning:

The binary member 1111 = decimal member (8+4+2+ 1) = 15. The example we just considered uses a positive power of the base, for those whose weight are

1 2negative powers of the base we have (2- ,2- , etc.) which is very useful in determining the decimal value of a binary fraction, example; determining the decimal value of 0. 011 will give 0. 0 1 1

-31 of 2 = 1 x l = 0. 1 25 8

-21 of 2 = 1 x1= 0.250 4

-10 of 2 = (1) X 1 = 0. 0001 2

The binary number 0. 011 = decimal number (0.125 + 0.250) = 0.375 Each binary digit in a binary number is referred to as a bit. The sequence of 4 bits is known as a nibble. 0010, 1010, 1111 are all nibbles. A group of8 bits is known as a byte, e.g. 00011010, and 11100101. The number of bits used to convey data in

o o 1of 2 = 1x2 = 1 1 1 1of 2 = 1x2 = 2

2 2 1of 2 = 1x2 = 4 3 3 1of 2 = 1x2 = 8

2

1 1 1 1

Digital Systems. An Introductory Perspective.

a computer or microprocessor is known as a world length. Micro processor based computers user a world length of a byte, simple microprocessors uses 1 nibble, which then latest uses 2 bytes . Mainframe computers uses 24 to 60 bit word length. Consider a nibble say 1111, the right hand bit has the least weighting known as the least significant bit (LSB), the left hand having the most weighting and is YJ"lown as the most significant bit, (MSB). As we program from right to left there is an increment in the weighting value in power of 2 as in example (1).

1.3.1 Basic Binary ArithmeticArithmetic operations using binary numbers are far simpler than the corresponding operations using decimal numbers due to the very elementary rules of addition and multiplication. The rules of binary addition are

0 + 0 = 00+ 1 = 11+ 0 = 11 + 1 = 0 (carry 1)

As in decimal addition, the least significant bits of the addend and the augend are added first. The result is the sum, possibly including a carry. The carry bit is added to the sum of the digits of the next column. The process continues until the bits of the most significant column are summed.Example 1.6 Let us consider the addition of the decimal numbers 27 and 28 in binary.

Decimal Binary27 11011 Addend

+28 +11100 Augend55 110111 Sum

11000 Carry

To verify that the sum is correct, we convert 110111 to decimal:5 4 3 2 1 01 x 2 + 1 x 2 + 0 x 2 + 1 x 2 + 1 x 2 + 1 x 2

= 32 + 16 + 0 + 4 + 2 + 1= 5


Example 1.7 Let us add 11 to 19 in binary. Since the addend and the augend arenegative, the sum will be negative.

Decimal Binary19 1001111 0101130 11110 Sum

00011 CarryIn all digital systems, the circuitry used for performing binary addition handles two numbers at a time. When more than two numbers have to be added, the first two are added, then the resulting sum is added to the third number, and so on.Binary subtraction is carried out by following the same method as in the decimalsystem. Each digit in the subtrahend is deducted from the corresponding digit in the minuend to obtain the difference. When the minuend digit is less than the subtrahend digit, then the radix number (i.e., 2) is added to the minuend, and a borrow 1 is added to the next subtrahend digit. The rules applied to the binary subtraction are

0 - 0 = 00 - 1 = 1 (borrow 1)1 - 0 = 11 - 1 = 0

Example 1.8 Let us consider the subtraction of 2110 from 2710 in binary:Decimal Binary27 11011 Minuend21 10101 Subtrahend 6 00110 Difference

00100 BorrowIt can easily be verified that the difference 00110 corresponds to decimal 6.2Example 1.9 Let us subtract 2210 from 1710. In this case, the subtrahend is greater than the minuend. Therefore the result will be negative.

Decimal Binary17 1000122 10110 5 00101 Difference

00001 Borrow


Binary multiplication is performed in the same way as decimal multiplication, by multiplying, then shifting one place to the left, and finally adding the partial products. Since the multiplier can only be 0 or 1, the partial product is either zero or equal to the multiplicand. The rules of multiplication are

0 0 = 00 1 = 01 0 = 01 1 = 1

Example 1.10 Let us consider the multiplication of the decimal numbers 67 by 13 in binary:

Decimal Binary67 1000011 Multiplicand

x13 1101 Multiplier871 1000011 First partial product

0000000 Second partial product 1000011 Third partial product 1000011 Fourth partial product 1101100111 Final product

Example 1.11 Let us multiply 13.5 by 3.25.Decimal Binary13.5 1101.10 Multiplicand

x3.25 11.01 Multiplier 43.875 110110 First partial product

000000 Second partial product 110110 Third partial product 110110 Fourth partial product 101011.1110 Final product

The decimal equivalent of the final product is 43 0.50 0.25 0.125 43.875.The process of binary division is very similar to standard decimal division. However, division is simpler in binary because when one checks to see how many times the divisor fits into the dividend, there are only two possibilities, 0 or 1.Example 1.12 Let us consider the division of 101110 (4610) by 111 (710)


0001 QuotientDivisor 111 101110 Dividend

0111 100

Since the divisor, 111, is greater than the first three bits of the dividend, the first three quotient bits are 0. The divisor is less than the first four bits of the dividend; therefore the division is possible, and the fourth quotient bit is 1. The difference is less than the divisor, so we bring down the net bit of the dividend:

00011111 101110 0111

1001 111 10

The difference is less than the divisor, so the next bit of the dividend is brought down:

000110111 101110

0111 1001 111 100 Remainder

In this case the dividend is less than the divisor; hence the next quotient bit is 0 and the division is complete. The decimal conversion yields 46/7 = 6 with remainder 4, which is correct. The methods we discussed to perform addition, subtraction, multiplication, and division are equivalents of the same operations in decimal. In digital systems, all arithmetic operations are carried out in modified forms; in fact, they use only addition as their basic operation.

direct input output operation

Digital systems operate only on binary numbers.

1.2 b Octal System This is a base eight number system widely used in computer techniques. Its useful properties includes that of simplicity in converting from binary to octal and vice versa, and easy Con ersion from binary to octal beings with the separation of the binar number into groups of three bits starting at the radix point

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.


of bits required to represent an octal digit is three. For example, octal 7 can be represented by binary 111. Thus, if each octal digit is written as a group of three bits, the octal number is converted into a binary number.Example 1.15 the octal number 3248 can be converted to a binary number as follows:

3 2 4

011 010 100

Hence 324 =110101002; the most significant 0 is dropped because it is 8meaningless, just as 0123 is the same as 123 .10 10The conversion from binary to octal is also straightforward. The binary number is partitioned into groups of three starting with the least significant digit. Each group of three binary digits is then replaced by an appropriate decimal digit between 0 and 7 see table 1.2.

Table 1.2 Binary to Octal ConversionBinary Octal 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7

Example 1.16. Let us convert 1100111010012 to octal:

6 3 5 1110 011 101 001

The octal representation of the binary number is 6351 . If the leftmost group of a 8partitioned binary number does not have three digits, it is padded on the left with 0's.


For example, 1101010 would be divided as001 1101 5010 2

The octal equivalent of the binary number is 1528. In case of a binary fraction, if the bits cannot be grouped into 3-bit segments, the 0's are added on the right to complete groups of three. Thus 110111.1011 can be written

110 6111 7101 5100 4

As shown in the previous section, the binary equivalent of a decimal number can be obtained by successively dividing the number by 2 and using the remainders as the answer, the first remainder being the lowest significant bit, and so on. A large number of divisions by 2 are required to convert from decimal to binary if the decimal number is large. It is often more convenient to convert from decimal to octal and then replace each digit in octal in terms of three digits in binary. For example, let us convert 523 to binary by going through octal.10

523/8 = 65, remainder 365/8 = 8, remainder 18/8 = 1, remainder 01/8 = 0, remainder 1Thus,

(523) = ( 1 0 1 3)10 8

= (001 000 001 011)2It can be verified that the decimal equivalent of 0010000010112 is 523 :10

9 3 1 01 x2 + 1 x 2 +1 x 2 + 1 x 2 = 512 + 8 + 2 + 1= 52310

Addition and subtraction operations using octal numbers are very much similar to that use in decimal systems. In octal addition, a carry is generated when the sum exceeds 710.


For example,153 + 327 = 5028 8 8

3 + 7 = 10 = 2 + 1 carry first column105 + 2 + 1 carry =0 + 1 carry second column1 + 3 + 1 carry = 5 third column

In octal subtraction, a borrow requires that 810 be added to the minuend digit and a 110 be added to the left adjacent subtrahend digit.670 - 125 = 5438 8 8

0 - 5 = (8 - 5 + 1 borrow) = 3 + 1 borrow first column107 - (2 + 1 borrow) = 7 - 3 = 4 second column6 - 1 = 5 third column

The octal number system has three bit digit representation and is one common solution to the problems with binary numbers. Another solution involves using a four bit pattern; this requires a digit for each of the 2 x 2x 2 x 2 or 16 possible bit pattern. The radix here 16 and the system is known as hexadecimal or hex. The least significant digit in front of the hexadecimal point is weighted 16= 1, the

2next is 16 etc. successive as follows -116 = 1/16-216 = 1/256-316 = 1/4096 etc.

The hexadecimal numbering system has a base 16; that is, there are 16 symbols. The decimal digits 0 to 9 are used as the first ten digits as in the decimal system, followed by the letters A, B, C, D, E, and F, which represent the values 10, 11, 12, 13, 14, and 15, respectively. Table 1.3 shows the relationship between decimal, binary, octal, and hexadecimal number systems. The conversion of a binary number to a hexadecimal number consists of partitioning the binary numbers into groups of 4 bits, and representing each group with its hexadecimal equivalent.

1.2c Hexadecimal Number System


Table 1.2 Number Equivalents

Decimal Binary Octal Hexadecimal0 0000 0 01 0001 1 12 0010 2 23 0011 3 34 0100 4 45 0101 5 56 0110 6 67 0111 7 78 1000 10 89 1001 11 910 1010 12 A11 1011 13 B12 1100 14 C13 1101 15 D14 1110 16 E15 1111 17 F


Using the digits available in the decimal system will give a problem in this hex notation countering the fact that we do not write double figures in the range between 10 and 15, instead we assign the first six letters of the alphabet giving the following; 10 is replaced by A, 11 by B, 12 by C, 13 by D, 14 by E and 15 by F. All the possible combination of four bits with their decimal and hexadecimal equivalent is show in the table 1.2 below.

12

Bit pattern Hexadecimal 0000 0 0 0001 I I 0010 2 2

0011 3 3 0100

4

4 0101

5

5 0110

6

6 0111

7

7 1000

8

8 1001

9

9 1010

10

A 1011

11

B 1100 12 C 1101 13 D 1110 14 E 1111 15 F

Decimal


Examples Binary to hexadecimal conversion

1. convert the following binary into hexadecimal 1011101010010010

Solution 1011 1010 1001 0010 Binary

B A 9 2 Hex

Hence 1011101010010010 = Ba 922 16

2. Convert (567. 1875)10 to Hexadecimal

Solutions Integer Part Fractional part

0.1875 x 16 = 3.0000

16 567 35 r.7

16 35 2 r.3

16 2 0 r.2

Hence (567. 1875) = (237 . 3)10 16

3. Convert 26810 to Hex Solution Solution 16 268 16 16 r.12 = C 16 12 r.0

0 r.1

So 268 = 10 10 16


1.2d Fixed and Floating Point Numbers. All the numbers considered up till now is based on the assumption that they are whole numbers. This is called fixed point notation and used to indicate that the binary point is fixed at the position where the power of the base 2 weighting

-1changes from positive to negative i.e at the point between 2 and 2 bits. Examples of fixed-point binary numbers are

01101111=11110 and 01100 111.101 = 103.625 . 10

In representing very large and very small numbers we employ scientific notation, for instance a number say 0.000000123456789 would be represented

6by 0.123457 x 10 . Notice only six digits are listed and the sixth digit is rounded. The number

of digits displayed in scientific notation is called the precision of the number.The computer version of scientific notation is called floating point. In

general floating point representation of a number to any base may be written in form;

+en = + m b Where e in the exponent m is the mantissa and b is the base

1.2e Negative Numbers Negative number are represented by adding a dash or minus sign to the

left of the number as in -2468.0ther approaches places the dash in the right as in 2468 -, or put parenthesis around negative numbers as in (2468). This approach is called signed magnitude method and can be adopted for use with any number system.

Since there are only two possible signs, the sign can be represented by a single bit. As with the sign - and- magnitude, the most significant bit (MSB) of the number is used as the sign bit; MSB is 0 for positive number and 1 for negative number.

The signed magnitude representation has limitations. It is not possible to perform basic arithmetic operations with positive and negative numbers and automatically provide the correct sign for theresult. For example the decimal expression 9 4 by the laws of arithmetic can be represented by 9 + (- 4) which implies the following


9 =+(-4) = 10000100

1000 II 0 I = -13

Hence addition of sign plus magnitude can produce an incorrect result. The method representing negative numbers that will lead to the desired

arithmetic results are the radix complement (2's complement in the binary system) and the diminished radix complement (1 's complement) methods.

One's complement of a binary number is formed by flipping all of its bits. Every one bit in the original number is changed to a zero, and every zero to a one. This results in the original number but with an opposite sign, for example 0 10010101 is (l06 ) will produce 01101010 or (-106 ) As with signed 2 10 10magnitude numbers the MSB is a sign bit.

Considering our example again, the result from 9 - 4 i.e. (9 + ( - 4) will now be

00001001 11111011100000100

Carry

Something seem to be wrong because the answering is still not five, it has one more bit than the original number. The extra bit is called a carry and is when it is generated during one's complement it must be moved from the high end to the low end of the number Hence

1 0 0 0 0 01 0 0 + 14

0 0 0 0 0 1 0 1This operation is called end round early and is necessary for the production of the correct answer in one's complement arithmetic. One's complement has a problem of alternate representation of zeros.

00001001

2


To correct the problem above we create two's complement of numbers. This is done by flipping all the bits as with one's complement and adding 1 to the result. For example positive five in binary is 00000101 , flipping the bits produces 211111010 , which is -510 in two's complement. In the two's complement 2arithmetic the carry in ignored.

1. 3 Codes and Their Conversions: Digital circuits use binary signals but are required to handle data which may be alphabetic, numeric, or special characters. Hence the signals that are available in some other form other than binary have to be converted into suitable binary form before they can be processed further by digital circuits. This means that in whatever format the information may be available it must be converted into binary format. To achieve this, a process of coding is required where each letter, special character, or numeral is coded in a unique combination of 0s and 1s using a coding scheme known as code. In digital systems a variety of codes are used to serve different purposes, such as data entry, arithmetic operation, error detection and correction, etc. Selection of a particular code depends on the requirement. Even in a single digital system a number of different codes may be used for different operations and it may even be necessary to convert data from one type of code to another. For conversion of data, code converter circuits are required, which will be discussed in due time. Codes can be broadly classified into five groups, viz. (i) Weighted Binary Codes, (ii) Non weighted Codes, (iii) Error-detection Codes, (iv) Error-correcting Codes, and (v) Alphanumeric Codes.

1.3.1. Codes: Various binary codes are used to represent data which may be numeric, alphabetic or special characters. Codes are also used for error detection and error correction in digital systems. Although, in digital systems in every code used, the information is represented in binary form, but the interpretation of the data is only possible if the code in which the data is being represented is known. For example, the binary number 1000010 represents 66 (decimal) in straight binary, 42 (decimal) in BCD, and letter B in ASCII code. Hence, while interpreting the data, one must be very careful regarding the code used.

1.3.1a. Weighted Binary CodesIf each position of a number represents a specifi c weight then the coding scheme is called weighted binary code. In such coding the bits are multiplied by their corresponding individual weight, and then the sum of these weighted bits gives the equivalent decimal digit.


BCD Code or 8421 Code The full form of BCD is Binary-Coded Decimal. Since this is a coding scheme relating decimal and binary numbers, four bits are required to code each decimal number. For example, (35)10 is represented as 0011 0101 using BCD code, rather than (100011) . From the example it is clear 2that it requires more number of bits to code a decimal number using BCD code than using the straight binary code. However, in spite of this disadvantage it is convenient to use BCD code for input and output operations in digital systems. The code is also known as 8-4-2-1 code. This is because 8, 4, 2, and 1 are the weights of the four bits of the BCD code. The weight of the LSB is 20 or 1, that of the next higher order bit is 21 or 2, that of the next higher order bit is 22 or 4, and that of the MSB is 23 or 8. Therefore, this is a weighted code and arithmetic operations can be performed using this code, which will be discussed later on. The bit assignment 0101, for example, can be interpreted by the weights to represent the decimal digit 5 because 0 8 + 1 4 + 0 2 + 1 1 = 5. Since four binary bits are used the maximum decimal equivalent that may be coded is 1510 (i.e., 11112). But the maximum decimal digit available is 910. Hence the binary codes 1010, 1011, 1100, 1101, 1110, 1111, representing 10, 11, 12, 13, 14, and 15 in decimal are never being used in BCD code. So these six codes are called forbidden codes and the group of these codes is called the forbidden group in BCD code. BCD code for decimal digits 0 to 9 is shown in Table 1.1.

Example 1.1. Give the BCD equivalent for the decimal number 589.Solution. The decimal number is 589BCD code is 0101 1000 1001Hence, (589)10 = (010110001001)BCD

Example 2.2. Give the BCD equivalent for the decimal number 69.27.Solution. The decimal number 6 9 2 7

BCD code is 0110 1001 0010 0111Hence, (69.27)10 = (01101001.00100111)BCD

84-2-1 CodeIt is also possible to assign negative weights to decimal code, as shown by the 84-2-1 code. In this case the bit combination 0101 is interpreted as the decimal digit 3, as obtained from 0 8 + 1 4 + 0 (2) + 1 (1) = 3.


This is a self-complementary code, that is, the 9s complement of the decimal number is obtained just by changing the 1s to 0s and 0s to 1s, or in effect by getting the 1s complement of the corresponding number. For example, if we change the 1s to 0s and 0s to 1s in the previous example we have 1010, which is interpreted as decimal 6, as obtained from 1 8 + 0 4 + 1 (2) + 0 (1) = 6. And 6 is the 9s complement of 3. This property is useful when arithmetic operations are done internally with decimal numbers (in a binary code) and subtraction is calculated by means of 9s complement.

2421 CodeAnother weighted code is 2421 code. The weights assigned to the four digits are 2, 4, 2, and 1. The 2421 code is the same as that in BCD from 0 to 4; however, it varies from 5 to 9. For example, in this case the bit combination 0100 represents decimal 4; whereas the bit combination 1101 is interpreted as the decimal 7, as obtained from 2 1 + 1 4 + 0 2 + 1 1 = 7. This is also a self-complementary code, that is, the 9s complement of the decimal number is obtained by changing the 1s to 0s and 0s to 1s. The 2421 codes for decimal numbers 0 through 9 are shown in Table 2.1.

1.3.1b. Nonweighted CodesThese codes are not positionally weighted. It basically means that each position of the binary number is not assigned a fi xed value. Excess-3 codes and Gray codes are such non-weighted codes.

Excess-3 CodeA decimal code that has been used in some old computers is Excess-3 code. This is a non weighted code. This code assignment is obtained from the corresponding value of 4-bit binary code after adding 3 to the given decimal digit. Here the maximum value may be 11002. Since the maximum decimal digit is 9 we have to add 3 to 9 and then get the BCD equivalent. Like 84-2-1 and 2421 codes Excess-3 is also a self-complementary code, that is, the 9s complement of the decimal number is obtained by changing the 1s to 0s and 0s to 1s. This self-complementary property of the code helps considerably in performing subtraction operation in digital systems.


2421 codes Excess-3 is also a self-complementary code, that is, the 9s complement of the decimal number is obtained by changing the 1s to 0s and 0s to 1s. This self-complementary property of the code helps considerably in performing subtraction operation in digital systems.

Example 1.3. Convert (367)10 into its Excess-3 code.Solution. The decimal number is 3 6 7Add 3 to each bit i.e 3 +3, 6 +3 and 7 +3The sum now implies 6 9 and 10Converting the above sum into 4-bit binary equivalent, we have an 4-bit binary equivalent of 0110 1001 1010 implying 6 = 0110, 9 = 1001 and 10 = 1010Hence, the Excess-3 code for (367)10 = 0110 1001 1010

Example 1.4. Convert (58.43)10 into its Excess-3 code.Solution. The decimal number is 5 8 4 3Add 3 to each bit +3 +3 +3 +3 will produce the sum 8 11 7 6Converting the above sum into 4-bit binary equivalent, we have a 4-bit binary equivalent of 1000 1011 0111 0110Hence, the Excess-3 code for (367)10 = 10001011.01110110

Decimal digit (BCD)8421 84-2-1 2421 Excess-3 0 1 2 3 4 5 6 7

0000

0001

0010

0011

0100

0101

0110

0111

0000

0111

0110

0101

0100

1011

1010

1001

0000

0001

0010

0011

0100

1011

1100

1101

0011

0100

0101

0110

0111

1000

1001

1010

8

9 1000

1001 1000

1111 1110

1111 1011

1100

Table 1.1 Decimal digits and their Binary codes


Gray CodeThe Gray code was designed by Frank Gray at Bell Labs and patented in 1953. It is an un-weighted binary code in which two successive values differ only by 1 bit. Owing to this feature, the maximum error that can creep into a system using the binary Gray code to encode data is much less than the worst-case error encountered in the case of straight binary encoding. Table 1.2 lists the binary and Gray code equivalents of decimal numbers 015. An examination of the four-bit Gray code numbers, as listed in Table 1.2, shows that the last entry rolls over to the first entry. That is, the last and the first entry also differ by only 1 bit. This is known as the cyclic property of the Gray code. Although there can be more than one Gray code for a given word length, the term was first applied to aspecific binary code for non-negative integers and called the binary-reflected Gray code or simply the Gray code. There are various ways by which Gray codes with a given number of bits can be remembered. One such way is to remember that the least significant bit follows a repetitive pattern of 2 (11, 00, 11,.... ), the next higher adjacent bit follows a pattern of 4 (1111, 0000, 1111, ....) and soon. We can also generate the n-bit Gray code recursively by prefixing a 0 to the Gray code for n-1 bits to obtain the first 2n-1 numbers, and then prefixing 1 to the reflected Gray code for n-1 bits to obtain the remaining 2n-1 numbers. The reflected Gray code is nothing but the code written in reverse order.

1.3.2 BinaryGray Code /Gray - Binary ConversionBinaryGray Code ConversionA given binary number can be converted into its Gray code equivalent by going through the following steps:1. Begin with the most significant bit (MSB) of the binary number. The MSB of the Gray code equivalent is the same as the MSB of the given binary number.2. The second most significant bit, adjacent to the MSB, in the Gray code number is obtained by adding the MSB and the second MSB of the binary number and ignoring the carry, if any. That is, if the MSB and the bit adjacent to it are both 1, then the corresponding Gray code bit would be an0.3. The third most significant bit, adjacent to the second MSB, in the Gray code number is obtained by adding the second MSB and the third MSB in the binary number and ignoring the carry, if any.4. The process continues until we obtain the LSB of the Gray code number by the addition of the LSB and the next higher adjacent bit of the binary number. The conversion process is further illustrated with the help of an example showing step-by-step conversion of (1011)2 into its Gray code equivalent:


Binary 1011Gray code 1- - -Binary 1011Gray code 11- -Binary 1011Gray code 111-Binary 1011Gray code 1110

Gray CodeBinary ConversionA given Gray code number can be converted into its binary equivalent by going through the following steps:1. Begin with the most significant bit (MSB). The MSB of the binary number is the same as the MSBof the Gray code number.

Decimal numbers Binary code Gray code

0 0000 0000 1 0001 0001 2 0010 0011 3 0011 0010 4 0100 0110 5 0101 0111 6 0110 0101 7 0111 0100 8 1000 1100 9 1001 1101 10 1010 1111 11 1011 1110 12 1100 1010 13 1101 1011 14 1110 1001 15 1111 1000

Table 1.2 Binary and Gray codes


2. The bit next to the MSB (the second MSB) in the binary number is obtained by adding the MSB in thebinary number to the second MSB in the Gray code number and disregarding the carry, if any.3. The third MSB in the binary number is obtained by adding the second MSB in the binary number to the third MSB in the Gray code number. Again, carry, if any, is to be ignored.4. The process continues until we obtain the LSB of the binary number. The conversion process is further illustrated with the help of an example showing step-by-stepconversion of the Gray code number 1110 into its binary equivalent:Gray code 1110Binary 1- - -Gray code 1110Binary 10 - -Gray code 1110Binary 101Gray code 1110Binary 1011

2.3.4 Applications1. The Gray code is used in the transmission of digital signals as it minimizes the occurrence of errors.2. The Gray code is preferred over the straight binary code in angle-measuring devices. Use of the Gray code almost eliminates the possibility of an angle misread, which is likely if the angle is represented in straight binary. The cyclic property of the Gray code is a plus in this application.3. The Gray code is used for labeling the axes of Karnaugh maps, a graphical technique used for minimization of Boolean expressions.4. The use of Gray codes to address program memory in computers minimizes power consumption. This is due to fewer address lines changing state with advances in the program counter.5. Gray codes are also very useful in genetic algorithms since mutations in the code allow for mostly incremental changes. However, occasionally a one-bit change can result in a big leap, thus leading to new properties.


Example 2.5. Convert (101011)2 into Gray code.Solution.Step 1. The MSB of the Gray code is the same as the MSB of the binary number.1 0 1 0 1 1 Binary1 GrayStep 2. Perform the ex-OR between the MSB and the second bit of the binary. The result is 1, which is the second bit of the Gray code.1 0 1 0 1 1 Binary1 1 GrayStep 3. Perform the ex-OR between the second and the third bits of the binary. The result is 1, which is the third bit of the Gray code.1 0 1 0 1 1 Binary1 1 1 GrayStep 4. Perform the ex-OR between the third and the fourth bits of the binary. The result is 1, which is the fourth bit of the Gray code.1 0 1 0 1 1 Binary1 1 1 1 GrayStep 5. Perform the ex-OR between the fourth and the fi fth bits of the binary. The result is 1, which is the fi fth bit of the Gray code.1 0 1 0 1 1 Binary1 1 1 1 1 GrayStep 6. Perform the ex-OR between the fi fth and the sixth bits of the binary. The result is 0, which is the last bit of the Gray code.1 0 1 0 1 1 Binary1 1 1 1 1 0 GrayAfter completing the conversion the Gray code of binary 101011 is 111110

Example 2.6. Convert (564)10 into Gray code.Solution.Step 1. Convert the decimal 564 into equivalent binary.Decimal number 564Binary number 1000110100Step 2. The reader should try to Convert the binary number into equivalent Gray code using the method used I example 2.5 above.

+

+

+

+

+


Example 2.7. Convert the Gray code 101101 into a binary number.Solution.Step 1. The MSB of the binary number is the same as the MSB of the Gray code.1 0 1 1 0 1 Gray1 BinaryStep 2. Perform the ex-OR between the MSB of the binary number and the second bit of the Gray code. The result is 1, which is the second bit of the binary number.1 0 1 1 0 1 Gray1 1 BinaryStep 3. Perform the ex-OR between the second bit of the binary number and the third bit of the Gray code. The result is 0, which is the third bit of the binary number.1 0 1 1 0 1 Gray therefore implies 1 1 0 Binary.

Example 2.4Find (a) the Gray code equivalent of decimal 13 and (b) the binary equivalent of Gray code number 1111.Solution(a) The binary equivalent of decimal 13 is 1101.BinaryGray conversionBinary 1101Gray 1- - -Binary 1101Gray 10 - -Binary 1101Gray 101 Binary 1101Gray 1011(b) Graybinary conversionGray 1111Binary 1- - -Gray 1111Binary 10- -Gray 1111Binary 101-Gray 1111Binary 1010


1.3.3 Alphanumeric CodesMany applications of the computer require not only handling of numbers, but also of letters. To represent letters it is necessary to have a binary code for the alphabet. In addition, the same binary code must represent the decimal numbers and some other special characters. An alphanumeric code is a binary code of a group of elements consisting of ten decimal digits, the 26 letters of the alphabet (both in uppercase and lowercase), and a certain number of special symbols such as #, /, &, %, etc. The total number of elements in an alphanumeric code is greater than 36. Therefore it must be coded with a minimum number of 6 bits (26 = 64, but 25 = 32 is insufficient). One possible 6-bit alphanumeric code is given in Table 2.5. It is used in many computers to represent alphanumeric characters and symbols internally and therefore can be called internal code. Frequently there is a need to represent more than 64 characters, including the lowercase letters and special control characters. For this reason the following two codes are normally used are; ASCII: The full form of ASCII (pronounced as-kee) is American Standard Code for Information Interchange, used in most microcomputers. It is actually a 7-bit code, where a character is represented with seven bits. The character is stored as one byte with one bit remaining unused. But often the extra bit is used to extend the ASCII to represent an additional 128 characters. Some of the codes are shown in Appendix 1.EBCDIC: The full form of EBCDIC is Extended Binary Coded Decimal Interchange Code. It is also an alphanumeric code generally used in IBM equipment and in large computers for communicating alphanumeric data. For the different alphanumeric characters the code grouping in this code is different from the ASCII code. It is actually an 8-bit code and a ninth bit is added as the parity bit. See appendix 2.

1.3.4 Hollerith CodeGenerally this code is used in punched cards. A punched card consists of 12 rows and 80 columns. An alphanumeric character is represented by each column of 12 bits each by punching holes in the appropriate rows. The presence of a hole represents a 1 and its absence indicates 0. The 12 rows are marked starting from the top, as 12, 11, 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. The fi rst three rows


are called the zone punch and the last nine are called the numeric punch. The code used here is called the Hollerith code. The letters are represented as twoholes in a column, one in zone punch and the other in numeric punch; decimal digits are represented as a single hole in a numeric punch. Special characters are represented as one, two, or three holes in a column; while the zone is always used, the other two holes, if used, are in a numeric punch with the eighth punch being commonly used. The Hollerith code is BCD and hence the transition from EBCDIC is simple. The Hollerith code is used in the card readers and punches of large computers, while EBCDIC may be used within the computer.

1.3.5 Error Detection and Correction CodesWhen we talk about digital systems, be it a digital computer or a digital communication set-up, the issue of error detection and correction is of great practical significance. Errors creep into the bit stream owing to noise or other impairments during the course of its transmission from the transmitter to the receiver. Any such error, if not detected and subsequently corrected, can be disastrous, as digital systems are sensitive to errors and tend to malfunction if the bit error rate is more than a certain threshold level. Error detection and correction, as we will see below, involves the addition of extra bits, called checkbits, to the information-carrying bit stream to give the resulting bit sequence a unique characteristic that helps in detection and localization of errors. These additional bits are also called redundant bits as they do not carry any information. While the addition of redundant bits helps in achieving the goal of making transmission of information from one place to another error free or reliable, it also makes it inefficient. In this section, we will examine some common error detection and correction codes. 1.3.6 Parity CodeA parity bit is an extra bit added to a string of data bits in order to detect any error that might have crept into it while it was being stored or processed and moved from one place to another in a digital system. We have an even parity, where the added bit is such that the total number of ls in the data bit string becomes even, and an odd parity, where the added bit makes the total number of ls in the data bit string odd. This added bit could be a 0 or a 1. As an example, if we have to add an even parity bit to 01000001 (the eight-bit ASCII code for A), it will be a 0 and the number will become 001000001. If we have to add an odd parity bit to the same number, it will be a l and the number will become 101000001.


The odd parity bit is a complement of the even parity bit. The most common convention is to use even parity, that is, the total number of 1s in the bit stream, including the parity bit, is even. The parity check can be made at different points to look for any possible single-bit error, as it would disturb the parity. This simple parity code suffers from two limitations. Firstly, it cannot detect the error if the number of bits having undergone a change is even. Although the number of bits in error being equal to or greater than 4 is a very rare occurrence, the addition of a single parity cannot be used to detect two-bit errors, which is a distinct possibility in data storage media such as magnetic tapes. Secondly, the single-bit parity code cannot be used to localize or identify the error bit even if one bit is in error. There are several codes that provide self-single-bit error detection and correction mechanisms, and these are discussed below.

1.3.7 Repetition CodeThe repetition code makes use of repetitive transmission of each data bit in the bit stream. In the case of threefold repetition, 1 and 0 would be transmitted as 111 and 000 respectively. If, in the received data bit stream, bits are examined in groups of three bits, the occurrence of an error can be detected. In the case of single-bit errors, 1 would be received as 011 or 101 or 110 instead of 111, and a 0 would be received as 100 or 010 or 001 instead of 000. In both cases, the code becomes self-correcting if the bit in the majority is taken as the correct bit. There are various forms in which the data are sent using the repetition code. Usually, the data bit stream is broken into blocks of bits, and then each block of data is sent some predetermined number of times. For example, if we want to send eight-bit data given by 11011001, it may be broken into two blocks of four bits each. In the case of threefold repetition, the transmitted data bit stream would be 110111011101100110011001. However, such a repetition code where the bit or block of bits is repeated 3 times is not capable of correcting two-bit errors, although it can detect the occurrence of error. For this, we have to increase the number of times each bit in the bit stream needs to be repeated. For example, by repeating each data bit 5 times, we can detect and correct all two-bit errors. The repetition code is highly inefficient and the information throughput drops rapidly as we increase the number of times each data bit needs to be repeated to build error detection and correction capability.


1.3.8 Cyclic Redundancy Check CodeCyclic redundancy check (CRC) codes provide a reasonably high level of protection at low redundancy level. The cycle code for a given data word is generated as follows. The data word is first appended by a number of 0s equal to the number of check bits to be added. This new data bit sequence is then divided by a special binary word whose length equals n+1, n being the number of check bits to be added. The remainder obtained as a result of modulo-2 division is then added to the dividend bit sequence to get the cyclic code. The code word so generated is completely divisible by the divisor used in the generation of the code. Thus, when the received code word is again divided by the same divisor, an error-free reception should lead to an all 0 remainder. A nonzero remainder is indicative of the presence of errors. The probability of error detection depends upon the number of check bits, n, used to construct the cyclic code. It is 100 % for single-bit and two-bit errors. It is also 100 % when an odd number of bits are in error and the error bursts have a length less than n + 1. The probability of detection reduces to 1 (1/2)n-1 for an error burst length equal to n + 1, and to 1 (1/2)n for an error burst length greater than n + 1.

1.3.9 Hamming CodeWe have seen, in the case of the error detection and correction codes described above, how an increase in the number of redundant bits added to message bits can enhance the capability of the code to detect and correct errors. If we have a sufficient number of redundant bits, and if these bits can be arranged such that different error bits produce different error results, then it should be possible not only to detect the error bit but also to identify its location. In fact, the addition of redundant bits alters the distance code parameter, which has come to be known as the Hamming distance. The Hamming distance is nothing but the number of bit disagreements between two code words. For example, the addition of single-bit parity results in a code with a Hamming distance of at least 2. The smallest Hamming distance in the case of a threefold repetition code would be 3. Hamming noticed that an increase in distance enhanced the codes ability to detect and correct errors. Hammings code was therefore an attempt at increasing the Hamming distance and at the same time having as high an information throughput rate as possible.The Hamming code is capable of correcting single-bit errors on messages of any length. Although the Hamming code can detect two-bit errors, it cannot give the error locations. The number of parity bits required to be transmitted along with the message, however, depends


upon the message length, as shown above. The number of parity bits n required to encode m message bits is the smallest integer that satisfies the condition (2n n > m.


Self Test Questions 1.

7. Express the following decimal numbers in Excess-3 code form:(a) 245, (b) 739, (c) 4567, and (d) 532.

8. Express the following Excess-3 codes as decimals:(a) 100000110110, (b) 0111110010010110, and 110010100011.

9. Convert the following binary numbers to Gray codes:(a) 10110, (b) 1110111, (c) 101010001, and (d) 1001110001110.

10. Express the following decimals in Gray code form:(a) 5, (b) 27, (c) 567, and (d) 89345.

11. Write your first name and last name in an 8-bit code made up of the seven ASCII bits and an odd parity bit in the most significant position. Include blanks between names.12. Express the following decimals in (1) 2,4,2,1 code and (2) 8, 4, 2, 1 code form: (a) 35, (b) 7, (c) 566, and (d) 8945.13. What is the difference between ASCII and EBCDIC codes? Why are EBCDIC codes used?14. Why is Gray code called the reflected code? Explain.

1. What is (a)(i) The radix of a number system and why is it important? (ii) A radix pont

(b) Why are 'complements' used to represent negative numbers. Why is complements used in place of sign plus magnitude to represent negative number? (c) Using one's complement arithmetic subtract the binary equivalent of 18 from 25 giving the final decimal result. Show all steps necessary. 3. Explain two advantage or disadvantages of binary coded decimal numbers over true binary numbers 4. Convert

(i) The following decimal numbers to binary numbers (a) 12.12 (b) 137 (ii) The following hexadecimal numbers to binary numbers

(a) 33FB (b) A047 (c) FDB8 (d) 2C9E (iii) The following numbers into decimal

(a) 11118 (b) FFEE Eb hex hex(iv) Represents the following 8421 BED codes to decimal numbers. (i) 1000011000000001 (ii) 010001010111 ,

6. Translate the following ASCII codes into English 476F644C 75636B.


CHAPTER TWO INTRODUCTION TO LOGIC GATES

2, 1 Diodes and Transistors are made from 8emiconductors, so called because they lie between the metals aud insulators in their ability to conduct electricity. Germanium and silicon are the most Popular semiconductors because of their use and are hard, brittle crystal by nature. Germanium possess a positively charged nucleus of+32 while th silicon atoms nucleus possesses positive change of + 14. The total positive charge of the nucleus is equalized by the total effective negative charge of the electrons, this result in an atom having a positive or negative effective charge but neutral. ...

The electrons traveling within their respective orbits possesses energy since they are a definite mass in motion, The energy level is detected by electron's momentum and its physical proximity to the nucleus. The conductivities of these materials is of greater importance have because the more likely the chances of outermost (valence) electrons breaking away for conduction, Conductivity can be increased by either heating the crystal or by adding other types of materials (impurities) to the crystal when it. is formed, The impurities may be donors such as arsenic which dona s extra free electron to the crystal, since arsenic atom contains five electrons in its valence band, or acceptors such as aluminum which' accepts" electrons from th crystal to produce free holes since each aluminum atom cont(lins only three electrons in its valence band.

A semiconductor which contains donor atoms is called an n-type semiconductor since conduction is by virtue of free electrons (negative charge) that which contains acceptor atoms is called a p-type semiconductor and the conduction here is by virture of holes in the crystal (positive charger). Diodes If a p-type region and an n-type region are formed in the same crystal structure, we have a device known as a diode. The boundaries between the two regions is called a junction, the terminal connected to the p region is called the anode and that connected to the n region is called the cathode. A diode is shown in figure 2.1. for two condition of applied voltage. In figure 2.1 a the anode is at a negative voltage with respect to the cathode and the diode is said to be reverse based.

The holes in p-region are attracted towards to anode terminal and electron in the n-region are attracted towards the cathode terminal congruently two charges flow across the junction and no current will flow through the diode. In figure 2-1 (b) the anode of the diode is at a positive voltage with respect to the cathode and the diode is said to be forward biased. In this case, the holes in the p region will flow across the junction and recombine with electrons in the n


region, similarly, the electrons in the n-region will flow across the junction and recombine with the holes in the p- region. The net result will be a large current through the diode for only a small applied voltage.

Figure :2.l: 'Conduction in a PN junction-diode Transistors A transistor is formed by a thin p-region or n-region between two n regions and two p - regions respectively. The former is called an N PN transistor while the later is called a P NP transistor It has three region and two junctions, the three region are called emitter. collector and base while the junctions are emitter junction and the collector junction. Figure 2.2 shows an N PN transistor.

Figure 2.2 NPN transistor common emitter Configuration In most applications the transistor is. ,used in common emitter configuration; as shown in figure.' 2.2 when the current through the output

Anode

P-region

Junction

N-refion

Cathode

Base

Collector

Vcc

EmitterVcc

R

E

L

B

N type collector region

P type Base region

Collector junction

N type Emitter region

Emitter junction


moderate input impedance (13k) moderate output impedance (50k) high current gain (35) High voltage gain (-270) highest power gain (40db)

lowest input impedance 35 highest output impedance (1M) low current gain (-0.98) high voltage gain (380) moderate power gain (26db)

highest input impedance (350kW) lowest output impedance (500kW) high current gain (-36) unity voltage gain (1.00)lowest power gain (15db )

Common Emitter (CE)

Common Base (CB)

Common Collector (CC) Emitter Follower

33

BE


2.2 Diode Logic Logic gates are used to obtain output signals that are usually pulses when certain combination of input signals occur. Two distinct voltage levels are provided and represent the binary number I and 0 corresponding to the true and False logic. The diode can be used to realize the above function. Suppose there are two inputs, A and B then the output is given by a signal A or B or both. There are four possible combination of input A and B. and the output is related to them and indicated in a table called the truth table.

(a) Diode Logic circuit

(b) Response with time

Figure 2.4 Diode Logic OR gate representation.

For no input (zero voltage) in fig 2 .4(a), no current flows. and the output is zero (0). An input of +5v (1) at either terminal in A or B or both forward biases the

5C0

5A0

5B0

5v

A

BA + B

34

I

I

R


voltage rises to nearly 5v (1). For two input that varies with time, the response is show in 2.4(b). The resistor R must be large compared with the resistance of a forward biased diode and small compared with that of the reverse biased diode, The truth table for the OR gate just described is show in table 2.1 below;

Table 2.1: Truth Table for diode logic or gate

A B C

Positive Positive Positive

Positive No signal Positive

No signal Positive Positive

No signal No signal No signal

If the diodes in figure 2.4a are reversed, they conduct negative pulse inputs. If the diode are reverse biased the output appears only when there are inputs at A and B. Though there may be several input terminals, if anyone of the input is zero (0) current flows through the reverse biased diode and the output is nearly zero. The circuit diagram and pulse train is shown below.

(a) (b)

Figure 2.5 Diode AND gate. (a) logic circuit (b) Typical response.

5v

5v

A.B

RL

R5A0

5B0

5A+B 0

t

v


Table 2.2. Truth table for diode AND gate

A B C

Negative Negative Negative

Negative No signal No signal

No signal Negative No signal

No signal No signal No signal

A transistor can be used to restore the levels of the signal in the OR gate since the output is always less than the input. The result here is a NOT OR or NOR operation as shown in figure 2.6 below;

(a) Circuit diagram

(b) Response

Figure 2.6 Diode transistor NOR gate.

A

B

C RK

Rc (RL)

Q1

-VB

A+B

+5v

t

v

5C= A+B 0

5 B 0

5 A 0


In this circuit with no inputs, the transistor switch is held off by negative base voltage and the output is +5V( 1 ). A positive voltage terminal A or B raises the base potential, forward biases the emitter junction, turns the transistor ON, and drops the output close to zero(0). The transistor provides how output resistance making this NOR element to be a supplier of inputs to many other gates. It has a universal function of achieving all other basic logic operation with its use alone. The diode transistor combination can be used to perform an inverted AND function. See diagram in figure 2. 7

(a) Circuit diagram

(b) Response

Figure2.7 Diode transistor NAND gate

A

B

RB RcA . B

+5v

5A0

5A0

5A.B 0

t

v


With positive inputs at A and B i.e. (1 AND1), the diodes are reversed biased, and no current flows. The positive base current causes heavy collector current and the output is nearly zero (0), if either of the inputs has a zero as their input value, at least one diode conducts to ground, the emitter junction drops below the critical value, no base current and hence no collector current flows, and the output is +5v (1).

2.3 Transistor Logic Gates Transistor transistor logic (TTL) is a very prominent logic family that uses a bipolar junction transistor throughout for a gate.

Figure 2.8 TTL gate with resistor pull- up

The circuit in figure 2.8 is broken down to three parts, the combiner, the restore and the buffer; The combiner consists of a multiple emitter transistor T1 (this number can be increased). The input signals to the gate are connected to a separate emitter which forms its junction with the base. If any base-emitter junction is sufficiently forward biased the transistor will be in the conductive state (i.e.. current will tend to flow in voltage supply particular base-emitter junction will be forward biased whenever the emitter is close to ground) . Thus, the transistor will be in the conductive state whenever any emitter has a voltage that is low (0). In this case, a significant amount of current flows out of the emitters that have a low voltage, which is primarily due to the base current. When all emitters are high (1), the transistor will be cut off, which imply little current flow in any emitter. The Restorer consists of the transistor T2 and two resistors. The base of T2 is connected to the collector of T so that the current in both leads is the same.1

B

A

RR R

T1T2

T3

Combiner Restorer Buffer

+5v

output


39

9


BA

RR R

T1T2

Combiner Restorer Buffer

+5v

TL

THR

40 H


Figure 2.10 Basic RTL NOR gate.

RTL NOT Gate The NOT element is an inverter', the output is the complement of a single input. With no input (0) the transistor in figure 2.10 switch is held open by a negative base voltage and the output is +5v (1). A positive input voltage (1) forward biases the emitter junction collector current flows. and the output voltage drops to few tenths of a volt (0).For a changing input the output response is shown in figure 411.b.

(a) Transistor Circuit

A

B

C

R1

R2

R3

RE

Vcc

Output

- VBE

RA

Rc

outputA

41

y = A.B.C


(b) Response

Figure 2.11 The transistor NOT gate.

2.5 Common Logic Systems In this section we will attempt to describe briefly different logic systems giving their diagrams, simple description, features and also giving suitable transistor and diodes: RTL:

Resistor Transistor Logic (NOR)

Figure 2.12 Circuit Diagram for RTL

5A0

5A0

v

t

y = A+B+Coutput

Vcc

RB

A

B

C

R1

R2

R3


Description: Logic is performed by resistors Any positive input produces an inverted output irrespective of the other inputs. Resistors R gives temperature stability. nFeatures: The circuit design is straight forward, All logical operations can be performed with only this circuit. Many transistors readily meet the steady state requirements.

Germanium Silicon

High Speed Low Speed High speed Low speed

2N78 2N526 2N705 2N335

2N167 2N526A 2N711 2N656A

2N169A 2N1304 2N828

2N396A 2N1305 2N964

2N525 2N1924 2N994

Table 2.4 Suitable Transistors

RTCL: Resistor Capacitor Transistor Logic.

Description: Same as RTL except that capacitors are used to enhance switching speed. The capacitors increase the base current for fast collector current turn on and minimize storage time by supplying a charge equal to the stored base charge. Features: Faster than RTL at the expense of additional components and stringent stored charge requirements.


Figure 2.13. Circuit Diagram

Table 2.5 Suitable Transistors.

Germanium Silicon

Low speed High speed Low speed High speed

2N396A 2N705 2N1613

2N404 2N711 2N2193

2N634

DL: Diode Logic.Description:Logic in performed by diodes. The output is not. inverted, arnplifiers are required to maintain the correct logic levels through several gates in series.Features: Several gates may be used between amplifiers. High speeds can be attained. Non-inversion amplifiers circuit design problems. Relatively inexpensive components are used.

y = A + B

RBR

A


(a)

(b)

Figure 2.14. Diode Logic Circuit Diagram.

A

B

C

A+B+C

A

B

C

A+B+C

+Vcc


Table 2.6. Suitable Transistors and Diodes.

Germanium Silicon Diode (silicon)

Low speed High speed Low speed High speed High speed

2N78 2N705 2N333 2N706 IN3604

2N167 2N711 2N337 2N708 IN3605

2N396A 2N964 2N656A 2N1613 IN1613

2N526 2N994 - 2N2193 -

2N635A

DCTL: Direct Coupled Transistor Logic.Description:Logic performed by transistors. V and V , measured with the transistor in CE nlsaturation, define the two logic levels. VCI must be much less than V,\! to ensure stability and circuit flexibility Features: Very low supply voltages may be used to achieve high power efficiency and miniaturization Relatively fast switching.

(a) (b)

Figure 2.15. Circuit diagram for Direct Coupled Transistor Logic.

B

A

A.B

Vcc

BA

A+ B


DTL: Diode Transistor LogicDescription:Logic is performed by diodes. The output is inverted and the transistor acts as an amplifier. This is essentially an extension of the logic discussed above.Features:High speed can be attained. the impedance and voltage levels from stage to stage are well defined.

(a)

(b)

Figure 2.16. Circuit Diagrams for Diode Transistor Logic.

A.B.C

Vcc

A

B

C

A

B

C

A+B+C+Vcc


Table 2.7. Suitable Transistors and Diodes.

TDL: Tunnel Diode Logic.

Description: Logic is performed by tunnel diode switching from low to high voltage state. Whether circuit represents AND or OR gate depends on the bias current through the resistor R. Tunnel diode biased near peak current for OR gate and close to ground for AND.

Features: Current flowing through input resistors determines logic. Circuit is basically simple and very high speed is obtainable.

Suitable Transistors and Diodes: TD - lA, TD - 2A, TD - 3A, TD-31IB These are German i um Tunnel diodes.

48

Germanium Silicon Silicon diodes

Low speed High speed Low speed High speed High speed

2N78 2N705 2N333 1N3604 2N706

2N167 2N711 2N337 1N3605 2N708

2N396A 2N964 1N3606 2N914

2N526 2N994 2N1613

2N635A

2N1304

2N1305


Figure 2.1 . 7 Circuit diagram of Tunnel Diode Logic.

A

B

C

+Vcc

A+B+C orA.B.C


I. Explain the following briefly (i) P-type material and n-type semiconductor materials (ii) Majority and minority carriers (iii) Impurity conduction.

2.(i) Explain with aid of a diagram conduction in a PN junction diode. (ii) What is a truth table? Explain the diode logic OR gate and give its truth table.

3. Explain with aid of a diagram the operation of an NPN transistor in common emitter configuration.


CHAPTER 3

COM BINATIONAL AND SEQUENTIAL LOGIC ELEMENTS

3.0 General Characteristics Consider a general model of a switching system shown in figure 3.0. We have n inputs or e~citation variables, X (t), k = 1,2, ------. n and p outputs, or response kvariables, z, (t),i = I, 2, ----- p, all assumed to function the time. If at any instance the present value of the inputs relay determines the output we describe this as a combinational system.

Figure 3.0 General Model

This system can be described by the equation of form Zi = fi (X1, X2. ----------, Xn) Here the value of variables will be those at some single time and their dependence on time need not be indicated. On the other hand if the present value of outputs is not solely input dependent but also on the past in story of the system, then we call this a sequential system. Digital computers are very important example of sequential system because there are many levels of sequential operation involving sequential use of subsystems that are themselves sequential. Example the addition of a number into the accumulator of a digital computer, here the resultant sum depends on both the number and on what has been put into the accumulator previously.

3.1 Basic Logic Gates The term "Logic" usually used to refer to a decision-making process. A logic gate, then is a circuit that can take a decision on whether to say yes or no at the output based on the inputs. A logic gate is a combinational logic which the output is controlled by the state of the input and if the inputs are changed a new output is obtained.

XR (t) Z (t)

XR

(t) Switching

System

Z (t)

XR

(t)

Zp (t)


L ic i cuit o nl combinational logic element ha e no memorl ment c n be nthe zed from the basic l i ates The

basic ran e of l i tes k w b th n m D. OR OT OR and D

The AND Logic Gate The peration of thi g can be best de crib u in imple

switching circuit The i nal camp will il uminate onl if and B re closed or we could sa the output F wil be logic 1 if input and input B r t logic 1 It is sometimes called the all or nothing gate The truth table shows the output tat r all po ible c mbinations of inputs Figure 3 Show The B i Ide

og c r s containing f o y v y, e e s a sy si og c g

g og c ga i no y e a es A N , NNAN

o s ate s ed by s g a ss g y a

y A a e a . " "

s e fo ss o s as c a

though memory .s ,

A

. . .1

N.

.

. ll

Figure 3.1 The AND Logic Gate

(b) Logic symbol Y = A.B(a) Circuit using switch

Inputs Outputs B A Y

Switch Voltage

Binary Switch

Voltage Binary

Light Binary

LOW

0

LOW

0

NO

0

LOW

0

HIGH

1

NO

0

HIGH

1

LOW

0

NO

0

HIGH

1

HIGH

1

YES

1

( c) Truth Table

A

B Y

A

BY


A short method used to represent the AND operation is called Boolean expression (from Boolean or Logic algebra) The Boolean exprcssion is a universal language used in digital electronics. In this expression the AND operation is represented by a dot this means that the operation above has a Boolean expression A . B = Y in Boolean form.

The OR Gate This is sometime called the "any or all gate can be represented by parallel connected switches as shown in figure 3.2 which also shows the logic symbol. The signal lamp will only illuminate if switch A or switch B or both are closed. Y will be logic 1 if input A or B or both inputs are at logic 1. The truth table lists the switch and light conditions for the OR gate circuit in Fig 3. 2. The Boolean expression t"l"lr the OR function has a plus sign as the symbol for OR.

( b) Logic Symbol and Boolean Expression

(a) Circuit Using Switches

Figure 3.2 The OR Gate Logic.

A

B

F Y = A + B

Inputs Outputs B A Y

Switch Binary Switch Binary Light Binary Open 0 Open 0 NO 0 Open 0 Closed 1 YES 1

Closed 1 Open 0 YES 1 Closed 1 Closed 1 YES 1

( c) Truth Table

A

B


The NOT Gate or Inverter The NOT gate is a single input gate which gives an output that is the opposite of the input It is often called an inverter or negator since it gives an outp hat is not the same as the input If the input is A the output is NO which is written as A (bar A) the mall c rcle on the output of t gate always indicate a change of sign The truth table shows the possible state for all possible inputs in figure 3.3.

(a) Logic symbol and Boolean expression.

(b) Truth Table for the inverter.

Figure 3.3 The NOT Gate.

-

.

. .

.

.

.

ut t, T A

. s i he

The Buffer This is a device that has only one input and one output and has same logic input and output It has no effect upon the logic le els of the circuit i e the input and output logic levels are identical It is used to interface logic circuits which demand more current than could be suppl ed by an un buffered logic circuitSince he output current can be much greate they exhibit current gain the

mb l and the truth table of the buffer is shown in figure 3.4.

v .

it r,

sy o

.

Input Output Voltage Binary Voltage Binary

Low 0 High 1 High 1 Low 0

Input Output 0 0 1 1

(a) Logic Symbol (b) Truth TableFigure 3.4 The Buffer

InputA Y

Y = YInputA


The NAND Gate The NAND gateis a NOT AND, or an inverted AND Function The standard

logic symbol for the NAND gate is shown in figure 3.5 (a) the little invert bubble (small circle) on the right means to In ert the AND The Boolean expression for the NAND is the invert for the AND as shown in the logic diagram This gate is a universal gate because it can be wired to create any other gate

.

v.

" "

.

.

(a) Logic Symbol and Boolean Expression

(b) Truth Table for AND and NAND Gate

Figure 3.5 The NAND Gate.

The truth table shows that the NAND gate is developed by inverting the AND outputs. NAND gate are usually applied in industrial practice and used extensively in digital equipments. The NAND can be combined to form other logic gates, hence the name the universal logic element. The reader should attempt to realize the other gates using the NAND gate.

The NOR Gate This is a NOT OR gate with an output of an OR gate inverted to form a NOR gate. The logic symbol and the Boolean expression for the OR function (A + B) is shown, the Boolean expression for the final NOR function is A + B.

A

By = A . B

Input Output B A AND NAND 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0


(a) Logic Symbol and Boolean Expression.

(b) Truth Table for OR and NOR Gates.

Figure 3.6 The NOR gate.

The Exclusive OR (XOR) Gate. This refers to "any but not all gate" the term exclusive is shortened using X hence we have X OR gate. The symbol (+) means the terms are X ORed together. The logic symbol, Boolean expression and truth table for the XOR is shown in figure 3. 6. It produces a HIGH output only when an odd number of HIGH inputs are present. The exclusive OR gates are used in variety of arithmetic circuits.


(b) Truth Table for OR and NOR gates.

Figure 3.7 The Exclusive OR Gate.

The Exclusive NOR Gate Th is short n d X OR te It has an added n t u ble on th utput ide Th Bo lean e press on for th X OR g te h s bar o er th A B

e pression telling us about the n ert d output Thi te is ummarized in fig3

is e e N ga i ver ed b b e os e o x i e N a a a v e

x i v e s ga s

. .

. . .

Input Output B A OR NOR 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0

A

B

F = A + B

A F = A + BInput Output

B A OR XOR 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0

+

B



( c) Truth Table for XOR and XNOR gates.

Figure 3.8 The Exclusive NOR gate.

Gates with more than Two Inputs. Th t o input gates has four possible states or options hen considerin the t uth table The Boolean expression for a two input ND ate for in tance is Y = A B and for a three input we should h e B C Y with th s expression e should expect an increment in th op ons of the truth table inputs If we apply the expression 2 where n represents the number of inputs e would have it that for a t o nput we ill ha e 2 4 and for three inp we will have 2 8 and four input we ill ha e 2 16 inputs etc respectively Consider an A D ate with three inputs in figure 3 9 for further expl nation The re der can de elop the truth bl for a four input OR gat

e w w g r A g s

av A . = i we ti

n , w2 3w i w v ut

4w v = N ga a v

ta e e.

(a) Logic Symbol and Boolean Expression for a three input OR gate.

. ..

= =

. . .

+F = A BA

B

Input Output B A XOR XNOR 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1

ABC

F = A . B . C


(b) Truth Table for three input AND Gate.

Figure 3.9 The Three Input AND Gate.

Since we frequently run into gates that ha e fr m t o to as much as eight or more inputs the basics co ered her i h nd reference we need to expend the number of inputs to a t

3.2 LOGIC NETWORK AND TIMING DIAGRAMS

Logic Network.Individual ogic gates ma be connec ed to provide any desired output The result of the combination Can be found by working through each gate in the network in turn producing the truth table for the particular network Here are some examples; I. An AND and NOT gate are connected together, complete the truth table

for this logic networkIl A NAND gate has a NOT gate on each of its inputs Draw the circuit and

complete the truth tableIll A logic system has three inputs as shown in the figure below develop

the truth table for this arrangement

v o w, v e s a a y

ga e.

l y t

. ,

.

.

.

. .

'

.

. .

,

Inputs Outputs C B A Y 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1


Figure 3. 10. Logic network for example (iii)(iv) A logic System has three inputs as shown in the figure 3 11 Develop the truth table

. .

.

Figure 3.11 Logic Network For example (iv)

.

Solution: Work out progressively from left to right through the individual gates, recall that for any two input logic gates there are four possible combinations and for the

nthree input there are eight combinations from the expression 2 .

Figure 3.12 Logic Network(

A

B

CF

D

F

A

B

C

A

BC

F


The truth table for figure 3.12 is given below,

(ii)

Figure 3.13 Logic Network for Question (ii).

From the network shown in figure 3.13 the truth table is as follows:

(iii) All possible combination are shown in column A B C and there will be 2rows in the table The truth table is shown below:

, , .

, '

A B C F 0 0 0 1

0 1 0 1

1 0 0 1

1 1 1" 0

A

B

A

B

F

0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 0 0 1

60

A

B F

A

B


Truth Table.

(v)

Truth Table.

As we saw in example (iii) the truth table will have three inputs as shown below:

A B C D F

0 0 0 0 0

0 0 1 0 0 0 1 0 0 0 0

1

1

0

0

1

0

0

0

0

1

0

1

0

0

1

1

0

1

0

1

1

1

1

1

A B C D F

0 0 0 0 0

0 0 1 0 1

0 1 0 1 1

0 1 1 1 1

1 0 0 1 1

1 0 1 1 1

1 1 0 1 1

1 1 1 1 1


Timing DiagramsIn most applications, the inputs to a gate are not stationary levels but are voltage waveforms that change frequently between HIGH and LOW logic levels. A Timing Diagram can show graphically the transitions (Inputs [Events]) and states (Outputs) of the switching voltage waveforms.Examples of pulsed AND gate operation with a timing diagram showing input and output relationships below. For each of the diagram produce their truth table

A and B are both HIGH during these four time intervals. Therefore F is HIGH

A

B

X

1 0 1 1 0

1 1 1 0 0

1 0 1 0 0

t1 t2 t3 t4 t5

A B X

A B

A HIGH LOW

B HIGH LOW

X HIGH LOW

{ { { {

62

F

I


Figure 3.14 Boolean expressions for AND gates with two, three, and four inputs.

A HIGH LOW

B HIGH LOW

X HIGH LOW

Inputs

Output

A

B

C

X

A BC

A

B

63

F

F


Figure 3.15 Example of pulsed OR gate operation with a timing diagram showing input and output time relationships. For each of these diagram develop the truth table.

Figure 3.16 TIMING DIAGRAM (Pulsed Operation)

Figuren3.16. Timing Diagram.

t1 t2 t3 t4

A

B

X

A B

1 1 O O

1 1 O O

O 1 1 1

64

A

B

C

D

X

A B C D

F


3.3 Logic Symbols The logic symbols used so far in our discussion are the primitive ones that is recognized by all in the electronic industry. Manufactures data manuals include traditional logic symbols and recently the IEEE functional symbols are also include. Those symbols are in accordance with ANSI/EEE standard 91-1984 and IEC publication 617-12. They are commonly called "dependency notation". All the IEEE logic symbols are rectangular with an identification character inside the rectangle. Characters outside the rectangle are not part of the standard symbol as it may vary with manufactures. The comparison between IEEE logic gate and primitives logic gate symbol is shown in Figure 3.17.

LogicFunction

Primitivelogic symbol

IEEE LogicSymbol

Figure 3.17 Logic Gate Symbols

A B & F

A B >1 F

A F1

A B F

A B >1 F

A B =1 F

A B F = A.B

AND GATE

A B F = A+B

OR GATE

A F = A

NOT or INVERTER

A B F = A.B

NAND GATE

A B F = A+B

NOR GATE

A B F = A+B

EXCLUSIVE-OR GATE

Inputs A B

Output F

o oo 11 o1 1

ooo1

A B F o oo

o11

1 1

o111

oo

A F A = -

11

A B

A B

F o o

oo1 1 1

1

o1 1 1

F o o

oo1

1

1 1

1 ooo

F A Bo o oo

oo

1 1 1

1 1 1


1. (a) Draw the primitive logic symbols for the following;(I) Two input AND gate (ii) Two input XOR gate (iii) Two input NOR gate (iv) Four input NAND gate

(b) Write the Boolean expression for each gate and Draw the truth table for each gate in question.

Given 4 two input AND gate, draw how you will produce a five input AND gate

3. Draw the IEEE standard logic symbol for a three input XNOR gate

4. Draw the logic wiring of NAND gate to realize the seven basic primitive gate (AND OR NAND NOR, XOR and XNOR)

5. Develop the truth table for the logic Network shown below;

(I)

(ii)

2. .

.

.

, , , .

F

DAB

E

F

DAB

E


(iii)

6. State the advantages of edge triggering and differentiate between leading `and trailing edge triggered latches.

7. What type of logic circuit can perform basic addition and what limitation does it have.


CHAPTER BOOLEAN ALGEBRA AND DIGITAL LOGIC.

4.1. IntroductionBoolean algebra provides the foundation for both computer hardware and software. An understanding of this mathematical system can help you better appreciate the connection between software and hardware. Boolean algebra is a mathematical system with its own set of rules (postulates), theorems, and values. In many respects, boolean algebra is similar to the real-arithmetic alge-bra you studied. In most respects, however, boolean algebra is actually easier to learn than real arithmetic algebra. The features of any algebraic system including operators, closure, commutativity, associativity, distribution, identity, and inverse. Then it presents some important postulates and theorems from boolean algebra and discusses the principle of duality that lets you easily prove additional theorems in boolean algebra. The Truth Table is a convenient way to visually represent a boolean function or expression. Every boolean function (or expression) has a corresponding truth table that provides all possible results for any combination of input values. This chapter presents several different ways to construct boolean truth tables. Although there are an in?nite number of boolean functions you can create given n input values, it turns out that there are a finite number of unique functions

npossible for a given number of inputs. In particular, there are 2^2 unique boolean functions of n inputs. For example, there are 16 functions of two

2variables (2^2 = 16). Since there are so few boolean functions with only two inputs, it is easy to assign different names to each of these functions (e.g., AND, OR, NAND, etc.). For functions of three or more variables, the number of functions is too large to give each function its own name. Therefore, we'll assign a number to these functions based on the bits appearing in the function's truth table. Algebraic manipulation of boolean functions and expression allows us to prove new theorems in boolean algebra, simplify expressions, convert expressions to canonical form, or show that two expressions are equivalent. Since there are an in?nite variety of possible boolean functions, yet a ?nite number of unique boolean functions (for a ?xed number of inputs), clearly there are an in?nite number of different functions that compute the same results. To avoid confusion, logic designers usually specify a boolean function using a canonical form (the sum of minterms form and the product of maxterms form.). If two canonical equations are different, then they represent different boolean functions.


Although the canonical forms provide a unique representation for a given boolean function, expressions appearing in canonical form are rarely optimal. That is, canonical expressions often use more literals and operators than other, equivalent, expressions. When designing an electronic circuit or a section of software involving boolean expressions, most engineers prefer to use an optimized circuit or program since optimized versions are less expensive and, probably, faster. Therefore, knowing how to create an optimized form of a boolean expression is very important. The implementation of addition, decoders, memory, shift registers, and counters is achieved using the boolean functions.Key FeaturesThe key features of Boolean Algebra are, 1. Use Of Binary Data There are two conditions in Boolean Algebra: TRUE (or Present) and FALSE (or Absent). These two states are represented in base 2: 1 indicates presence and 0 indicates absence.2. Use Of Truth Table To Represent Data In order to use Boolean Algebra as a technique of qualitative comparison, it is necessary to construct a data matrix as a truth table.3. Boolean Addition (OR) In Boolean Algebra, if A + B = Z, and A = 1 and B = 1, then Z = 1. In other words 1 + 1 = 1. The basic idea in Boolean Addition is that if any of the additive terms is satisfied (Present), then the outcome is true (Occurs). Addition in Boolean Algebra is equivalent to the logical operator OR. Thus the statement A + B = Z becomes: If either A equals1 OR B equals 1, then Z equals 1. 4. Boolean Multiplication (AND) Boolean Multiplication differs substantially from normal multiplication. Boolean Multiplication is relevant because the typical social science application of Boolean Algebra concerns the process of simplifying expressions known as SUMS OF PRODUCTS. A product is a specific combination of causal conditions eg. F = Abc + aBc + abC + ABc + AbC + aBC + ABC 5. Combinatorial Logic The absence of a cause has the same logical status as the presence of a cause in Boolean Analysis. Boolean Multiplication indicates that presence and absence conditions are combined.


6. Boolean Minimization If two Boolean expressions differ in only one causal condition, yet produce the same outcome, then the causal condition that distinguishes the two expressions can be considered irrelevant and can be removed to create a simpler, combined expression. eg. If Abc = F and ABc = F Then this allows the replacement of these two terms with the single, simpler expression: Ac = F (ie. the value of B is irrelevant. Cause B may be either present or absent , F will still occur.) 7. Implication A Boolean Expression is said to imply another if the membership of the second term is a subset of the membership of the first.eg. A implies Abc because A embraces all the membe

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