Advances in Designing Clockless Digital Systems Advances in Designing Advances in Designing Clockless Clockless Digital Systems Digital Systems Prof. Steven M. Prof. Steven M. Nowick Nowick [email protected][email protected]Department of Computer Science Department of Computer Science Columbia University Columbia University New York, NY, USA New York, NY, USA
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Advances in Designing Clockless Digital Systems
Advances in Designing Advances in Designing ClocklessClockless Digital SystemsDigital Systems
Trends in Chip Design: Trends in Chip Design: next decadenext decade“Semiconductor Industry Association (SIA) Roadmap”“Semiconductor Industry Association (SIA) Roadmap” (97(97--8)8)
Unprecedented Challenges:Unprecedented Challenges:complexity and scale (= size of systems)complexity and scale (= size of systems)
Design becoming unmanageable using a centralized Design becoming unmanageable using a centralized single clock (synchronous) approach….single clock (synchronous) approach….
#5
Trends and Challenges (cont.)Trends and Challenges (cont.)
1. Clock Rate:1. Clock Rate:
1980: 1980: several several MegaHertzMegaHertz
2001: 2001: ~750 ~750 MegaHertzMegaHertz -- 1+ 1+ GigaHertzGigaHertz2005:2005: several several GigaHertzGigaHertz
Design Challenge:Design Challenge:
“clock skew”:“clock skew”: clock must be clock must be nearnear--simultaneoussimultaneous across across entire chipentire chip
#6
Trends and Challenges (cont.)Trends and Challenges (cont.)
2. Chip Size and Density:2. Chip Size and Density:
Total #Transistors per Chip: Total #Transistors per Chip: 6060--80% increase/year80% increase/year~1970: ~1970: 4 thousand4 thousand (Intel 4004 microprocessor)(Intel 4004 microprocessor)
today: today: 5050--200+ million200+ million
2006 and beyond:2006 and beyond: towards 1towards 1 billion+billion+
Design Challenges:Design Challenges:system complexity, design time, clock distributionsystem complexity, design time, clock distributionclock will require 10clock will require 10--20 cycles to reach across chip20 cycles to reach across chip
#7
Trends and Challenges (cont.)Trends and Challenges (cont.)
Chips themselves becoming Chips themselves becoming distributed systems….distributed systems….contain many subcontain many sub--regions, regions, operating at different speeds:operating at different speeds:
Design Challenge:Design Challenge: breakdown of single centralizedbreakdown of single centralizedclock controlclock control
systems not limited to “worstsystems not limited to “worst--case” clock ratecase” clock rate
#11
Asynchronous Design: Some Recent DevelopmentsAsynchronous Design: Some Recent Developments
1. Philips Semiconductors:1. Philips Semiconductors:commercial use: 100 million commercial use: 100 million asyncasync chips for consumer electronics:chips for consumer electronics:
pagers, cell phones, smart cards, digital passports, automotive pagers, cell phones, smart cards, digital passports, automotive 33--4x lower power4x lower power,, less electromagnetic interference (“EMI”)less electromagnetic interference (“EMI”)
3. Sun Labs:3. Sun Labs:commercial use: highcommercial use: high--speed speed FIFO’sFIFO’s in recent “Ultra’s” (memory access)in recent “Ultra’s” (memory access)
4. IBM Research:4. IBM Research:experimental: highexperimental: high--speed pipelines, filters, mixedspeed pipelines, filters, mixed--timing systemstiming systems
Lack of Existing Asynchronous Design Tools:Lack of Existing Asynchronous Design Tools:
Most commercial “CAD” tools targeted to synchronousMost commercial “CAD” tools targeted to synchronous
Synchronous CAD tools: Synchronous CAD tools: major drivers of growth in microelectronics industry major drivers of growth in microelectronics industry
CAD Tools for CAD Tools for AsyncAsync ControllersControllers
MINIMALIST:MINIMALIST: developed at Columbia University [1994developed at Columbia University [1994--] ] extensible CAD package for synthesis of extensible CAD package for synthesis of asynchronous controllersasynchronous controllersintegrates synthesis, optimization and verification toolsintegrates synthesis, optimization and verification toolsused in 80+ sites/17+ countries (being taught in IIT Bombay)used in 80+ sites/17+ countries (being taught in IIT Bombay)URL:URL: httphttp://://www.cs.columbia.edu/asyncwww.cs.columbia.edu/async
Includes several optimization tools: Includes several optimization tools: State MinimizationState MinimizationCHASM: CHASM: optimal state encodingoptimal state encoding22--Level HazardLevel Hazard--Free Logic MinimizationFree Logic MinimizationVerilogVerilog backback--endend
Obtain multiObtain multi--GigaHertzGigaHertz speedsspeedsUsed by IBM, currently incorporated into Philips tool flowUsed by IBM, currently incorporated into Philips tool flow
#26
MOUSETRAP: A Basic FIFO (no computation)MOUSETRAP: A Basic FIFO (no computation)
Stages communicate using Stages communicate using transitiontransition--signaling:signaling:
reqN
ackN-1
reqN+1
ackN
Data Latch
Latch Controller
doneN
Data in Data out
En
Stage NStage N-1 Stage N+1
[Singh/Nowick, IEEE Int. Conf. on Computer Design (2001)]