Advanced VHDL for Design A 3 day course introducing VHDL language features which are not commonly known or used. The 3-day Advanced VHDL for Design class is aimed at experienced VHDL users who wish to take advantage of the lesser known aspects of the VHDL language to create reliable, re-usable design units in a standardised manner. A pre-requisite for this course is the Introducon to VHDL course or equivalent experience. Topics Covered • Introducon • Recap of design units • Latest VHDL Standards • The RTL Synthesis Subset • Books and Other Resources • The ASIC Design Flow • VHDL in the Design Flow • Effects of Coding on Synthesis Results • Coding Styles and Synthesis Runme • Type Guidelines • Types and Subtypes • Recommended Types for Synthesis • Preparing for Reuse • Advantages of Reuse • Designing Reusable IP • Managing VHDL Libraries • Limitaons of Standard Approaches • Recommended Library Structure • Exploing Enes and Architectures • Types of Design Unit • Advantages of Mulple Architectures • Synthesis Consideraons • Using Sub-programs Efficiently • Sub-program recap • Reasons for Using Sub-programs • Synthesis Limitaons • VHDL Configuraons • The Power of Configuraons • What Works With Synthesis • Opmising for Power • Power Reducon Techniques • RTL Tips to Reduce Power