Ads 1271

SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007

FEATURES 105kSPS Data Rate

AC Performance:51kHz Bandwidth109dB SNR (High-Resolution Mode)−108dB THD

DC Accuracy:1.8µV/°C Offset Drift2ppm/ °C Gain Drift

Selectable Operating Modes:High-Speed: 105kSPS Data RateHigh-Resolution: 109dB SNRLow-Power: 35mW Dissipation

Power-Down Control

Digital Filter:Linear Phase ResponsePassband Ripple: ±0.005dBStop Band Attenuation: 100dB

Internal Offset Calibration On Command

Selectable SPI or Frame Sync Serial Interface

Designed for Multichannel Systems:Daisy-Chainable Serial InterfaceEasy Synchronization

Simple Pin-Driven Control

Modulator Output Option

Specified from −40 °C to +105°C Analog Supply: 5V

Digital Supply: 1.8V to 3.3V

APPLICATIONS Vibration/Modal Analysis

Acoustics

Dynamic Strain Gauges

Pressure Sensors

Test and Measurement

DESCRIPTIONThe ADS1271 is a 24-bit, delta-sigma analog-to-digitalconverter (ADC) with a data rate up to 105kSPS. It offersa unique combination of excellent DC accuracy andoutstanding AC performance. The high-order,chopper-stabilized modulator achieves very low drift withlow in-band noise. The onboard decimation filtersuppresses modulator and signal out-of-band noise. TheADS1271 provides a usable signal bandwidth up to 90%of the Nyquist rate with less than 0.005dB of ripple.

Traditionally, industrial delta-sigma ADCs offering gooddrift performance use digital filters with large passbanddroop. As a result, they have limited signal bandwidth andare mostly suited for DC measurements. High-resolutionADCs in audio applications offer larger usable bandwidths,but the offset and drift specification are significantlyweaker than their industrial counterparts. The ADS1271combines these converters, allowing high-precisionindustrial measurement with excellent DC and ACspecifications ensured over an extended industrialtemperature range.

Three operating modes allow for optimization of speed,resolution, and power. A selectable SPI or a frame-syncserial interface provides for convenient interfacing tomicrocontrollers or DSPs. The output from the modulatoris accessible for external digital filter applications. Alloperations, including internal offset calibration, arecontrolled directly by pins; there are no registers toprogram.

∆ΣModulator

DigitalFilter

VREFP VREFN AVDD DVDD

DRDY/FSYNCSCLKDOUTDINFORMAT

AINP

AINN

SerialInterface

ControlLogic

DGNDAGND

SYNC/PDWNMODE

CLK

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Copyright 2004−2007, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.

! "# $ %& $ " '&(% ) &%$%"# $'%"%$ ' #$ " *$ $&#$ $ +)&% '%$$ $ %$$+ %& $ " '#$)

SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners.


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2

ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range unless otherwise noted(1)

ADS1271 UNIT

AVDD to AGND −0.3 to +6.0 V

DVDD to DGND −0.3 to +3.6 V

AGND to DGND −0.3 to +0.3 V

Input Current100, Momentary mA

Input Current10, Continuous mA

Analog Input to AGND −0.3 to AVDD + 0.3 V

Digital Input or Output to DGND −0.3 to DVDD + 0.3 V

Maximum Junction Temperature +150 °COperating Temperature Range −40 to +105 °CStorage Temperature Range −60 to +150 °C

(1) Stresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periodsmay degrade device reliability. These are stress ratings only, andfunctional operation of the device at these or any other conditionsbeyond those specified is not implied.

This integrated circuit can be damaged by ESD. TexasInstruments recommends that all integrated circuits behandled with appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation tocomplete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.

ORDERING INFORMATIONFor the most current package and ordering information,see the Package Option Addendum located at the end ofthis data sheet, or refer to our web site at www.ti.com.


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3

ELECTRICAL CHARACTERISTICS All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted.

Specified values for ADS1271 and ADS1271B (high-grade version) are the same, except where shown in BOLDFACE type.

ADS1271 ADS1271B

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Analog Inputs

Full-scale input voltage (FSR(1)) VIN = (AINP – AINN) ±VREF ±VREF V

Absolute input voltage AINP or AINN to AGND AGND – 0.1 AVDD + 0.1 AGND – 0.1 AVDD + 0.1 V

Common-mode input voltage VCM = (AINP + AINN)/2 2.5 2.5 V

Differential High-Speed mode 16.4 16.4 kΩDifferentialinputimpedance

High-Resolution mode 16.4 16.4 kΩinputimpedance Low-Power mode 32.8 32.8 kΩ

DC Performance

Resolution No missing codes 24 24 Bits

Data rateHigh-Speed mode 105,469 105,469 SPS

Data rate(fDATA)

High-Resolution mode 52,734 52,734 SPS(fDATA)

Low-Power mode 52,734 52,734 SPS

Integral nonlinearity (INL)Differential input,VCM = 2.5V

± 0.0006 ± 0.0015 ± 0.0006 ± 0.0015 %FSR(1)

Offset errorHigh-Speed mode Without calibration 0.150 1 0.150 1 mV

Offset errorWith calibration On the level of the noise

Offset drift 1.8 1.8 µV/C

Gain error 0.1 0.5 0.1 0.5 %FSR(1)

Gain error drift 2 2 ppm/°C

High-Speed mode Shorted input 9.0 20 9.0 16 µV, rms

Noise High-Resolution mode 6.5 6.5 12 µV, rmsNoise

Low-Power mode 9.0 9.0 16 µV, rms

Common-mode rejection fCM = 60Hz 90 100 95 110 dB

Power-supply AVDDf = 60Hz

80 80 dBPower-supplyrejection DVDD

f = 60Hz80 80 dB

AC Performance

Signal-to-noise(2)

High-Speed mode 99 106 101 106 dBSignal-to-noiseratio (SNR) (2)

(unweighted)High-Resolution mode 109 103 109 dBratio (SNR)

(unweighted) Low-Power mode 106 101 106 dB

Total harmonic distortion (THD)(3) VIN = 1kHz, −0.5dBFS −105 −95 −108 −100 dB

Spurious-free dynamic range −108 −109 dB

Passband ripple ±0.005 ±0.005 dB

Passband 0.453 fDATA 0.453 fDATA Hz

−3dB Bandwidth 0.49 fDATA 0.49 fDATA Hz

Stop band attenuation 100 100 dB

High-Speed mode 0.547 fDATA 63.453 fDATA 0.547 fDATA 63.453 fDATA Hz

Stop band High-Resolution mode 0.547 fDATA 127.453 fDATA 0.547 fDATA 127.453 fDATA HzStop band

Low-Power mode 0.547 fDATA 63.453 fDATA 0.547 fDATA 63.453 fDATA Hz

Group delay

High-Speed andLow-Power modes

38/fDATA 38/fDATA sGroup delay

High-Resolution mode 39/fDATA 39/fDATA s

Settling time(latency)

High-Speed andLow-Power modes

Complete settling 76/fDATA 76/fDATA s

(latency)High-Resolution mode Complete settling 78/fDATA 78/fDATA s

(1) FSR = full-scale range = 2VREF.(2) Minimum SNR is ensured by the limit of the DC noise specification.(3) THD includes the first nine harmonics of the input signal.(4) MODE and FORMAT pins excluded.(5) See the text for more details on SCLK.


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ELECTRICAL CHARACTERISTICS (continued)All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted.

Specified values for ADS1271 and ADS1271B (high-grade version) are the same, except where shown in BOLDFACE type.

ADS1271BADS1271

PARAMETER UNITSMAXTYPMINMAXTYPMINTEST CONDITIONS

Voltage Reference Inputs

Reference input voltage (VREF) VREF = VREFP – VREFN 2.0 2.5 2.65 0.5 2.5 2.65 V

Negative reference input (VREFN) AGND − 0.1 VREFP − 2.0 AGND − 0.1 VREFP − 0.5 V

Positive reference input (VREFP) VREFN + 2.0 AVDD − 0.5 VREFN + 0.5 AVDD + 0.1 V

Reference High-Speed mode 4.2 4.2 kΩReferenceInputimpedance

High-Resolution mode 4.2 4.2 kΩInputimpedance Low-Power mode 8.4 8.4 kΩ

Digital Input/Output

VIH 0.7 DVDD DVDD 0.7 DVDD DVDD V

VIL DGND 0.3 DVDD DGND 0.3 DVDD V

VOH IOH = 5mA 0.8 DVDD DVDD 0.8 DVDD DVDD V

VOL IOL = 5mA DGND 0.2 DVDD DGND 0.2 DVDD V

Input leakage(4) 0 < VIN DIGITAL < DVDD ±10 ±10 µA

Master clock rate (fCLK) 0.1 27 0.1 27 MHz

SPI format 24 fDATA fCLK 24 fDATA fCLK MHz

Serial clockrate (f )(5)

High-Speed mode 64 fDATA 64 fDATA 64 fDATA 64 fDATA MHzSerial clockrate (fSCLK)(5)

Frame-Sync format High-Resolution mode 128 fDATA 128 fDATA 128 fDATA 128 fDATA MHzSCLK Frame-Sync format

Low-Power mode 64 fDATA 64 fDATA 64 fDATA 64 fDATA MHz

Power Supply

AVDD 4.75 5 5.25 4.75 5 5.25 V

DVDD 1.65 3.6 1.65 3.6 V

High-Speed mode 17 25 17 25 mA

High-Resolution mode 17 25 17 25 mA

AVDD current Low-Power mode 6.3 9.5 6.3 9.5 mAAVDD current

Power-Down modeT > 85°C 1 70 1 70 µA

Power-Down modeT ≤ 85°C 1 10 1 10 µA

High-Speed mode 3.5 6 3.5 6 mA

High-Resolution mode 2.5 5 2.5 5 mA

DVDD current Low-Power mode 1.8 3.5 1.8 3.5 mADVDD current

Power-Down modeT > 85°C, DVDD = 3.3V 1 70 1 70 µA

Power-Down modeT ≤ 85°C, DVDD = 3.3V 1 20 1 20 µA

PowerHigh-Speed mode 92 136 92 136 mW

Powerdissipation

High-Resolution mode 90 134 90 134 mWdissipation

Low-Power mode 35 54 35 54 mW

Temperature Range

Specified −40 +105 −40 +105 C

Operating −40 +105 −40 +105 C

Storage −60 +150 −60 +150 C

(1) FSR = full-scale range = 2VREF.(2) Minimum SNR is ensured by the limit of the DC noise specification.(3) THD includes the first nine harmonics of the input signal.(4) MODE and FORMAT pins excluded.(5) See the text for more details on SCLK.


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PIN ASSIGNMENTS

PW PACKAGETSSOP-16

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VREFP

VREFN

DGND

DVDD

CLK

SCLK

DRDY/FSYNC

DOUT

AINP

AINN

AGND

AVDD

MODE

FORMAT

SYNC/PDWN

DIN

ADS1271

Terminal Functions

PIN

NAME NO. FUNCTION DESCRIPTION

AINP 1 Analog Input Positive analog input

AINN 2 Analog Input Negative analog input

AGND 3 Analog Input Analog ground

AVDD 4 Analog Input Analog supply

MODE 5 Digital Input MODE = 0: High-Speed modeMODE 5 Digital InputMODE = float: High-Resolution modeMODE = 1: Low-Power mode

FORMAT 6 Digital Input FORMAT = 0: SPIFORMAT 6 Digital InputFORMAT = float: Modulator output (ADS1271B only)FORMAT = 1: Frame-Sync

SYNC/PDWN 7 Digital Input Synchronize/Power-down input, active low

DIN 8 Digital Input Data input for daisy-chain operation

DOUT 9 Digital Output ADC data output, modulator output (modulator mode)

DRDY/FSYNC 10 DigitalInput/Output

If FORMAT = 0 (SPI), then pin 10 = DRDY outputIf FORMAT = 1 (Frame-Sync), then pin 10 = FSYNC input

SCLK 11 Digital Input Serial clock for ADC data retrieval, modulator clock output (modulator mode)

CLK 12 Digital Input Master clock

DVDD 13 Digital Input Digital supply

DGND 14 Digital Input Digital ground

VREFN 15 Analog Input Negative reference input

VREFP 16 Analog Input Positive reference input


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TIMING CHARACTERISTICS: SPI FORMAT

CLK

tCPW

tCLK

tCPW

tSD tS

tDIST

tDOHD

tSPW

Bit 23 (MSB) Bit 22 Bit 21

tSPW tDOPD

tCD

tDS

tDDO

tDIHD

• • •

tCONV

DRDY

SCLK

DOUT

DIN

TIMING REQUIREMENTS: SPI FORMAT For TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.

SYMBOL PARAMETER MIN TYP MAX UNIT

tCLK CLK period (1/fCLK) 37 10,000 ns

tCPW CLK positive or negative pulse width 15 ns

High-Speed mode 256 CLK periods

tCONV Conversion period (1/fDATA) High-Resolution mode 512 CLK periodstCONV Conversion period (1/fDATA)

Low-Power mode 512 CLK periods

tCD(1) Falling edge of CLK to falling edge of DRDY 8 ns

tDS(1) Falling edge of DRDY to rising edge of first SCLK to retrieve data 5 ns

tDDO(1) Valid DOUT to falling edge of DRDY 0 ns

tSD(1) Falling edge of SCLK to rising edge of DRDY 8 ns

tS(2) SCLK period tCLK ns

tSPW SCLK positive or negative pulse width 12 ns

tDOHD(1)(3) SCLK falling edge to old DOUT invalid (hold time) 5 ns

tDOPD(1) SCLK falling edge to new DOUT valid (propagation delay) 12 ns

tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns

tDIHD(3) Old DIN valid to falling edge of SCLK (hold time) 6 ns

(1) Load on DRDY and DOUT = 20pF.(2) For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc.(3) tDOHD (DOUT hold time) and tDIHD (DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient

temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.


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TIMING CHARACTERISTICS: FRAME-SYNC FORMAT

SCLK

FSYNC

DOUT

DIN

tDOHD

tFPW

tS tSFtSPW

tSPW

tFRAME

tFPW

tFS

tDIHD

tDDO

tDIST

Bit 23 (MSB) Bit 22 Bit 21

tDOPD

CLK

tCPW

tCPWtCF

tCLK

TIMING REQUIREMENTS: FRAME-SYNC FORMAT for TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.

SYMBOL PARAMETER MIN TYP MAX UNIT

tCLK CLK period (1/fCLK) 37 10,000 ns

tCPW CLK positive or negative pulse width 15 ns

tCF Falling edge of CLK to falling edge of SCLK −0.35 tCLK 0.35 tCLK ns

High-Speed mode 256 CLK periods

tFRAME Frame period (1/fDATA) High-Resolution mode 256 or 512(1) CLK periodstFRAME Frame period (1/fDATA)

Low-Power mode 256 or 512(1) CLK periods

tFPW FSYNC positive or negative pulse width 1 SCLK periods

tFS Rising edge of FSYNC to rising edge of SCLK 5 ns

tSF Rising edge of SCLK to rising edge of FSYNC 5 ns

SCLK period (SCLK mustHigh-Speed mode τFRAME/64 τFRAME periods

tSSCLK period (SCLK mustbe continuously running)

High-Resolution mode τFRAME/128 τFRAME periodstS be continuously running)Low-Power mode τFRAME/64 τFRAME periods

tSPW SCLK positive or negative pulse width 0.4tSCLK 0.6tSCLK ns

tDOHD(2)(3) SCLK falling edge to old DOUT invalid (hold time) 5 ns

tDOPD(2) SCLK falling edge to new DOUT valid (propagation delay) 12 ns

tDDO(2) Valid DOUT to rising edge of FSYNC 0 ns

tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns

tDIHD(3) Old DIN valid to falling edge of SCLK (hold time) 6 ns

(1) The ADS1271 automatically detects either frame period (only 256 or 512 allowed).(2) Load on DOUT = 20pF.(3) tDOHD (DOUT hold time) and tDIHD (DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient

temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.


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TYPICAL CHARACTERISTICS

TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.

Figure 1

OUTPUT SPECTRUM

10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

−140

−160

Am

plitu

de(d

B)

10k 100k

High−Speed ModefIN = 1kHz, −0.5dBFS32,768 Points

Figure 2

OUTPUT SPECTRUM

10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

−140

−160

Am

plitu

de(d

B)

10k 100k

High−Speed ModefIN = 1kHz, −20dBFS32,768 Points

Figure 3

OUTPUT SPECTRUM

0.1 1 10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

−140

−160

−180

Am

plitu

de(d

B)

10k 100k

High−Speed ModeShorted Input2,097,152 Points

Figure 4

NOISE HISTOGRAM− 5

0− 4

5− 4

0− 3

5− 3

0− 2

5− 2

0− 1

5− 1

0 − 5 0 5 10 15 20 25 30 35 40 45 50

Output (µV)

420k

360k

300k

240k

180k

120k

60k

0

Num

ber

ofO

ccu

rren

ces

High−Speed ModeShorted Input2,097,152 Points

Figure 5

OUTPUT SPECTRUM

10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

−140

−160

Am

plitu

de(d

B)

10k 100k

High−Resolution ModefIN = 1kHz, −0.5dBFS32,768 Points

Figure 6

OUTPUT SPECTRUM

10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

−140

−160

Am

plitu

de(d

B)

10k 100k

High−Resolution ModefIN = 1kHz, −20dBFS32,768 Points


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TYPICAL CHARACTERISTICS (continued)


Figure 7

OUTPUT SPECTRUM

0.1 1 10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

−140

−160

−180

Am

plitu

de(d

B)

10k 100k

High−Resolution ModeShorted Input1,048,576 Points

Figure 8

NOISE HISTOGRAM

− 30

− 28

− 26

− 24

− 22

− 20

− 18

− 16

− 14

− 12

− 10 − 8 − 6 − 4 − 2 0 2 4 6 8

10

12

14

16

18

20

22

24

26

28

30

Output (µV)

210k

180k

150k

120k

90k

60k

30k

0

Num

ber

ofO

ccur

renc

es

High−Resolution ModeShorted Input1,048,576 Points

Figure 9

OUTPUT SPECTRUM

10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

−140

−160

Am

plitu

de(d

B)

10k 100k

Low−Power ModefIN = 1kHz, −0.5dBFS32,768 Points

Figure 10

OUTPUT SPECTRUM

10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

−140

−160

Am

plitu

de(d

B)

10k 100k

Low−Power ModefIN = 1kHz, −20dBFS32,768 Points

Figure 11

OUTPUT SPECTRUM

0.1 1 10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

−140

−160

−180

Am

plitu

de(d

B)

10k 100k

Low−Power ModeShorted Input1,048,576 Points

Figure 12

NOISE HISTOGRAM

− 50

− 45

− 40

− 35

− 30

− 25

− 20

− 15

− 10 − 5 0 5

10

15

20

25

30

35

40

45

50

Output (µV)

200k

180k

160k

140k

120k

100k

80k

60k

40k

20k

0

Num

ber

ofO

ccu

rren

ces

Low−Power ModeShorted Input1,048,576 Points


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Figure 13

TOTAL HARMONIC DISTORTIONvs FREQUENCY

10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

TH

D,T

HD

+N

Am

plitu

de(d

B)

10k 100k

High−Speed ModeVIN = −0.5dBFS

THD+N

THD

Figure 14

TOTAL HARMONIC DISTORTIONvs INPUT LEVEL

−120 −100 −80 −60 −40 −20 0

Input Amplitude (dBFS)

0

−20

−40

−60

−80

−100

−120

−140

TH

D,T

HD

+N

Am

plitu

de(d

B)

High−Speed ModefIN = 1kHz

THD+N

THD

Figure 15


10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

TH

D,T

HD

+N

Am

plitu

de(d

B)

10k 100k

High−Resolution ModeVIN = −0.5dBFS

THD+N

THD

Figure 16


−120 −100 −80 −60 −40 −20 0


0

−20

−40

−60

−80

−100

−120

−140

TH

D,T

HD

+N

Am

plitu

de(d

B)

High−Resolution ModefIN = 1kHz

THD+N

THD

Figure 17


10 100 1k

Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

TH

D,T

HD

+N

Am

plitu

de(d

B)

10k 100k

Low−Power ModeVIN = −0.5dBFS

THD+N

THD

Figure 18


−120 −100 −80 −60 −40 −20 0


0

−20

−40

−60

−80

−100

−120

−140

TH

D,T

HD

+N

Am

plitu

de(d

B)

Low−Power ModefIN = 1kHz

THD+N

THD


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Figure 19

ABSOLUTE OFFSET DRIFT HISTOGRAM

1 3 5 7 9 11 13 15 17 19 21

Absolute Offset Drift (µV/C)

60

50

40

30

20

10

0

Occ

urr

ence

s(%

)

outliers: T < −20C

30 units, based on 20C intervalsover the range −40C to +105C

Figure 20

GAIN DRIFT HISTOGRAM

− 6.0

− 5.5

− 5.0

− 4.5

− 4.0

− 3.5

− 3.0

− 2.5

− 2.0

− 1.5

− 1.0

− 0.5 0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Gain Drift (ppm/C)

15

10

5

0

Occ

urre

nce

s(%

)

30 units, based on 20Cintervals over the range

−40C to +105C

Figure 21

OFFSET POWER−ON WARMUP

0 10 20 30 40 50 60

Time After Power−On (s)

40

30

20

10

0

−10

−20

−30

−40

Nor

mal

ized

Offs

et(µ

V)

High−Speed ModeDVDD = 3.3V

ResponseBand

Figure 22

GAIN ERROR POWER−ON WARMUP

0 10 20 30 40 50 60

Time After Power−On (s)

10

8

6

4

2

0

−2

−4

−6

−8

−10

No

rma

lized

Gai

nE

rror

(pp

m)

High−Speed ModeDVDD = 3.3V

ResponseBand

Figure 23

UNCALIBRATED OFFSET HISTOGRAM

− 50

0

− 45

0

− 40

0

− 35

0

− 30

0

− 25

0

− 20

0

− 15

0

− 10

0

− 50 0 50

100

150

200

250

300

Uncalibrated Offset (µV)

30

20

10

0

Un

its(%

)

High−Speed Mode30 Units

Figure 24

GAIN ERROR HISTOGRAM

− 235

0

− 230

0

− 225

0

− 220

0

− 215

0

− 210

0

− 205

0

− 200

0

− 195

0

− 190

0

− 185

0

− 180

0

− 175

0

− 170

0

− 165

0

− 160

0

Gain Error (ppm)

50

40

30

20

10

0

Un

its(%

)

High−Speed Mode30 Units


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Figure 25

REFERENCE INPUT DIFFERENTIAL IMPEDANCEvs TEMPERATURE

−40 −20 0 20 40 60 80 100

Temperature (C)

4280

4260

4240

4220

4200

4180

4160

4140

4120

4100

Ref

ere

nce

Inpu

tIm

peda

nce

(Ω)

120 125

High−Speed andHigh−Resolution Modes

Figure 26

REFERENCE INPUT DIFFERENTIAL IMPEDANCEvs TEMPERATURE

−40 −20 0 20 40 60 80 100

Temperature (C)

8900

8800

8700

8600

8500

8400

8300

8200

Ref

eren

ceIn

put

Imp

edan

ce(Ω

)

120 125

Low−Power Mode

Figure 27

ANALOG INPUT DIFFERENTIAL IMPEDANCEvs TEMPERATURE

−40 −20 0 20 40 60 80 100

Temperature (C)

16550

16500

16450

16400

16350

16300

16250

16200

16150

Ana

log

Inp

utIm

ped

anc

e(Ω

)

120 125

High−Speed andHigh−Resolution Modes

Figure 28

ANALOG INPUT DIFFERENTIAL IMPEDANCEvs TEMPERATURE

−40 −20 0 20 40 60 80 100

Temperature (C)

33200

33000

32800

32600

32400

32200

32000

Ana

log

Inp

utIm

ped

ance

(Ω)

120 125

Low−Power Mode

Figure 29

INTEGRAL NONLINEARITY vs TEMPERATURE

−40 −20 0 20 40 60 80 100

Temperature (C)

14

12

10

8

6

4

2

0

INL

(ppm

)

120 125

High−Resolution

High−Speed

Low−Power

Figure 30

LINEARITY ERROR vs INPUT LEVEL

−2.5 −2.0 2.0−1.5 1.5−1.0 1.0−0.5 0.50

VIN (V)

10

8

6

4

2

0

−2

−4

−6

−8

−10

Line

arit

yE

rro

r(p

pm

)

2.5

High−Speed Mode

T = +25C

T = +125C

T = +105C

T = −40C


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13



Figure 31

NOISE vs AVDD

4.75 4.85 5.154.95 5.05

AVDD (V)

20

18

16

14

12

10

8

6

4

2

0

RM

SN

oise

(µV

)

5.25

High−Resolution

High−Speed

Low−Power

Figure 32

NOISE vs DVDD

1.6 2.0 2.21.8 3.2 3.42.4 2.6 2.8 3.0

DVDD (V)

20

18

16

14

12

10

8

6

4

2

0

RM

SN

oise

(µV

)

3.6

High−Resolution

High−Speed

Low−Power

Figure 33

NOISE vs TEMPERATURE

−40 −20 0 20 40 60 80 100

Temperature (C)

12

10

8

6

4

2

0

RM

SN

oise

(µV

)

120 125

High−Resolution

High−Speed

Low−Power

Figure 34

NOISE vs INPUT LEVEL

−2.5 −2.0 −1.5 −1.0 1.51.0−0.5 0.50

VIN (V)

20

18

16

14

12

10

8

6

4

2

0

RM

SN

ois

e(µ

V)

2.52.0

High−Resolution

High−Speed Low−Power

Figure 35

AVDD CURRENT vs TEMPERATURE

−40 −20 0 20 40 60 80 100

Temperature (C)

22

20

18

16

14

12

10

8

6

4

2

0

AV

DD

Cur

rent

(mA

)

120 125

High−Speed andHigh−Resolution

Low−Power

Figure 36

DVDD CURRENT vs TEMPERATURE

−40 −20 0 20 40 60 80 100

Temperature (C)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

DV

DD

Cur

rent

(mA

)

120 125

Low−Power

High−Resolution

High−Speed


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14



Figure 37

OFFSET AND GAIN ERROR vs VREF

0.5

100

75

50

25

0

−25

−50

400

300

200

100

0

−100

−2001.0 1.5 2.0

VREF (V)

Nor

mal

ize

dO

ffset

(µV

)

Nor

mal

ized

Ga

inE

rror

(ppm

)

2.5 3.0

See Electrical Characteristics for VREF Operating Range

Offset

Gain Error

Figure 38

NOISE vs VREF

0.5

12

10

8

6

4

2

01.0 1.5

VREF and Common−Mode Input Voltage (V)

RM

SN

ois

e(µ

V)

2.0 2.5 3.0

High−Speed

Low−Power

High−Resolution


Figure 39

INTEGRAL NONLINEARITY vs VREF

0.5

12

10

8

6

4

2

01.0 1.5

VREF (V)

INL

(pp

m)

2.0 2.5 3.0


Figure 40

TOTAL HARMONIC DISTORTION vs VREF

0.5

−100

−105

−110

−115

−1201.51.0

VREF (V)

TH

D(d

B)

2.0 2.5

High−Speed ModefIN = 1kHz, −0.5dBFS


Figure 41

COMMON−MODE REJECTION RATIOvs FREQUENCY

10 100 1k

Common−Mode Signal Frequency (Hz)

0

−20

−40

−60

−80

−100

−120

−140

CM

RR

(dB

)

10k 1M100k

High−Speed Mode

Figure 42

NOISE AND OFFSETvs COMMON−MODE INPUT VOLTAGE

−0.5 0.50

20

18

16

14

12

10

8

6

4

2

01.0 1.5

Common−Mode Input Voltage (V)

RM

SN

oise

(µV

)

70

50

30

10

−10

−30

−50

−70

−90

−110

−130

No

rmal

ize

dO

ffset

(µV

)

2.0 2.5 3.5 4.5 5.03.0 4.0

High−Speed Mode

Offset

Noise


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15

OVERVIEWThe ADS1271 is a 24-bit, delta-sigma ADC. It offers thecombination of outstanding DC accuracy and superior ACperformance. Figure 43 shows the block diagram for theADS1271. The ADS1271 converter is comprised of anadvanced, 6th-order, chopper-stabilized, delta-sigmamodulator followed by a low-ripple, linear phase FIR filter.The modulator measures the differential input signal,VIN = (AINP – AINN), against the differential reference,VREF = (VREFP – VREFN). The digital filter receives themodulator signal and provides a low-noise digital output.To allow tradeoffs among speed, resolution, and power,three modes of operation are supported on the ADS1271:High-Speed, High-Resolution, and Low-Power. Table 1summarizes the performance of each mode.

In High-Speed mode, the data rate is 105kSPS; inHigh-Resolution mode, the SNR = 109dB; and inLow-Power mode, the power dissipation is only 35mW.The digital filter can be bypassed, enabling direct accessto the modulator output.

The ADS1271 is configured by simply setting theappropriate IO pins—there are no registers to program.Data is retrieved over a serial interface that supports bothSPI and Frame-Sync formats. The ADS1271 has adaisy-chainable output and the ability to synchronizeexternally, so it can be used conveniently in multichannelsystems.

∆ΣModulator

DigitalFilter

VREFP

VREF

VIN

VREFN

Σ

Σ

DRDY/FSYNC

SCLK

DOUT

DIN

FORMAT

SYNC/PDWN

MODE

CLK

SPIor

Frame−SyncSerial

Interface

AINP

AINN

Figure 43. Block Diagram

Table 1. Operating Mode Performance Summary

MODE DATA RATE (SPS) PASSBAND (Hz) SNR (dB) NOISE (µVRMS) POWER (mW)

High-Speed 105,469 47,777 106 9.0 92

High-Resolution 52,734 23,889 109 6.5 90

Low-Power 52,734 23,889 106 9.0 35


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16

ANALOG INPUTS (AINP, AINN)

The ADS1271 measures the differential input signalVIN = (AINP – AINN) against the differential referenceVREF = (VREFP – VREFN). The most positive measurabledifferential input is +VREF, which produces the mostpositive digital output code of 7FFFFFh. Likewise, themost negative measurable differential input is −VREF,which produces the most negative digital output code of800000h.

While the ADS1271 measures the differential input signal,the absolute input voltage is also important. This is thevoltage on either input (AINP or AINN) with respect toAGND. The range for this voltage is:

−0.1V < (AINN or AINP) < AVDD +0.1V

If either input is taken below –0.4V or above (AVDD + 0.4),ESD protection diodes on the inputs may turn on.

If these conditions are possible, external Schottky clampdiodes or series resistors may be required to limit the inputcurrent to safe values (see Absolute Maximum Ratings).

The ADS1271 uses switched-capacitor circuitry tomeasure the input voltage. Internal capacitors are chargedby the inputs and then discharged. Figure 44 shows aconceptual diagram of these circuits. Switch S2represents the net effect of the modulator circuitry indischarging the sampling capacitor; the actualimplementation is different. The timing for switches S1 andS2 is shown in Figure 45. The sampling time (tSAMPLE) isthe inverse of modulator sampling frequency (fMOD) and isa function of the mode, format, and frequency of CLK, asshown in Table 2. When using the Frame-Sync format withHigh-Resolution or Low-Power modes, the ratio betweenfMOD and fCLK depends on the frame period that is set by theFSYNC input.

ESD Protection

AVDDAGND

AVDD

AINP

9pF

AINN

AGND

S1

S1

S2

Figure 44. Equivalent Analog Input Circuitry

ON

OFFS1

ON

OFFS2

tSAMPLE = 1/fMOD

Figure 45. S1 and S2 Switch Timing for Figure 44

Table 2. Modulator Frequency for the DifferentMode and Format Settings

MODEINTERFACE

FORMAT fMOD

High-Speed SPI or Frame-Sync fCLK/4

High-ResolutionSPI fCLK/4

High-ResolutionFrame-Sync fCLK/4 or fCLK/2

Low-PowerSPI fCLK/8

Low-PowerFrame-Sync fCLK/8 or fCLK/4

The average load presented by the switched capacitorinput can be modeled with an effective differentialimpedance, as shown in Figure 46. Note that the effectiveimpedance is a function of fMOD.

AINP

AINN

Zeff = 16.4kΩ × (6.75MHz/fMOD )

Figure 46. Effective Input Impedances

The ADS1271 is a very high-performance ADC. Foroptimum performance, it is critical that the appropriatecircuitry be used to drive the ADS1271 inputs. See theApplication Information section for the recommendedcircuits.


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17

VOLTAGE REFERENCE INPUTS (VREFP,VREFN)

The voltage reference for the ADS1271 ADC is thedifferential voltage between VREFP and VREFN:VREF = (VREFP−VREFN). The reference inputs use astructure similar to that of the analog inputs with theequivalent circuitry on the reference inputs shown inFigure 47. As with the analog inputs, the load presented bythe switched capacitor can be modeled with an effectiveimpedance, as shown in Figure 48.

ESDProtection

AVDDAVDD

VREFNVREFP

Figure 47. Equivalent Reference Input Circuitry

VREFP VREFN

Zeff = 4.2kΩ × (6.75MHz/fMOD)

Figure 48. Effective Reference Impedance

ESD diodes protect the reference inputs. To keep thesediodes from turning on, make sure the voltages on thereference pins do not go below AGND by more than 0.4V,and likewise do not exceed AVDD by 0.4V. If theseconditions are possible, external Schottky clamp diodes orseries resistors may be required to limit the input currentto safe values (see Absolute Maximum Ratings).

Note that the valid operating range of the reference inputsis limited to the following:

For the ADS1271:

−0.1V ≤ VREFN ≤ VREFP − 2V

VREFN + 2V ≤ VREFP ≤ AVDD − 0.5V

For the ADS1271B:

−0.1V ≤ VREFN ≤ VREFP − 0.5V

VREFN + 0.5V ≤ VREFP ≤ AVDD + 0.1V

A high-quality reference voltage with the appropriate drivestrength is essential for achieving the best performance fromthe ADS1271. Noise and drift on the reference degradeoverall system performance. See the Application Informationsection for example reference circuits.


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18

CLOCK INPUT (CLK)

The ADS1271 requires an external clock signal to beapplied to the CLK input pin. As with any high-speed dataconverter, a high-quality, low-jitter clock is essential foroptimum performance. Crystal clock oscillators are therecommended clock source. Make sure to avoid excessringing on the clock input; keeping the clock trace as shortas possible using a 50Ω series resistor will help.

The ratio between the clock frequency and output data rateis a function of the mode and format. Table 3 shows theratios when the SPI format is selected. Also included in thistable is the typical CLK frequency and the corresponding

data rate. When High-Speed mode is used, eachconversion takes 256 CLK periods. WhenHigh-Resolution or Low-Power modes are selected, theconversions take 512 CLK periods.

Table 4 shows the ratios when the Frame-Sync format isselected. When using the Frame-Sync format in eitherHigh-Resolution or Low-Power mode, the fCLK/fDATA ratiocan be 256 or 512. The ADS1271 automatically detectswhich ratio is being used. Using a ratio of 256 allows theCLK frequency to be reduced by a factor of two whilemaintaining the same data rate. The output data ratescales with the clock frequency. See the Serial Interfacesection for more details on the Frame-Sync operation.

Table 3. Clock Ratios for SPI Format

MODE SELECTION fCLK/fDATA TYPICAL f CLK (MHz) CORRESPONDING DATA RATE (SPS)

High-Speed 256 27 105,469

High-Resolution 512 27 52,734

Low-Power 512 27 52,734

Table 4. Clock Ratios for Frame-Sync Format

MODE SELECTION fCLK/fFRAME TYPICAL f CLK (MHz) CORRESPONDING DATA RATE (SPS)

High-Speed 256 27 105,469

High-Resolution256 13.5 52,734

High-Resolution512 27 52,734

Low-Power256 13.5 52,734

Low-Power512 27 52,734


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19

MODE SELECTION (MODE)

The ADS1271 supports three modes of operation:High-Speed, High-Resolution, and Low-Power. The modeselection is determined by the status of the digital inputMODE pin, as shown in Table 5. A high impedance, orfloating, condition allows the MODE pin to support a thirdstate. The ADS1271 constantly monitors the status of theMODE pin during operation and responds to a change instatus after 12,288 CLK periods. When floating the MODEpin, keep the total capacitance on the pin less than 100pFand the resistive loading greater than 10MΩ to ensureproper operation. Changing the mode clears the internaloffset calibration value. If onboard offset calibration isbeing used, be sure to recalibrate after a mode change.

When daisy-chaining multiple ADS1271s together andoperating in High-Resolution mode (MODE pin floating), theMODE pin of each device must be isolated from one another;this ensures proper device operation. The MODE pins can betied together for High-Speed and Low-Power modes.

Table 5. Mode Selection

MODE PIN STATUS MODE SELECTION

Logic Low (DGND) High-Speed

Float(1) High-Resolution

Logic High (DVDD) Low-Power

(1) Load on MODE: C < 100pF, R > 10MΩ.

When using the SPI format, DRDY is held high after amode change occurs until settled (or valid) data is ready,as shown in Figure 49.

In Frame-Sync format, the DOUT pin is held low after amode change occurs until settled data is ready, as shownin Figure 49. Data can be read from the device to detectwhen DOUT changes to logic 1, indicating valid data.

FORMAT SELECTION (FORMAT)

To help connect easily to either microcontrollers or DSPs,the ADS1271 supports two formats for the serial interface:an SPI-compatible interface and a Frame-Sync interface.The format is selected by the FORMAT pin, as shown inTable 6. If the status of this pin changes, perform a syncoperation afterwards to ensure proper operation. Themodulator output mode does not require a sync operation.

Table 6. Format Selection

FORMAT PIN STATUS SERIAL INTERFACE FORMAT

Logic Low (DGND) SPI

Float(1) Modulator Output(2)

Logic High (DVDD) Frame-Sync

(1) Load on FORMAT: C < 100pF, R > 10MΩ.(2) See Modulator Output section.

MODEPin

ADS1271Mode

High−Speed

SYMBOL

tMD Time to register MODE changes CLK periods

tNDR Time for new data to be ready 128Conversions

(1/fDATA)

MIN TYP MAX UNITSDESCRIPTION

Low−Power

Low−Power ModeValid Data Ready

DRDYSPI

Format

Frame−SyncFormat

CLK

tMD

DOUT

Low−Power ModeValid Data on DOUT

tNDR

tNDR

12,288

Figure 49. Mode Change Timing


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20

SYNCHRONIZATION

The SYNC/PDWN pin has two functions. When pulsed, itsynchronizes the start of conversions and, if held low formore than 219 CLK cycles (tSYN), places the ADS1271 inPower-Down mode. The SYNC/PDWN pin can be left highfor continuous data acquisition. See the Power-Down andOffset Calibration section for more details.

The ADS1271 can be synchronized by pulsing theSYNC/PDWN pin low and then returning the pin high.When the pin goes low, the conversion process is stopped,and the internal counters used by the digital filter are reset.When the SYNC/PDWN pin is returned high, theconversion process is restarted. Synchronization allowsthe conversion to be aligned with an external event; forexample, the changing of an external multiplexer on theanalog inputs, or by a reference timing pulse.

The SYNC/PDWN pin is capable of synchronizing multipleADS1271s to within the same CLK cycle. Figure 50 showsthe timing requirement of SYNC/PDWN and CLK in SPIformat.

Figure 51 shows the timing requirement for Frame-Syncformat.

After synchronization, indication of valid data depends onthe whether SPI or Frame-Sync format was used.

In the SPI format, DRDY goes high as soon asSYNC/PDWN is taken low, as shown in Figure 50. AfterSYNC/PDWN is returned high, DRDY stays high while thedigital filter is settling. Once valid data is ready for retrieval,DRDY goes low.

In the Frame-Sync format, DOUT goes low as soon asSYNC/PDWN is taken low, as shown in Figure 51. AfterSYNC/PDWN is returned high, DOUT stays low while thedigital filter is settling. Once valid data is ready for retrieval,DOUT begins to output valid data. For propersynchronization, FSYNC, SCLK, and CLK must beestablished before taking SYNC/PDWN high, and mustthen remain running.

CLK

DRDY

SYNC/PDWNtNDR

tSYN

tCSHD

tSCSU

SYMBOL

tSCSU

Synchronize pulse width 218

5

10

1 CLK periods

tCSHD

Time for new data to be ready 128 Conversions (1/fDATA)


tSYN

SYNC/PWDN to CLK setup time ns

tNDR

CLK to SYNC/PWDN hold time ns

Figure 50. Synchronization Timing for SPI format

FSYNC

Valid DataDOUT

tNDR

SYMBOL

tSYN Synchronize pulse width 2181

5

10

CLK periods

tNDR Time for new data to be ready 128 129 Conversions (1/fDATA)


tSCSU SYNC/PWDN to CLK setup time ns

tCSHD CLK to SYNC/PWDN hold time ns

CLK

SYNC/PDWN tSYN

tCSHD

tSCSU

Figure 51. Synchronization Timing for Frame-Sync Format


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21

POWER-DOWN AND OFFSET CALIBRATION

In addition to controlling synchronization, theSYNC/PDWN pin also serves as the control forPower-Down mode and offset calibration. To enter thismode, hold the SYNC/PDWN pin low for at least 219 CLKperiods. While in Power-Down mode, both the analog anddigital circuitry are completely deactivated. The digitalinputs are internally disabled so that is not necessary toshut down CLK and SCLK. To exit Power-Down mode,return SYNC/PDWN high on the rising edge of CLK.

The ADS1271 uses a chopper-stabilized modulator toprovide inherently very low offset drift. To further minimizeoffset, the ADS1271 automatically performs an offsetself-calibration when exiting Power-Down mode. Whenpower down completes, the offset self-calibration beginswith the inputs AINP and AINN automaticallydisconnected from the signal source and internally shortedtogether. There is no need to modify the signal sourceapplied to the analog inputs during this calibration.It is critical for the reference voltage to be stable whenexiting Power-Down mode; otherwise, the calibration willbe corrupted.

The offset self-calibration only removes offset errors internalto the device, not offset errors due to external sources.

NOTE: When an offset self-calibration is performed, theresulting offset value will vary each time within thepeak-to-peak noise range of the converter. In High-Speedmode, this is typically 178 LSBs.

The offset calibration value is cleared whenever the devicemode is changed (for example, from High-Speed mode toHigh-Resolution mode).

When using the SPI format, DRDY will stay high afterexiting Power-Down mode while the digital filter settles, asshown in Figure 52.

When using the Frame-Sync format, DOUT will stay lowafter exiting Power-Down mode while the digital filtersettles, as shown in Figure 53.

NOTE: In Power-Down mode, the inputs of the ADS1271must be driven (do not float) and the device drives theoutputs driven to a DC level.

Status

CLK

Converting Sync Power Down Converting

Post−CalibrationData Ready

Offset Cal and Filter Settling

DRDY

• • •• • •

SYNC/PDWN tPDWN tOFS

SYMBOL

tPDWN pulse width to enter Power−Down mode 219 CLK periods

tOFS Time for offset calibration and filter settling 256Conversions

(1/fDATA)


SYNC/PDWN

Figure 52. Power-Down Timing for SPI format

SYMBOL

tPDWN pulse width to enter Power−Down mode 219 CLK periods

tOFS Time for offset calibration and filter settling 257256Conversions

(1/fDATA)


Status

CLK

FSYNC

DOUT

• • •• • •

SYNC/PDWN tOFStPDWN

Converting Sync Power Down Converting

Post−Calibration Data

Offset Cal and Filter Settling

SYNC/PDWN

Figure 53. Power-Down Timing for Frame-Sync Format


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22

POWER-UP SEQUENCE

The analog and digital supplies should be applied beforeany analog or digital input is driven. The power suppliesmay be sequenced in any order. Once the supplies and thevoltage reference inputs have stabilized, data can be readfrom the device.

FREQUENCY RESPONSE

The digital filter sets the overall frequency response. The filteruses a multi-stage FIR topology to provide linear phase withminimal passband ripple and high stopband attenuation. Theoversampling ratio of the digital filter (that is, the ratio of themodulator sampling to the output data rate: fMOD/fDATA) is afunction of the selected mode, as shown in Table 7. fMOD isCLK/2, CLK/4, or CLK/8, depending on the mode.

Table 7. Oversampling Ratio versus Mode

MODE OVERSAMPLING RATIO (f MOD/fDATA)

High-Speed 64

High-Resolution 128

Low-Power 64

High-Speed and Low-Power Modes

The digital filter configuration is the same in bothHigh-Speed and Low-Power modes with the oversamplingratio set to 64. Figure 54 shows the frequency response inHigh-Speed and Low-Power modes normalized to fDATA.Figure 55 shows the passband ripple. The transition frompassband to stop band is illustrated in Figure 56. Theoverall frequency response repeats at 64x multiples of themodulator frequency fMOD, as shown in Figure 57. Theseimage frequencies, if present in the signal and notexternally filtered, will fold back (or alias) into thepassband, causing errors. The stop-band of the ADS1271provides 100dB attenuation of frequencies that begin justbeyond the passband and continue out to fMOD. Placing anantialiasing, low-pass filter in front of the ADS1271 inputsis recommended to limit possible high-amplitudeout-of-band signals and noise.

0

−20

−40

−60

−80

−100

−120

−1400.4

Normalized Input Frequency (fIN/fDATA)

Am

plitu

de(d

B)

0 0.2 0.6 0.8 1.0

Figure 54. Frequency Response for High-Speedand Low-Power Modes

0.02

0

−0.02

−0.04

−0.06

−0.08

−0.100.2


Am

plitu

de(d

B)

0 0.1 0.3 0.4 0.5 0.6

Figure 55. Passband Response for High-Speedand Low-Power Modes


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23

0

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10


Am

plitu

de(d

B)

0.45 0.47 0.49 0.51 0.53 0.55

Figure 56. Transition Band Response forHigh-Speed and Low-Power Modes

20

0

−20

−40

−60

−80

−100

−120

−140

−160

Input Frequency (fIN/fDATA)

Ga

in(d

B)

0 16 32 48 64

Figure 57. Frequency Response Out to f MOD forHigh-Speed and Low-Power Modes

High-Resolution Mode

The oversampling ratio is 128 in High-Resolution mode.Figure 58 shows the frequency response inHigh-Resolution mode normalized to fDATA. Figure 59shows the passband ripple, and the transition frompassband to stop band is illustrated in Figure 60. Theoverall frequency response repeats at multiples of themodulator frequency fMOD, (128 × fDATA), as shown inFigure 61. The stop band of the ADS1271 provides 100dBattenuation of frequencies that begin just beyond thepassband and continue out to fMOD. Placing anantialiasing, low-pass filter in front of the ADS1271 inputsis recommended to limit possible high-amplitudeout-of-band signals and noise.

0

−20

−40

−60

−80

−100

−120

−1400.50


Am

plitu

de(d

B)

0 0.25 0.75 1

Figure 58. Frequency Response forHigh-Resolution Mode

0.02

0

−0.02

−0.04

−0.06

−0.08

−0.100.2


Am

plitu

de(d

B)

0 0.1 0.3 0.4 0.5 0.6

Figure 59. Passband Response forHigh-Resolution Mode


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24

0

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10


Am

plitu

de(d

B)

0.45 0.47 0.49 0.51 0.53 0.55

Figure 60. Transition Band Response forHigh-Resolution Mode

20

0

−20

−40

−60

−80

−100

−120

−140

−160

Ga

in(d

B)


0 32 64 96 128

Figure 61. Frequency Response out to f MOD forHigh-Resolution Mode

Table 8. Antialiasing Filter Order Image Rejection

ANTIALIASING

IMAGE REJECTION (dB)(f−3dB at fDATA)

ANTIALIASINGFILTER ORDER HS, LP HR

1 39 45

2 75 87

3 111 129

PHASE RESPONSE

The ADS1271 incorporates a multiple stage, linear phasedigital filter. Linear phase filters exhibit constant delay timeversus input frequency (constant group delay). Thismeans the time delay from any instant of the input signalto the same instant of the output data is constant and isindependent of input signal frequency. This behaviorresults in essentially zero phase errors when analyzingmulti-tone signals.

SETTLING TIME

As with frequency and phase response, the digital filteralso determines settling time. Figure 62 shows the outputsettling behavior after a step change on the analog inputsnormalized to conversion periods. The X axis is given inunits of conversion. Note that after the step change on theinput occurs, the output data changes very little prior to 30conversion periods. The output data is fully settled after 76conversion periods for High-Speed and Low-Powermodes, and 78 conversions for High-Resolution mode.

100

0

%S

ettl

ing

Conversions (1/fDATA)

0 2010 4030 6050 8070

Fully Settled Dataat 76 Conversions

(78 Conversions forHigh−Resolution mode)

Initial Value

Final Value

Figure 62. Settling Time for All Power Modes


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25

DATA FORMAT

The ADS1271 outputs 24 bits of data in two’s complementformat.

A positive full-scale input produces an output code of7FFFFFh, and the negative full-scale input produces anoutput code of 800000h. The output clips at these codesfor signals exceeding full-scale. Table 9 summarizes theideal output codes for different input signals.

Table 9. Ideal Output Code versus Input Signal

INPUT SIGNAL VIN(AINP − AINN) IDEAL OUTPUT CODE(1)

+VREF 7FFFFFh

+VREF

223 1

000001h

0 000000h

−VREF

223 1

FFFFFFh

−VREF 223

223 1 800000h

(1) Excludes effects of noise, INL, offset and gain errors.

SERIAL INTERFACE

Data is retrieved from the ADS1271 using the serialinterface. To provide easy connection to eithermicrocontrollers or DSPs, two formats are available for theinterface: SPI and Frame-Sync. The FORMAT pin selectsthe interface. The same pins are used for both interfaces(SCLK, DRDY/FSYNC, DOUT and DIN), though theirrespective functionality depends on the particular interfaceselected.

SPI SERIAL INTERFACE

The SPI-compatible format is a simple read-only interface.Data ready for retrieval is indicated by the DRDY outputand is shifted out on the falling edge of SCLK, MSB first.The interface can be daisy-chained using the DIN inputwhen using multiple ADS1271s. See the Daisy-Chainingsection for more information.

SCLK (SPI Format)

The serial clock (SCLK) features a Schmitt-triggered inputand shifts out data on DOUT on the falling edge. It alsoshifts in data on the falling edge on DIN when this pin isbeing used for daisy-chaining. The device shifts data outon the falling edge and the user shifts this data in on the

rising edge. Even though the SCLK input has hysteresis,it is recommended to keep SCLK as clean as possible toprevent glitches from accidentally shifting the data. SCLKshould be held low after data retrieval. SCLK may be runas fast as the CLK frequency. SCLK may be either infree-running or stop-clock operation betweenconversions. For best performance, limit fSCLK/fCLK to ratiosof 1, 1/2, 1/4, 1/8, etc. When the device is configured formodulator output, SCLK becomes the modulator clockoutput (see the Modulator Output section).

For the fSCLK/fCLK ratio of 1, care must be observed thatthese signals are not tied together. After Power On, SCLKremains an output until a few clocks have been receivedon the CLK input.

DRDY/FSYNC

In the SPI format, this pin functions as the DRDY output. Itgoes low when data is ready for retrieval and then returnshigh on the falling edge of the first subsequent SCLK. If datais not retrieved (that is, SCLK is held low), DRDY will pulsehigh just before the next conversion data is ready, as shownin Figure 63. The new data is loaded within the ADS1271 oneCLK cycle before DRDY goes low. All data must be shiftedout before this time to avoid being overwritten.

DRDY

SCLK

1/fDATA1/fCLK

Figure 63. DRDY Timing with No Readback

DOUT

The conversion data is shifted out on DOUT. The MSBdata is valid on DOUT when DRDY goes low. Thesubsequent bits are shifted out with each falling edge ofSCLK. If daisy-chaining, the data shifted in using DIN willappear on DOUT after all 24 bits have been shifted out.When the device is configured for modulator output, DOUTbecomes the modulator data output (see the ModulatorOutput section).

DIN

This input is used when multiple ADS1271s are to bedaisy-chained together. The DOUT pin of the first deviceconnects to the DIN pin of the next, etc. It can be used witheither the SPI or Frame-Sync formats. Data is shifted in onthe falling edge of SCLK. When using only one ADS1271,tie DIN low. See the Daisy-Chaining section for moreinformation.


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FRAME-SYNC SERIAL INTERFACE

Frame-Sync format is similar to the interface often used onaudio ADCs. It operates in slave fashion—the user mustsupply framing signal FSYNC (similar to the left/right clockon stereo audio ADCs) and the serial clock SCLK (similarto the bit clock on audio ADCs). The data is output MSBfirst or left-justified. When using Frame-Sync format, theCLK, FSYNC and SCLK inputs must be synchronizedtogether, as described in the following sub-sections.

SCLK (Frame-Sync Format)

The serial clock (SCLK) features a Schmitt-triggered inputand shifts out data on DOUT on the falling edge. It alsoshifts in data on the falling edge on DIN when this pin isbeing used for daisy-chaining. Even though SCLK hashysteresis, it is recommended to keep SCLK as clean aspossible to prevent glitches from accidentally shifting thedata. When using Frame-Sync format, SCLK must runcontinuously. If it is shut down, the data readback will becorrupted. Frame-Sync format requires a specificrelationship between SCLK and FSYNC, determined bythe mode shown in Table 10. When the device isconfigured for modulator output, SCLK becomes themodulator clock output (see the Modulator Outputsection).

Table 10. SCLK Period When Using Frame-SyncFormat

MODE REQUIRED SCLK PERIOD

High-Speed τFRAME/64

High-Resolution τFRAME/128

Low-Power τFRAME/64

DRDY/FSYNC

In Frame-Sync format, this pin is used as the FSYNC input.The frame-sync input (FSYNC) sets the frame period. Therequired FSYNC periods are shown in Table 11. ForHigh-Speed mode, the FSYNC period must be 256 CLKperiods. For both High-Resolution and Low-Power modes,the FSYNC period can be either 512 or 256 CLK periods;the ADS1271 will automatically detect which is beingused. If the FSYNC period is not the proper value, datareadback will be corrupted. It is recommended thatFSYNC be aligned with the falling edge of SCLK.

Table 11. FSYNC Period

MODE REQUIRED FSYNC PERIOD

High-Speed 256 CLK Periods

High-Resolution 256 or 512 CLK periods

Low-Power 256 or 512 CLK periods

DOUT

The conversion data is shifted out on DOUT. The MSBdata becomes valid on DOUT on the CLK rising edge priorto FSYNC going high. The subsequent bits are shifted outwith each falling edge of SCLK. If daisy-chaining, the datashifted in using DIN will appear on DOUT after all 24 bitshave been shifted out. When the device is configured formodulator output, DOUT becomes the modulator dataoutput (see the Modulator Output section).

DIN

This input is used when multiple ADS1271s are to bedaisy-chained together. It can be used with either SPI orFrame-Sync formats. Data is shifted in on the falling edgeof SCLK. When using only one ADS1271, tie DIN low.Seethe Daisy-Chaining section for more information.


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27

DAISY-CHAINING

Multiple ADS1271s can be daisy-chained together tosimplify the serial interface connections. The DOUT of oneADS1271 is connected to the DIN of the next ADS1271.The first DOUT provides the output data and the last DINin the chain is connected to ground. A common SCLK isused for all the devices in the daisy chain. Figure 64 showsan example of a daisy chain with four ADS1271s.Figure 65 shows the timing diagram when reading back inthe SPI format. It takes 96 SCLKs to shift out all the data.

In SPI format, it is recommended to tie all theSYNC/PDWN inputs together, which forcessynchronization of all the devices. It is only necessary tomonitor the DRDY output of one device when multipledevices are configured this way.

In Frame-Sync format, all of the devices are driven tosynchronization by the FSYNC and SCLK inputs. However,to ensure synchronization to the same fCLK cycle, it isrecommended to tie all SYNC/PDWN inputs together.

The device clocks the SYNC/PDWN pin on the falling edgeof fCLK. To ensure exact synchronization, the SYNC/PDWNpin should transition on the rising edge of fCLK

Since DOUT and DIN are both shifted on the falling edgeof SCLK, the propagation delay on DOUT creates thesetup time on DIN. Minimize the skew in SCLK to avoidtiming violations. See Mode Selection section for MODEpin use when daisy-chaining.

The SPI format offers the most flexibility whendaisy-chaining because there is more freedom in settingthe SCLK frequency. The maximum number of ADS1271sthat can be daisy-chained is determined by dividing theconversion time (1/fDATA) by the time needed to read backall 24 bits (24 × 1/fSCLK).

Consider the case where:

fCLK = 27MHz

mode = High-Resolution (52,734SPS)

format = SPI

fSCLK = 27MHz

The maximum length of the daisy-chain is:

27MHz/(24 × 52,734SPS) = 21.3

Rounding down gives 21 as the maximum number ofADS1271s that can be daisy-chained.

Daisy-chaining also works in Frame-Sync format, but themaximum number of devices that can be daisy-chained isless than when using the SPI format. The ratio between theframe period and SCLK period is fixed, as shown inTable 10. Using these values, the maximum number ofdevices is two for High-Speed and Low-Power modes, andfive for High-Resolution mode.

ADS12714

DIN

SCLK

SCLK

SYNC

DOUT

ADS12713

DOUT

ADS12712

DOUT

ADS12711

DOUT

SYNC

DIN

SCLK

SYNC

DIN

SCLK

SYNC

DIN

SCLK

SYNC DRDY

Figure 64. Example of SPI-Format, Daisy-Chain Connection for Multiple ADS1271s

DRDY

SCLK 1

ADS12711Bit 23 (MSB)

ADS12711Bit 0 (LSB)

ADS12714Bit 0 (LSB)



24 25 73 96

DOUT

Figure 65. Timing Diagram for Example in Figure 64 (SPI Format)


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28

MODULATOR OUTPUT

The ADS1271 incorporates a 6th-order, single-bit,chopper-stabilized modulator followed by a multi-stagedigital filter, which yields the conversion results. The datastream output of the modulator is available directly,bypassing the internal digital filter. In this mode, anexternal digital filter implemented in an ASIC, FPGA, orsimilar device is required. To invoke the modulator output,float the FORMAT pin and tie DIN to DVDD. DOUT thenbecomes the modulator data stream output and SCLKbecomes the modulator clock output. The DRDY/FSYNCpin becomes an unused output and can be ignored. Thenormal operation of the Frame-Sync and SPI interfaces isdisabled, and the functionality of SCLK changes from aninput to an output, as shown in Figure 66. Note thatmodulator output mode is specified for the B grade deviceonly.

FORMAT

DIN Modulator Data Output

Modulator Clock Output

(Float)

DOUT

DVDD

SCLK

Figure 66. Modulator Output (B-Grade Device)

In modulator output mode, the frequency of the SCLKclock output depends on the mode selection of theADS1271. Table 12 lists the modulator clock outputfrequency versus device mode.

Table 12. Modulator Output Clock Frequencies

MODE PINMODULATOR CLOCK OUTPUT

(SCLK)

0 fCLK/4

Float fCLK/4

1 fCLK/8

Figure 67 shows the timing relationship of the modulatorclock and data outputs.

SCLK

DOUT

ModulatorClock Output

ModulatorData Output

(10ns max)

Figure 67. Modulator Output Timing


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29

APPLICATION INFORMATION

To obtain the specified performance from the ADS1271,the following layout and component guidelines should beconsidered.

1. Power Supplies: The device requires two powersupplies for operation: DVDD and AVDD. The allowedrange for DVDD is 1.65V to 3.6V, and AVDD isrestricted to 4.75V to 5.25V. Best performance isachieved when DVDD = 1.8V. For both supplies, usea 10µF tantalum capacitor, bypassed with a 0.1µFceramic capacitor, placed close to the device pins.Alternatively, a single 10µF ceramic capacitor can beused. The supplies should be relatively free of noiseand should not be shared with devices that producevoltage spikes (such as relays, LED display drivers,etc.). If a switching power supply source is used, thevoltage ripple should be low (< 2mV). The powersupplies may be sequenced in any order.

2. Ground Plane: A single ground plane connecting bothAGND and DGND pins can be used. If separate digitaland analog grounds are used, connect the groundstogether at the converter.

3. Digital Inputs: It is recommended to source terminatethe digital inputs to the device with 50Ω seriesresistors. The resistors should be placed close to thedriving end of digital source (oscillator, logic gates,DSP, etc.) This helps to reduce ringing on the digitallines, which may lead to degraded ADC performance.

4. Analog/Digital Circuits: Place analog circuitry (inputbuffer, reference) and associated tracks together,keeping them away from digital circuitry (DSP,microcontroller, logic). Avoid crossing digital tracksacross analog tracks to reduce noise coupling andcrosstalk.

5. Reference Inputs: It is recommended to use aminimum 10µF tantalum with a 0.1µF ceramiccapacitor directly across the reference inputs, VREFPand VREFN. The reference input should be driven bya low-impedance source. For best performance, thereference should have less than 3µVRMS broadbandnoise. For references with noise higher than this,external reference filtering may be necessary.

6. Analog Inputs: The analog input pins must be drivendifferentially to achieve specified performance. A truedifferential driver or transformer (AC applications) canbe used for this purpose. Route the analog inputstracks (AINP, AINN) as a pair from the buffer to theconverter using short, direct tracks and away fromdigital tracks.

A 1nF to 10nF capacitor should be used directlyacross the analog input pins, AINP and AINN. A low-kdielectric (such as COG or film type) should be used tomaintain low THD. Capacitors from each analog inputto ground should be used. They should be no largerthan 1/10 the size of the difference capacitor (typically100pF) to preserve the AC common-modeperformance.

7. Component Placement: Place the power supply,analog input, and reference input bypass capacitorsas close as possible to the device pins. This isparticularly important for the small-value ceramiccapacitors. Surface-mount components arerecommended to avoid the higher inductance ofleaded components.

Figure 68 to Figure 70 illustrate basic connections andinterfaces that can be used with the ADS1271.


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30

1.8V to 3.3V (1)

Tie toEitherDVDD

or GND

+5V

DifferentialInputs

50Ω

50Ω

50Ω

50Ω

50Ω

100Ω

+5V

+

+

50Ω10µF

10µF 0.1µF

0.47µF

0.1µF+

0.1µF

100pF

100pF

10µF

+5V

1nF100µF

0.1µF

0.1µF

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VREFP

VREFN

DGND

DVDD

CLK

SCLK

DRDY/FSYNC

DOUT

AINP

AINN

AGND

AVDD

MODE

FORMAT

SYNC/PDWN

DIN

ADS1271

27MHzClock

Source

REF3125100Ω 1kΩ

1kΩ

10nF

OPA350

(2)

NOTE: (1) 1.8V recommended. (2) Recommendedcircuit for reference noise filtering.

Figure 68. Basic Connection Drawing

+15V(1)

NOTES: (1) Bypass with 10µF and 0.1µF capacitors.(2) 2.7nF for Low−Power mode.

−15V(1)

VREF

VIN

49.9ΩAINP

OPA1632

AINN

VOCM

0.1µF

1kΩ1kΩ

1kΩ1kΩ

49.9Ω

1.5nF(2)

1.5nF(2)

Figure 69. Basic Differential Input Signal Interface

+15V(1)

NOTES: (1) Bypass with 10µF and 0.1µF capacitors.(2) 10nF for Low−Power mode.

−15V(1)

VREF

VIN

OPA1632

49.9ΩAINP

AINN

VO DIFF = 0.25 × VINVO COMM = VREF

VOCM

0.1µF

249Ω1kΩ

249Ω1kΩ

49.9Ω

5.6nF(2)

5.6nF(2)

Figure 70. Basic Single-Ended Input SignalInterface


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31

Revision History

DATE REV PAGE SECTION DESCRIPTION

10/07 F 25 SCLK (SPI Format) Added final paragraph to section.

9/07 E 20 Synchronization Added sentence to 1st paragraph regarding SYNC/PDWN left high.

2 Absolute Maximum Ratings Deleted lead temperature.

7Timing Characteristics:Frame-Sync Format

Changed tDDO parameter from “falling edge” to “rising edge.”7

Timing Characteristics:Frame-Sync Format Added “(only 256 or 512 allowed)” to Note 1.

16 Analog Inputs (AINP, AINN)Changed “0.1V” to “0.4V” in 3rd paragraph

16 Analog Inputs (AINP, AINN)Added 4th paragraph about clamp diode and series resistor requirements.

17Voltage ReferFence Inputs(VREFP, VREFN)

Changed “0.1V” to “0.4V” in 1st paragraph of right column.

7/06 D

17Voltage ReferFence Inputs(VREFP, VREFN) Added sentence about clamp diode and series resistor requirements.

7/06 DChanged text from 2nd paragraph through end of section.

20 Synchronization Changed Figure 50.20 Synchronization

Changed Figure 51.

22 Frequency Response Added “or CLK/8” to last sentence of 2nd paragraph.

26 DOUT Changed “SCLK” to “CLK” in 2nd sentence of 3rd paragraph.

29 Application InformationChanged “REFP” to “VREFP” in part 5.

29 Application InformationChanged “REFN” to “VREFN” in part 5.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

PACKAGE OPTION ADDENDUM

www.ti.com 21-May-2010

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type PackageDrawing

Pins Package Qty Eco Plan (2) Lead/Ball Finish

MSL Peak Temp (3) Samples

(Requires Login)

ADS1271IBPW ACTIVE TSSOP PW 16 90 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

ADS1271IBPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS& no Sb/Br)


ADS1271IBPWR ACTIVE TSSOP PW 16 2000 Green (RoHS& no Sb/Br)


ADS1271IBPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS& no Sb/Br)


ADS1271IPW ACTIVE TSSOP PW 16 90 Green (RoHS& no Sb/Br)


ADS1271IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS& no Sb/Br)


ADS1271IPWR ACTIVE TSSOP PW 16 2500 Green (RoHS& no Sb/Br)


ADS1271IPWRG4 ACTIVE TSSOP PW 16 2500 Green (RoHS& no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

http://www.ti.com/productcontent

PACKAGE OPTION ADDENDUM

www.ti.com 21-May-2010

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

ADS1271IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

ADS1271IPWR TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2009

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS1271IBPWR TSSOP PW 16 2000 346.0 346.0 29.0

ADS1271IPWR TSSOP PW 16 2500 346.0 346.0 29.0

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2009

Pack Materials-Page 2

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.

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