ADM-XRC Gen 3 SDK 1.7.0 for Linux Release Note V1.0

ADM-XRC Gen 3 SDK 1.7.0 for LinuxRelease Note


IntroductionThis release note accompanies the ADM-XRC Gen 3 SDK for Linux. The latest version of this SDK can be foundat:

ftp://ftp.alpha-data.com/pub/admxrcg3/linux

For support, send e-mail to [email protected]

Operating systems supportedThis release of the ADM-XRC Gen 3 SDK supports the following operating systems:

• GNU/Linux distribution with 2.6.x kernel or 3.x kernel

Hardware supportedThis release of the ADM-XRC Gen 3 SDK supports the following Alpha Data models:

• ADM-XRC-6TL

• ADM-XRC-6T1

• ADM-XRC-6T-DA1

• ADM-XRC-6TGE and ADM-XRC-6TGEL

• ADM-XRC-6T-ADV8

• ADPE-XRC-6T and ADPE-XRC-6T-L

• ADM-XRC-7K1 with 7K325T initial engineering silicon (IES) (devices marked with SCD code "ES9937")

ADM-XRC-7K1 with 7K410T initial engineering silicon (IES) (devices marked with SCD code "ES9937")

ADM-XRC-7K1 with production silicon (devices with SDC code missing)

• ADM-XRC-7V1 with 7VX485T initial engineering silicon (IES) (devices marked with SCD code "ES9937")

ADM-XRC-7V1 with general engineering silicon (GES) (devices marked with SCD code "ES")

ADM-XRC-7V1 with production silicon (devices not marked with an SDC code)

• ADM-VPX3-7V2 with general engineering silicon (GES) (devices marked with SCD code "ES")

ADM-VPX3-7V2 with production silicon (devices not marked with an SDC code)

Related productsADB3 Driver for Linux is required to run the examples in this SDK. We recommend using the latest version of thedriver that is available from:


Page 1ad-rn-0113_v1_0.pdf


mailto:[email protected]?subject=ADM-XRC%20Gen%203%20SDK%201.7.0%20for%20Linux



License AgreementThe license agreement for this software is available in the folder where the software is unpacked, in the filelicense.txt. Please contact Alpha Data if alternative licensing conditions are required.

Alpha Data reserves the right to use a different license agreement for future releases of this software.

Installation instructionsThis release of the SDK is distributed in source code form as a tarball (.tar.gz file extention). Please refer to theREADME file inside the tarball for instructions on how to configure and build the examples within.

Known issuesHardware monitoring may require 'pumping'

In PCI-E firmware revisions 0x00 - 0x01 of the ADM-XRC-6TL and ADM-XRC-6T1, the hardware monitoring logicdoes not automatically trigger conversion cycles in the LM87 system monitor chip. As a result, the valuesdisplayed by the 'monitor' and 'sysmon' utilities will always be zero. As a workaround, a script can be run in thebackground to 'pump' the LM87 interface at intervals of one second.

Linux bash script

#!/bin/bashfor ((;1;)) ; do echo 0x42D0000 | $ADMXRC3_SDK/apps/linux/dump/dump $* wd 2 0x400 4 sleep 1done

Windows batch file:

@ECHO ON:loopECHO 0x42D0000 | "%ADMXRC3_SDK%\bin\win32\x86\dump.exe" %* wd 2 0x400 4CHOICE /N /D Y /C YN /T 1 >NULGOTO loop

These scripts periodically write the value 0x42D0000 to offset 0x400 in window 2 (Model-specific registers),which commands an LM87 conversion cycle to be performed. Changing the interval to be less than one secondis not recommended as the LM87 requires approximately 0.5s to complete a conversion cycle.

NOTE: PCI-E firmware revision 0x02 and later for the ADM-XRC-6TL and ADM-XRC-6T1 do not require thisworkaround. Only a very small number of shipped ADM-XRC-6TL and ADM-XRC-6T1 cards have PCI-Efirmware revision 0x00 or 0x01.

Release historyNOTE: in the notes below, $ADMXRC3_SDK and %ADMXRC3_SDK% are equivalent, meaning "the path in thefilesystem where the SDK is installed".

Release 1.7.0

Note: Virtex-6 Models Xilinx ISE 14.7 was used to generate the Virtex-6 pre-built bitstreams (.bit files) in this release of the SDK. ISE14.2 or later is recommended for Virtex-6 models. Refer to the section "Supported Xilinx ISE Versions" in theSDK User Guide for detailed information about Xilinx ISE versions.

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Note: 7 Series Models (ISE) If Xilinx ISE is used to generate 7 Series bitstreams (.bit files), ISE 14.4 or later is recommended whentargetting production silicon devices. Refer to the section "Supported Xilinx ISE Versions" in the SDK UserGuide for detailed information about Xilinx ISE versions.

Note: 7 Series Models (Vivado) Xilinx Vivado 2014.2 was used to generate 7 Series pre-built bitstreams (.bit files) in this release of the SDK.Vivado 2014.2 or later is recommended for 7 Series models with production silicon devices. Refer to thesection "Supported Xilinx Vivado Versions" in the SDK User Guide for detailed information about Xilinx Vivadoversions.

(a) General:

(1) This release adds Vivado support.

(2) This release adds support for the ADM-PCIE-7V3.

(b) Documentation:

(1) Split the ADM-XRC Gen 3 SDK User Guide into four documents, for better manageability. The fourdocuments are: (i) Example applications, (ii) Example FPGA designs, (iii) Common HDL modulesand (iv) Introduction to ADB3 OCP.

(2) Added application notes about memory configurations that are not supported out-of-box (i.e. requirerebuild of bitstream) for the ADM-XRC-7V1, ADM-XRC-7V1 and ADM-VPX3-7V2.

(c) ADMXRC3 API header files:

(1) Added support for ADM-PCIE-7V3.

(2) Bumped version definitions to 1.7.2.

(d) Example applications:

(1) Added a Visual Studio 2012 project containing all Windows examples.

(2) The DUMP utility new has fill commands, which can fill a range of addresses with an 8-bit, 16-bit,32-bit or 64-bit value.

(3) Added a new utility, DMADUMP. This is similar to the DUMP utility except that it uses a DMA enginefor data transfer as opposed to CPU-initiated bus cycles.

(e) Example HDL designs:

(1) The clock structure in the latest version of the MPTL target interface used by the ADM-XRC-7K1 and ADM-XRC-7V1 IES models has changed. This results in the mclk_bufr frequency constraint inthe example designs for these models being relaxed from 250MHz to 125MHz.

(2) Moved the conv_ddr3_part function from uber_tb_pkg to test_uber_mem. This makes theboard-specific block test_uber_mem now independent of the Uber design.

(3) Replaced the chipscope.cpj file with the chipscope_ila.cdc file. This ChipScope ILA signal namedefinition file is model/device independent.

(4) Added new function make_defined_sl to adb3_ocp package. Used make_defined_* functions inmptl_if_bridge_wrap and mptl_if_target_wrap blocks to ensure that MPTL signals are neverdriven undefined during Full MPTL simulations. This avoids feedback of undefined values betweenthe bridge and target MPTL interfaces.

(5) Reinstated the complete MPTL bridge interface netlist for 7 Series model Full MPTL simulation.Previously one with the mptl128_gtx6_interface replaced by the VHDL file was used.



Removed the mptl128_gtx6_interface file and references to it from 7 Series Full MPTL simulationfiles.

(6) The ADM-XRC-6TGEL full MPTL simulation .do file contains references to files specific to theADM-XRC-6TGE. These have been corrected.

(7) Removed the Uber example design MPTL and PCIe clock outputs from blk_clocks on 6 Seriesmodels. Added MPTL clock as a new port at the top level of the design.

(8) Added a new model-specific package uber_model_pkg_<model>.vhd to the Uber exampledesign. This contains the model-specific clock read register offset definitions, memory interfacetypes, memory application types and component definitions which were previously inuber_pkg.vhd.

(9) Added new Uber example design types clks_measured_t and clks_memory_t to replaceclk_vec_t. Signals of these types are used by the blk_clocks, blk_ds_clk_read, blk_direct_slave and blk_mem_if blocks and .xcf constraints files.

(10) Modified packages adb3_target_inc_pkg_sim_ocp_<model>.vhd andadb3_target_inc_pkg_syn_ngc_<model>.vhd. Removed MPTL clock element of clks_mgt_in_t record and constant MGT_CLKS_VALID as they are no longer used. Split *_GPIO_WIDTH constant into *_GPIO_P_WIDTH and *_GPIO_N_WIDTH constants.

(11) Combined the 'x' and 'h' variants of ADM-XRC-7V1 and ADM-VPX3-7V2 .xcf files for all exampledesigns. These variants now use the same constraints.

(12) Planahead projects are now created in their own model/device-specific directory within the exampledesign planahead directory.

(13) Replaced block blk_mem_test with new block blk_mem_test_base and wrapper appropriate toOCP standard in use. The data width of the new block is determined by generics.

(14) Added test to Uber example design simulation scripts to determine if the ISE or Vivado environment glbl.v file should be used.

(15) Added global reset to DDR3 SDRAM banks. Reset is generated from ram global control register.

(16) Corrected definition of DDR3 SDRAM states C_DDES and C_NOOP in packageddr3_sdram_int_pkg

(17) Changed paths to 7 Series DDR3 SDRAM bank interfaces to make them more design independent.Reflected changes in design .ucf constraints and .do simulation macros.

(18) Changed handling of patches for Xilinx MIG DDR3 SDRAM Controller IP. Instead of the usermanually applying the patch after generating the MIG DDR3 SDRAM Controller files, the patchesmust now be downloaded and unzipped into specific folders in the SDK. They are then appliedautomatically when the user generates MIG DDR3 SDRAM Controller files.

(19) Corrected OPTION_M in adb3_target_tb_inc_pkg from memory part size in Mib/Gib to onboardSDRAM size in MiB/GiB

(20) Changed package ddr3_if_pkg from being common for all 7 Series models to being model-specific.

(21) Added MIG7 2.1 DDR3 SDRAM Controller support for all 7 Series models with Vivado 2014.2.

(22) Moved instantiation of MIG XADC from model-specific block blk_mem_if to new MIGversion-specific block ddr3_if_idc for 7 Series models.

(23) Added ability to use TAB characters in DDR3 SDRAM simulation initialisation files.

(24) Removed second redundant CONFIG INTERNAL_VREF_BANK32=0.750 fromuber-admxrc7k1.ucf

(25) Removed unnecessary BUFGs from elements of clks_measured output from blk_clocks in 7Series Uber example design. Added new IDELAYCTRL clock pll_idc_clk to elements of



clks_memory output from blk_clocks in 7 Series Uber example design.

(26) Added Vivado project support for all 7 Series models including ADM-VPX3-7V2 model 7V2000T device. Projects must be built prior to use.

(27) Added support for new model: ADM-PCIE-7V3. This model is supported using Xilinx Vivado only.

(28) Added Modelsim simulation support for ADM-VPX3-7V2 model 7V2000T device.

(29) Added support for DDR3 SDRAM dual rank parts/modules for Virtex-7 based models. Duringsimulation a model instance for each rank of each part/module is instantiated. Bitfiles built withdesigns for use with dual rank parts/modules are not compatible with single rank parts/modules.

(30) Added incrementing tag values to Uber example design test_uber_ds. Added TAG value to OCPwrite and read comments in this block.

(31) Added new block date_time to Uber example design blk_ds_info. This produces date and timevectors which have their INIT property set by the today_pkg. The INIT property may be overriddenusing TCL commands during the Vivado build process.

(32) Added new OPTION_Y constant to package adb3_target_inc_pkg, in order to define the targetFPGA speed grade.

(33) Added retiming logic to the status registers from the memory interface block, in order to ease timing.

(34) The OCP profile with 128-bit data, defined in adb3_ocp_pkg.vhd, is now known as "OCP Full".

(35) Added new OCP profile: "OCP Wide" profile, with 256-bit wide data, in packageadb3_ocp_w_pkg.vhd.

(36) Added "OCP Wide" versions of certain OCP components, with 256-bit wide data, in packageadb3_ocp_w_pkg.vhd.

(37) Added new OCP profile: "OCP Quad" profile, with 512-bit wide data, in packageadb3_ocp_w_pkg.vhd.

(38) Added "OCP Quad" versions of certain OCP components, with 512-bit wide data, in packageadb3_ocp_w_pkg.vhd.

(39) Added non-blocking OCP profile (width) conversion modules for converting between OCP Full, OCPWide and OCP Quad profiles.

Known release-specific issues:

(f) Example HDL designs:

(1) The Uber example design uses the Xilinx MIG DDR3 SDRAM interface:

• For models with Virtex-6 devices, MIG6 v3.92 is used, which requires ISE 14.2 or later.

• For models with 7 Series initial engineering silicon (IES) fitted, MIG7 v1.4 is used with ISE13.4 or later.

• For models with 7 Series general engineering silicon (GES) or 7 Series production silicon,MIG7 v1.8 is used with ISE 14.4 or later, or MIG7 v2.1 is used with Vivado 2014.2 or later.

(2) Prior to generating the MIG7 1.4 DDR3 SDRAM interface using ISE 13.4 or later, a Xilinx patchmust be downloaded. See http://www.xilinx.com/support/answers/45653.htm .

(3) Prior to generating the MIG7 1.8 DDR3 SDRAM interface using ISE 14.4 or later, a Xilinx patchmust be downloaded. See http://www.xilinx.com/support/answers/53420.htm .

(4) Use of Modelsim libraries compiled by ISE 14.x "compxlib" utility in a "full MPTL" simulation ofmodel ADM-XRC-6TL appears to be problematic. Use of ISE 14.x ISIM in "full MPTL" simulation ofmodel ADM-XRC-6TL appears to be problematic.


http://www.xilinx.com/support/answers/45653.htm



(5) Simulation of designs using MIG7 v1.4 DDR3 SDRAM interface in ISE 13.4 ISIM does not work.This appears to be a problem specific to the combination of ISE 13.4 ISIM and the MIG7 v1.4 DDR3SDDRAM interface.

(6) "Full MPTL" simulation of designs in PlanAhead ISIM is very slow compared to the equivalentModelSim simulation. This behaviour appears to be inherent to ISIM.

(7) "Full MPTL" simulation of 7 Series models is not currently possible using Vivado generatedsimulation libraries. This is because components in the 6-series bridge netlists are not supported inVivado generated simulation libraries.

(8) "Full MPTL" simulation of designs in Vivado XSIM is not currently possible. This is becausecomponents in the 6-series bridge netlists are not supported in 7 Series simulation libraries.

(9) Simulation of FPGA example designs using Vivado XSIM produces mixed results. "OCP Only"simulation of designs Simple and ITest work correctly. Simulation of designs SimpleDMA and Uber do not run with Vivado 2014.2.

(10) Generation of chipscope cores using ISE 14.4 may not work. The error "Unknown" Line 0: Savefailed due to mkdir failure may be produced. See http://www.xilinx.com/support/answers/36547.htm

(11) This release of the SDK is partially compatible with Vivado 2014.3. Vivado projects for the ITest,Simple and SimpleDMA example FPGA designs can be successfully generated and built withVivado 2014.3, but Uber cannot. The Uber example FPGA design depends upon MIG7 v2.1, whichis not supported by Vivado 2014.3. Vivado 2014.3 support will be added in the next release of thisSDK.

(12) Connecting to the JTAG chain of the ADM-XRC-7K1, ADM-XRC-7V1 or ADM-VPX3-7V2 usingVivado 2014.3 Hardware Manager may corrupt the state of the Virtex-6 PCIe Bridge FPGA, causingit to stop responding to PCI Express packets. This issue is currently under investigation. It isrecommended that Vivado 2014.2 Hardware Manager is used instead for debugging.

Release 1.6.1


Note: 7 Series Models Xilinx ISE 14.5 was used to generate the 7 Series pre-built bitstreams (.bit files) in this release of the SDK. ISE14.4 or later is recommended for 7 Series models with production silicon devices. Refer to the section"Supported Xilinx ISE Versions" in the SDK User Guide for detailed information about Xilinx ISE versions.

1 Example HDL designs:

(a) Corrected the sensitivity list of the 'drive_mig' process in adb3_ocp_ocp2ddr3_nb.vhd so that a fewlatches are no longer inferred due to signals missing from the sensitivity list.

(b) Corrected the pipelining of the 'ds_q' signal in blk_ds_io_test_*.vhd (for all supported models), toeliminate an error seen in a message of the form "Test ... IO completed: FAILED" when simulatingthe UBER design for the ADM-VPX-7V2 using certain .do files supplied in this SDK.

(c) The Modelsim .do files for simulating the UBER design in Modelsim, for a Virtex-7 or Kintex-7 modelwith the lightweight behavioural (LWB) DDR3 SDRAM model, have been modified so that a Verilogsimulation license is no longer required.







Release 1.6.0


Note: 7 Series Models Xilinx ISE 14.5 was used to generate the 7 Series pre-built bitstreams (.bit files) in this release of the SDK. ISE14.4 or later is recommended for 7 Series models with production silicon devices. Refer to the section"Supported Xilinx ISE Versions" in the SDK User Guide for detailed information about Xilinx ISE versions.

1 General:

(a) Added support for general engineering silicon devices (SCD code "ES") and production devices (noSCD code) for models ADM-XRC-7K1 and ADM-XRC-7V1. 7 Series initial engineering silicon (SCDcode "ES9937") support for these models uses files with 'ies' in the path and/or filename.

(b) Added support for new models: ADM-XRC-6TGEL and ADM-VPX3-7V2.

2 Documentation:

(a) ADMXRC3 API Specification updated to 1.7.0, detailing some new definitions and API functions.

(b) ADMXRC3 API Hardware Addendum updated to include information about new models.

3 ADMXRC3 API header files:

(a) The ADMXRC3 API header file <admxrc3.h> now conforms to ADMXRC3 API Specification 1.7.0.Additions include support for the new models ADM-XRC-6TGEL and ADM-VPX3-7V2 and new APIfunctions ADMXRC3_GetDeviceStatus & ADMXRC3_ClearDeviceErrors. Refer to "ADMXRC3API 1.7.0 Specification" for further details.

4 ADMXRC3 DLL import libraries:

(a) The Windows DLL import libraries in $ADMXRC3_SDK/lib/win32/ and$ADMXRC3_SDK/lib/win32gnu/ have been updated to include the new functions defined by <admxrc3.h>.

5 Example applications:

(a) Example VxWorks applications should now compile without portability warnings and run correctly,when built with the 64-bit compilers provided in VxWorks 6.9 or later.

(b) Added support for new models to example applications: ADM-XRC-6TGEL and ADM-VPX3-7V2.

(c) Certain example applications and utilities now check for device errors using theADMXRC3_GetDeviceStatus function in ADMXRC3 API 1.7.0 and later, and attempt to cleardevice errors if possible. If the driver in use does not support ADMXRC3_GetDeviceStatus, thischeck is not performed.

(d) The build system for the example VxWorks applications has been replaced. Configuration files areno longer required, and the makefile infrastructure provided by VxWorks is used instead. CPU,toolchain etc. are now specified on the make command line.

(e) In $ADMXRC3_SDK/apps/src/common/args.c (used by example applications and utilities forWindows & Linux), fixed a bug in stripTrailingSpace function that may corrupt the heap or thestack (depending on what its parameter points to) on some architectures.

(f) sysmon utility:



• The trace key is now a tool window that can be toggled on and off, and permits traces to beindividually shown and hidden on the corresponding scope.

• Added bi-colour traces, to allow for more sensors in a given reconfigurable computing device.This means that on models with more than 13 sensors, sensors 13 and up are no longerindistinguishable from each other due to being coloured white.

• The sysmon utility can now be built in Linux distributions that include gtkmm-3.0, and willprefer gtkmm-3.0 if built in a system that has both installed.

• A new tab showing device status, as returned by the ADMXRC3_GetDeviceStatus, hasbeen added. If the driver in use does not support ADMXRC3_GetDeviceStatus, this tab isnot visible. Device errors can be manually cleared via this tab, subject to the user runningsysmon having sufficient privileges to successfully call the ADMXRC3_ClearDeviceErrors API function.


(a) Value of rtt_nom generic used by the MIG DDR3 SDRAM interface for the ADM-XRC-7K1 wasincorrect in previous releases. The value is now generated by function conv_rtt_nom_option in thepackage $ADMXRC3_SDK/hdl/vhdl/common/ddr3_sdram_if/ddr3_if_pkg_k7.vhd and will be"40" for DDR3-1600 (i.e. 800 MHz clock to physical devices).

(b) Corrected value of SIM generic in component ddr3_if_bank in ddr3_if_pkg from "TRUE" to"FALSE".

(c) Implemented some changes in TCL scripts such as makeppr.tcl that generate PlanAhead projectsfor the example FPGA designs, for compatibility with ISE 14.3, 14.4 and 14.5.

(d) Corrected LOCs in reference MPTL constraints fragmenthdl/constraints/mptl/admxrc7v1/mptl-admxrc7v1.ucf.

(e) Updated ADB3 PCI-E to OCP Bridge cores for the ADM-XRC-6T-ADV8 inhdl/vhdl/common/adb3_target/admxrc6tadv8/adb3_target/admxrc6tadv8_pcie_x8_*.ngc.These cores feature PCI Express Gen 1 by 8 lanes with 1 or 4 DMA engines. The appropriate core(.ngc file) is chosen by the pcie_if_target_wrap_6tadv8.vhd wrapper according to the constantsPCIE_SER_WIDTH and DMA_CHANNELS in the packagehdl/vhdl/common/adb3_target/admxrc6tadv8/adb3_target_inc_pkg_*_6tadv8_pcie.vhd.

(f) Corrected the value of PCIEREFCLK_* constants from 250MHz to 100MHz inadb3_target_tb_inc_pkg testbench packages. This applies to the models ADM-XRC-7K1 andADM-XRC-7V1.

(g) Updated the MPTL cores, $ADMXRC3_SDK/hdl/vhdl/common/adb3_target/<model>/adb3_target/mptl128_interface_target_*.ngc, for the following models: ADM-XRC-6T1,ADM-XRC-6TGE, ADM-XRC-6T-DA1, ADPE-XRC-6T, ADPE-XRC-6T-L, ADM-XRC-7K1 andADM-XRC-7V1. These generally improve the robustness of the MPTL link between Bridge andTarget FPGAs.

(h) MPTL cores are now provided in $ADMXRC3_SDK/hdl/vhdl/common/adb3_target/<model>/adb3_target/mptl128_interface_target_*.ngc, for the following models: ADM-XRC-6TGEL andADM-VPX3-7V2

(i) Increased the frequency of the Uber example design's pll_pri_clk on model ADM-XRC-6T-ADV8 from 100MHz to 200MHz, to bring it in line with other models.

(j) Changed the IOB attribute on the Uber example design gpio_inout and finti_l signals from "TRUE"to "FORCE". An error will now be generated if Xilinx ISE is unable to map the flip-flops that drivethese signals into IOBs.

(k) Changed the IOB attribute on the ITest example design finti_l signal from "TRUE" to "FORCE". Anerror will now be generated if Xilinx ISE is unable to map the flip-flop(s) that drive this signal into an



IOB.

(l) Removed the Uber example design MPTL and PCIe clock outputs from blk_clocks on 7 Seriesmodels. Added MPTL clock as a new port at the top level of the design.

(m) The Uber example design now supports DDR3 SDRAM parts up to 4 Gibit with a single bitstream(for a given <model;>-<device> combination) on all models except the ADM-XRC-7K1.

(n) Changed Uber example design so that unused DDR3 SDRAM address bits are always driven low.Width of physical DDR3 SDRAM address bus is defined by new DDR3_BANK_ROW_WIDTH_MAX constant in adb3_target_inc_pkg package. Width of used DDR3 SDRAM address bus is definedby DDR3_BANK_ROW_WIDTH constant in adb3_target_inc_pkg package.

(o) Added checks to ensure that the version of Xilinx ISE that is in use is compatible with the FPGAdesigns in this version of the SDK. Refer to the section "Supported Xilinx ISE Versions" in theADM-XRC Gen 3 SDK User Guide for detailed information about Xilinx ISE versions supported bythis version of the SDK. ISE version checking is performed by the check_ise_ver.tcl script at thefollowing points:

• When building an FPGA design using the provided makefile build system.

• When generating PlanAhead projects for an FPGA design using the provided genppr.tcl script.

(p) Added checks to ensure that any required patches have been applied to generated MIG DDR3interface HDL files. Checking is performed by the TCL scripts check_ddr3_if_mig*.tcl at thefollowing points:

• When building an FPGA design using the provided makefile build system.

• When generating PlanAhead projects for an FPGA design using the provided genppr.tcl script.

• When simulating an FPGA design using the provided ModelSim .do scripts.

(q) Added scripts and associated files for generating MIG7 v1.8 DDR3 SDRAM interface (for 7 Seriesproduction silicon) for use on 7 Series Gen 3 reconfigurable computing hardware. Requires ISE14.4 or later.

(r) Added scripts and associated files for generating MIG6 v3.92 DDR3 SDRAM interface (for Virtex-6production silicon) for use on Virtex 6 Gen 3 reconfigurable computing hardware. Requires ISE 14.2or later.

(s) The memory bank test block,$ADMXRC3_SDK/hdl/vhdl/common/mem_apps/blk_mem_test.vhd now performs a couple ofextra phases designed to maximise (i) number of simultaneous 1->0 & 0->1 transitions on physicaldata pins and (ii) number of simultaneous 1->0 and 0->1 transitions on OCP data bus.

(t) Reimplemented the logic that drives the MIG DDR3 interface in$ADMXRC3_SDK/hdl/vhdl/common/adb3_ocp/adb3_ocp_ocp2ddr3_nb*.vhd to improve easeof timing closure.



(a) The Uber example design uses the Xilinx MIG DDR3 SDRAM interface:

• For models with Virtex-6 devices, MIG6 v3.92 is used, which requires ISE 14.2 or later.

• For models with 7 Seres initial engineering silicon (IES) fitted, MIG7 v1.4 is used, whichrequires 13.4 or later.

• For models with 7 Series general engineering silicon (GES) or 7 Series production silicon,



MIG7 v1.8 is used, which requires ISE 14.4 or later.

(b) After generating the MIG7 1.4 DDR3 SDRAM interface using ISE 13.4 or later, a Xilinx patch mustbe applied. See http://www.xilinx.com/support/answers/45653.htm .

(c) After generating the MIG7 1.8 DDR3 SDRAM interface using ISE 14.4 or later, a Xilinx patch mustbe applied. See http://www.xilinx.com/support/answers/53420.htm .

(d) Use of Modelsim libraries compiled by ISE 14.x "compxlib" utility in a "full MPTL" simulation ofmodel ADM-XRC-6TL appears to be problematic. Use of ISE 14.x ISIM in "full MPTL" simulation ofmodel ADM-XRC-6TL appears to be problematic.

(e) Simulation of designs using MIG7 v1.4 DDR3 SDRAM interface in ISE 13.4 ISIM does not work.This appears to be a problem specific to the combination of ISE 13.4 ISIM and the MIG7 v1.4 DDR3SDDRAM interface.

(f) "Full MPTL" simulation of designs in ISE ISIM is very slow compared to the equivalent ModelSimsimulation. This behaviour appears to be inherent to ISIM.

Release 1.5.0

Note: 6 Series Models The Xilinx ISE 13.4 toolset was used to generate the Virtex-6 pre-built bitstreams (.bit files) in this release ofthe SDK. ISE 13.2 or later is strongly recommended for 6-series models due to corrections to BRAM timing(see http://www.xilinx.com/support/answers/42444.htm), and improvements in BRAM placement. Refer to thesection "Supported Xilinx ISE Versions" in the SDK User Guide for detailed information about Xilinx ISEversions.

Note: 7 Series Models The Xilinx ISE 13.4 toolset, with Initial Engineering Silicon patches, was used to generate the 7 series(Virtex-7 and Kintex-7) pre-built bitstreams (.bit files) in this release of the SDK. Refer to the section"Supported Xilinx ISE Versions" in the SDK User Guide for detailed information about Xilinx ISE versions.

Corrections:

1 Documentation:

(a) Documented the missing flag ADMXRC3_CONFIGURE_NOCHECK in the ADMXRC3 APISpecification document; this flag has always been present in the ADMXRC3 API but was wronglyomitted from documentation.

(b) Corrected an error in the description of ADMXRC3_NONBLOCK_IDLE in the ADMXRC3_STATUS type in the ADMXRC3 API Specification document.


(a) Corrected an incorrect unit in Linux version of sysmon utility, which showed "kiByte" as the unit forthe "Physical Size" attribute of a memory bank. The corrected unit is "kiWord".

(b) Corrected a build failure with the Linux version of sysmon in some Linux distributions, where linkingfails with a large number of "unknown symbol" errors. This has been corrected by moving $(LIBS) inthe linker rule in apps/linux/sysmon/Makefile.build to the end of the rule (certain recent GNUtoolchains need libraries listed after object modules).

(c) Corrected various bugs in the display of device information in the Windows version of the sysmon utility.

(d) Corrected a race condition when setting the PAGE register in the memtesth example application,where on some platforms, a CPU-initiated write to the PAGE register could be overtaken by





accesses to the DDR3 SDRAM. The PAGE register is now read back immediately after it is written,which guarantees that the CPU's write to the PAGE register has been completed.

(e) Fixed a bug in the sampleParseCommandLine function in $ADMXRC3_SDK/apps/common/args.cwhere some members of the pArguments structure were not initialized in cases where the functionreturned early (e.g. when the user passes the '-help' option to a program); the matching call tosampleCleanupCommandLine might then have crashed the program. ThesampleParseCommandLine function now initializes members of the pArguments structure as earlyas possible to avoid this problem.


(a) Changed the Uber simulation clock frequency measurement sample period from 1us to 4us in filesblk_ds_clk_read_*.vhd to improve simulation accuracy.

(b) The DDR3 SDRAM simulation model has been modified so that it does not accept commands withundefined addresses. An error will now be generated with these commands.

(c) Fixed potential division by zero initialisation problem in test_board_clocks_*.vhd.

Enhancements:

4 General:

(a) Added support for the following new models: ADM-XRC-6T-DA1, ADPE-XRC-6T(-L),ADM-XRC-7K1 & ADM-XRC-7V1. HDL support for the latter two models is for Initial EngineeringSilicon devices (SCD code "ES9937") in this release of the SDK.

(b) Added scripts that generate PlanAhead project files for the example FPGA designs.

(c) A new ddr3_sdram_if directory has been added to hdl\vhdl\common\. It contains the scripts togenerate the MIG DDR3 interface compatible with the ISE version used to build the SDK bitfiles.Use of the mem_if\ddr3_sdram directory is deprecated as the MIG DDR3 interface version it uses(MIG v3.6) is not compatible with ISE versions after 13.2.

(d) Added use of parameters in Modelsim macro files. The first parameter selects the MIG version, andthe second selects the run time. If no parameters are present, then the MIG version and run timeare both selected within the macro file.

5 Documentation:

(a) Documented the new "Common Buffer" ADMXRC3 API functions (ADMXRC3_GetCommonBuffer etc.) in the ADMXRC3 API Specification.

(b) Updated the ADMXRC3 API Hardware Addendum with information about the new models supportedin this release of the SDK.

(c) Updated the SDK User Guide to describe enhancements to example HDL designs.

(d) Completed documentation missing from the 'Common HDL Components' section in the SDK UserGuide.

(e) Updated the SDK User Guide to describe the new example HDL designs: ITest and SimpleDMA.

(f) Updated the SDK User Guide to describe the new ADB3 OCP profiles.


(a) Added new utilities: bitstrip and loader.

(b) Added new example application: simpledma.

(c) Added a solution and project files for Microsoft Visual Studio 2010 for the example Windowsapplications and utilities, in apps/win32vs2010. The Microsoft Visual Studio 2008 solution andprojects are now in apps/win32vs2008.



(d) Added the BYSERIAL flag to most VxWorks example applications, allowing them to open a deviceby serial number.

(e) Modified the itest example to work (by default) with the new ITest FPGA design bitstream instead ofUber. A command-line option can make it revert to using the UBER FPGA design bitstream.

(f) Improved the behaviour of the sampleOpenCard function in the common command-line argumentparsing framework used by the example applications and utilities. When opening a card by its serialnumber, it now enumerates cards in passive mode (which should always succeed), and ifnecessary, re-opens the card (if found) in active mode. This avoids misleading "device not found"errors being returned when attempting to open a card in active mode by a process that lacksAdministrator privileges; in such cases an "access denied" error is now returned as expected.

(g) The memtesth example application (using the UBER example FPGA design) now displays betterinformation about the failure when memory bank training fails for a particular bank.


(a) Added the "Common Buffer" API functions (ADMXRC3_GetCommonBuffer etc.).

(b) Added definitions for the new models to the ADMXRC3_MODEL_TYPE enumerated type:ADM-XRC-6T-DA1, ADPE-XRC-6T, ADPE-XRC-6T-L, ADM-XRC-7K1 & ADM-XRC-7V1.


(a) Added a new example FPGA design called ITest, which demonstrates handling of interruptsgenerated within a target FPGA.

(b) Added a new example FPGA design called SimpleDMA, which demonstrates how to interfacedirectly (as an OCP slave) to an OCP port, both for the Direct Slave OCP port and for DMA channelOCP ports.

(c) Two new ADB3 OCP profiles have been added to adb3_ocp_pkg: OCP Lite for register access;and OCP Stream for streaming data. The original profile will be refered to as OCP Full.

(d) The adb3_ocp_ocp2ddr3_nb and adb3_ocp_cross_clk_dom_nb blocks have been re-writtenusing custom FIFOs. This simplifies the design and reduces resource usage. Theadb3_ocp_split_b and adb3_ocp_mux_b blocks have also been re-written.

(e) New block adb3_ocp_reg32_b using OCP full profile has been added.

(f) New block adb3_ocp_full2lite using OCP full/Lite profiles has been added.

(g) New blocks adb3_ocp_l_split, adb3_ocp_l_spliteq using OCP Lite profile have been added.

(h) New block adb3_ocp_l_ictrl using OCP Lite profile have been added.

(i) New block adb3_ocp_ocp2ddr3_nb for use with 7 series cards.

(j) The fifo_pkg and dpmem_pkg packages are no longer required and have been removed.

(k) Removed the dependency of adb3_target_tb_inc_pkg_* on ddr3_sdram_pkg.

(l) The adb3_target_types_pkg and adb3_target_inc_pkg_sim_mptl_*.vhd packages are no longerrequired and have been removed.

(m) Moved component definitions from adb3_target_pkg to adb3_target_inc_pkg. Moved functiondefinitions from adb3_target_pkg to adb3_ocp_pkg. Removed adb3_target_pkg.

(n) Moved component definitions from adb3_target_tb_pkg to adb3_target_tb_inc_pkg. Removedadb3_target_tb_pkg.

(o) Added a new high speed 'light weight behavioural' simulation version of MIG DDR3 SDRAMinterface/testbench DDR3 models for simulation. Light weight behavioural or full MIG simulation isselected in the modelsim .do file for the model in use.



(p) The pon_rst (power-on reset) signal in the simple example design now generates ocp_ready tothe target MPTL interface instance. This applies a pulse at configuration time to target MPTLinterface, to ensure that it locks reliably.

(q) Reset of most of the logic in example designs with an MPTL interface is now generated from thenew mptl_ready output from the target MPTL interface.

(r) Reset of most of the logic in example designs with a PCI Express interface now also includes thepcie_rst_l signal, so that either power-on reset or PCI Express reset can reset the design.

(s) Constants which have different values during simulation and synthesis are now generated usingcompiler directives/generics rather than the TARGET_USE constant. This has been removed. Thisapplies to the uber blocks blk_ds_clk_read and ddr3_if_bank.

(t) Improved configuration time for ADM-XRC-6T-ADV8 bitstreams by specifying optimal BITGEN options: -g persist:no -g StartupClk:cclk -g BPI_1st_read_cycle:4 -g BPI_page_size:8 -gConfigRate:26. Note that if using PlanAhead 13.x to generate bitstreams for theADM-XRC-6T-ADV8, user action is required, as explained in the section "Extra BITGEN options inPlanAhead 13.x for the ADM-XRC-6T-ADV8" in the SDK User Guide.

(u) PCI-E gen 1 x8 cores for the ADM-XRC-6T-ADV8 with 1 and 4 DMA engines are now provided inhdl/vhdl/common/adb3_target/admxrc6tadv8/pcie_target/, and the packageshdl/vhdl/common/adb3_target/admxrc6tadv8/adb3_target_inc_pkg_*_6tadv8_pcie.vhd now havevalues of 4 for DMA_CHANNELS and 8 for PCIE_SER_WIDTH. The synthesizable filehdl/vhdl/common/adb3_target/admxrc6tadv8/pcie_target/pcie_if_target_wrap_6tadv8.vhd has beenupdated to reflect the larger number of choices for the PCI-E core that is instantiated based on theaforementioned constants.

(v) Previous SDKs supported MIG DDR3 SDRAM interface version 3.6. This version is supported untilXilinx ISE 13.2.

This SDK adds support for MIG6 DDR3 SDRAM interface version 3.9 for Xilinx 6 series models.This version is supported from Xilinx ISE 13.3.

This SDK adds support for MIG7 DDR3 SDRAM interface version 1.4 for Xilinx 7 series models.This version is supported by Xilinx ISE 13.4.



(a) The Uber example design for the larger devices in the Virtex-6 FPGA families sometimes fails tomeet timing constraints when placed and routed using Xilinx ISE versions prior to 13.2. ISE version13.2 greatly improves BRAM placement which enables these designs to meet timing. This versionor later is also strongly recommended due to corrections to BRAM timing (see http://www.xilinx.com/support/answers/42444.htm).

(b) The Uber example design in this release of the SDK uses Xilinx MIG DDR3 SDRAM interfaceversions MIG6 3.9 (6 series) and MIG7 1.4 (7 series). MIG6 3.9 is supported by ISE13.3 onwards.MIG7 1.4 is supported by ISE13.4 onwards. Previous releases of the SDK used MIG 3.6 (6 series).Xilinx supported this version of MIG up to ISE13.2.

(c) After generation of the MIG7 1.4 DDR3 SDRAM interface using ISE13.4, a Xilinx patch is requiredto be applied. See http://www.xilinx.com/support/answers/45653.htm.

(d) Use of Modelsim libraries generated by ISE14.x in simulation of model ADM-XRC-6TL appears tobe problematic.

(e) ISIM simulation of designs using MIG7 v1.4 DDR3 SDRAM interface (Uber) on 7 series modelsappears to be problematic.

(f) "Full MPTL" ISIM simulation of designs is very slow compared to the equivalent ModelSimsimulation.



Release 1.4.0

Note: The Xilinx ISE 13.2 toolset was used to generate the prebuilt bitstreams (.bit files) in this release of the SDK.ISE 13.2 or later is therefore strongly recommended due to corrections to BRAM timing (see http://www.xilinx.com/support/answers/42444.htm), and improvements in BRAM placement.

The example FPGA designs will not build successfully with any Xilinx ISE version earlier than 12.4 due tochanges in net name formatting introduced with ISE 12.4.

Corrections:


(a) The "configure" script for the Linux example applications no longer incorrectly says that "install" is avalid target when it finishes.

(b) Fixed missing endian conversions in "memtesth" example.

(c) Fixed "simple" example displaying endian-swapped version of value written to register, whenexecuted on a big-endian machine.

(d) Changed how the error value for sensors is displayed by the "info" utility so that small errors don'tshow as 0.0.


(a) Fixed a bug in the adb3_ocp_ocp2ddr3 component present in the SDK 1.3.1 release. Please usethe updated version of this component (0.5, 14 Jun 2011) included in this version of the SDK. Bugrelates to acceptance of slave OCP commands when slave command FIFO becomes full.

(b) Fixed a bug in the ddr3_sdram component present in the SDK 1.3.1 release. Please use theupdated version of this component (0.3, 10 Jun 2011) included in this version of the SDK. Bugrelates to correct selection of tFAW and tRRD values depending on the page size of the DDR3SDRAM part in use.

(c) Corrected MIG DDR3 SDRAM custom part MT41J64M16XX-187E timing parameters. Should usetfaw="50", trrd="10" for 2KiB page size. Corrected MIG3.6 project files timing parameters totfaw="50", trrd="10" for 2KiB page size.

(d) Corrected uber example design GPIO IOSTANDARD constraint. Changed

NET "gpio_inout_xrm_gpio_xrm_da_cc_n" IOSTANDARD = "LVCMOS25"; to

NET "gpio_inout_xrm_gpio_xrm_da_cc_p" IOSTANDARD = "LVCMOS25";

(e) Fixed a bug in the Uber adb3_ocp_sim_read testbench procedure where valid OCP response datawas accepted before response accept went high. This only occurred if a valid response wasavailable before a read command had been issued. This procedure was in the adb3_target_tb_pkg SDK 1.3.1 package but is now in the adb3_ocp_tb_pkg package.

(f) Corrected DDR3 part number from MT47J128M16_187E to MT41J128M16_187E in packageddr3_sdram_pkg.

Enhancements:

3 General:

(a) Added support for models ADM-XRC-6TGE and ADM-XRC-6TADV8.

4 Documentation:



(a) Updated documentation to describe enhancements to example HDL designs.

(b) Expanded documentation which describes the ADB3 OCP protocol.

(c) Expanded documentation which describes the common components.

(d) Documented the improvements and new logging features of the "sysmon" utility.


(a) The example applications now support the ADM-XRC-6TGE and ADM-XRC-6T-ADV8 in general.

(b) The "sysmon" utility now has time (X-axis) labels.

(c) The "sysmon" utility now permits logging of data to a file over arbitrary periods.


(a) Changed the adb3_ocp_ocp2ddr3 component. Modified the ordering of the address presented tothe MIG DDR3 interface. This allows a single bitfile to be compatible with different size DDR3SDRAM parts, for example 1Gib and 2Gib parts.

(b) Added DDR3 model support for parts MT41J256M16_187E, MT41J128M16_15E,MT41J256M16_15E to package ddr3_sdram_pkg.

(c) Added dma_abort input to mptl_if_target_wrap component and instantiations in simple and uber top levels.

(d) Added mptl_online output to mptl_if_bridge_wrap component and instantiations in test_simple and test_uber testbenches.

(e) Changed all 6TL/6T1 build scripts and .prj/.scr files to allow each board/device combination to havetheir own build directory build. The edif and output directories are no longer present.

(f) Changed uber blocks blk_clks, blk_ds_clk_read, blk_ds_io_test, blk_mem_if and ddr3_if_bank to be board-specific. Changed uber testbench package uber_tb_pkg to be board specific.

(g) Added board-specific testbench package adb3_target_tb_inc_pkg_*.

(h) Added board-specific test_board_clks block to simple and uber testbenches. This replaces theindividual clock generation/test functions in the previous version of the testbenches.

(i) Changed the gen_mem_if and gen_chipscope scripts so that they use the 6vlx240t device bydefault. The device is no longer required to be entered as part of the command line.

(j) Changed the Direct Slave OCP channel split hierarchy. BRAM and on-board RAM address split nowoccurs in the pll_pri_clk domain.

(k) Added new adb3_ocp_simple_bus_if_nb ADB3 OCP component. Used to replace the BRAMinterface in uber blk_bram.

(l) Re-structured adb3_ocp_retime_nb component.

(m) Re-structured MPTL interface components. Moved them from mptl directory to board specificdirectories in adb3_target. Removed mptl directory.

(n) Re-structured mem_if directory. Changed gen_mem_if .bat/.bash scripts into a single .tcl script withboard type as an input parameter. Changed from single rtl directory to board specific directoriescontaining rtl. For example mem_if/ddr3_sdram/admxrc6t1/rtl/mig_v3_6/ for the ADM-XRC-6T1.

(o) Re-structured chipscope directory. Changed gen_chipscope .bat/.bash scripts into a single .tclscript with board type as an input parameter. Changed from single cgp directory to board specificdirectories containing ngc. For example chipscope/admxrc6t1/ngc/ for the ADM-XRC-6T1.

(p) Added simulation check for correct compilation of MIG DDR3 vhdl files in uber .do files. Addedsynthesis check for presence of MIG DDR3 vhdl files in uber makefile. Added message prompting



user to generate cores if they are not present.

(q) Added power-on reset to top level of simple example design.

(r) Changed name of interrupt signal output from blk_ds_int_test from interrupt_l to finti_l. Addednew active high interrupt output interrupt.

(s) Moved all simulation procedures from package adb3_target_tb_pkg to new packageadb3_ocp_tb_pkg.

(t) Added new SDK version register to blk_ds_info and new constant SDK_VERSION totoday_pkg_*.vhd.

(u) Changed name of packages adb3_target_inc_*_pkg.vhd to adb3_target_inc_pkg_*.vhd.

(v) Moved memory model instantiation from the testbench to a new board specific blocktest_uber_mem_*.vhd.



(a) The Uber example design for the larger devices in the Virtex-6 FPGA families sometimes fails tomeet timing constraints when placed and routed using Xilinx ISE versions prior to 13.2. ISE version13.2 greatly improves BRAM placement which enables these designs to meet timing. This versionor later is also strongly recommended due to corrections to BRAM timing (see http://www.xilinx.com/support/answers/42444.htm).

Release 1.3.1

Note: The Xilinx ISE 12.4 toolset was used to generate the prebuilt bitstreams (.bit files) in this release of the SDK.This release supersedes beta release 1.3.0b1.

New behavior:

1 Bi-architecture build of the example applications is no longer performed by default, as most 64-bit Linuxdistributions do not install (by default) the necessary compatibility packages for building 32-bit binaries. Tobuild both 32-bit and 64-bit binaries for the API libraries, specify '-biarch yes' when running the 'configure'script.

Corrections:


(a) Fixed a bug in remaining() function used in DUMP and VPD utilities; caused assertion traps inWindows debug builds.

(b) Fixed the behavior of the "Device" Combo Box in the Windows version of the SYSMON utility sothat when devices are added, removed, disabled or enabled (e.g. using Device Manager), itcorrectly reflects the changes.

(c) Command line application framework in $ADMXRC3_SDK/apps/src/common/:

• Fixed a problem where applications built for Linux that expect UNIX pathnames can have theleading / in a path interpreted as the start of an option rather than as a path.


(a) Fixed a bug in the adb3_ocp_ocp2ddr3 component present in the SDK beta release (1.3.0b1).Please use the updated version of this component (0.3, 05 May 2011) included in this version of theSDK.



Enhancements:

4 General:

(a) Added support for DDR3 memory on models ADM-XRC-6TL and ADM-XRC-6T1.

5 Documentation:

(a) The User Guide now contains outlines of the components that are the common HDL modules in$ADMXRC3_SDK/hdl/vhdl/common/. Full details of the operation and usage of these components isscheduled for the next release of the SDK.


(a) The FLASH utility now has the "info" command, which displays information about the Flash memoryand then exits. Also added comments to source code that detail the Flash address map onsupported models.

(b) The DUMP utility now displays addresses within the specified window rather than the application'sbuffer virtual addresses.

(c) Added a host-driven memory test application MEMTESTH, which performs a test of the memorybanks on supported models.

(d) The MONITOR utility now accepts an option which specifies how many times to performmeasurements, so that (for example) a single set of measurements can be displayed.

(e) The SIMPLE example now exits when CTRL-D (Linux) is pressed or CTRL-Z is entered (Windows),instead of requiring 0x55AA to be entered.

(f) Command line application framework in $ADMXRC3_SDK/apps/src/common/:

• The FPGA configuration code from the command-line parsing framework code in$ADMXRC3_SDK/apps/src/common/args.c has been moved into a separate file$ADMXRC3_SDK/apps/src/common/fpga.c, so that args.c itself has no dependency on theADMXRC3 API.

(g) Various changes within the apps/src/ tree improve portability of source code, to facilitate building theapplications for Windows using non-Microsoft compilers such as gcc.


(a) Added the ADMXRC3_*DMA*Ex functions, which enable a 64-bit local address (i.e. OCP address)to be passed.

(b) Improved portability for non-Microsoft compilers such as gcc.

8 ADMXRC3 API import libraries (Win32):

(a) Updated to include the functions ADMXRC3_*DMA*Ex and ADMXRC3_*DMA*Ex, which enable a64-bit local address (i.e. OCP address) to be passed.

(b) Added GCC-compatible libraries in $ADMXRC3_SDK/lib/win32gnu.


(a) The MPTL cores for the ADM-XRC-6T1 in $ADMXRC3_SDK/hdl/vhdl/common/mptl/admxrc6t1have been updated. FPGA designs using these cores should be rebuilt.

The MPTL cores for the ADM-XRC-6TL in $ADMXRC3_SDK/hdl/vhdl/common/mptl/admxrc6tlhave been updated. FPGA designs using these cores should be rebuilt.

(b) Added support for full MPTL simulation. Previously, only OCP-only simulation was available.

(c) Added a new folder $ADMXRC3_SDK/hdl/constraints/, which contains required and



recommended synthesis constraints (.xcf) and implementation constraints (.ucf) for FPGA designs.Currently it contains mandatory constraints for the MPTL core and the Xilinx MIG v3.6 DDR3SDRAM interface.

(d) Added a new package adb3_ocp_comp, containing general purpose component definitions, to$ADMXRC3_SDK/hdl/vhdl/common/adb3_ocp/. Added new components adb3_ocp_mux_nb, adb3_ocp_ocp2ddr3_nb,adb3_ocp_retime_nb, and adb3_ocp_split_nb to adb3_ocp_comp package.

(e) Added a new folder $ADMXRC3_SDK/hdl/vhdl/common/mem_apps/, which contains theon-board memory application library. Added new component blk_mem_test to the mem_apps library.

(f) Added a new folder $ADMXRC3_SDK/hdl/vhdl/common/mem_if/, which contains on-boardmemory interface code.

Added new package mem_if_pkg.

Added a new folder $ADMXRC3_SDK/hdl/vhdl/common/mem_if/ddr3_sdram/, which containscode for DDR3 SDRAM on-board memory interfaces.

Added a new folder $ADMXRC3_SDK/hdl/vhdl/common/mem_if/ddr3_sdram/mig_v3_6/, whichcontains the generated Xilinx MIG v3.6 DDR3 interface files and scripts to generate those files.

Added new component ddr3_if_bank_v3_6, which is a wrapper for the Xilinx MIG v3.6 DDR3interface.

(g) Added a new folder $ADMXRC3_SDK/hdl/vhdl/common/mem_tb/, which contains on-boardmemory model library.

Added a new folder $ADMXRC3_SDK/hdl/vhdl/common/mem_tb/ddr3_sdram/, which containsDDR3 SDRAM model code.

Added new component ddr3_sdram to the mem_tb library.

(h) Uber example design:

• Added new blocks blk_bram, blk_clock_freq, blk_dma_switch, blk_ds_mem_reg,blk_mem_app, blk_mem_if, test_uber_dma_1ch_nb to$ADMXRC3_SDK/hdl/vhdl/examples/uber/common.

• Added connection of DMA OCP channel 0 to all banks of DDR3 SDRAM using the OCPswitching block blk_dma_switch and the DDR3 SDRAM bank interface blockddr3_if_bank_v3_6. Added connection of all DMA channels to blk_bram using the OCPswitching block blk_dma_switch. All banks of on-board memory and the blk_bram share thecommon DMA OCP channel 0 address space.

• Added connection of the Direct Slave OCP channel to all banks of DDR3 SDRAM. DirectSlave access to the DDR3 SDRAM banks is via a 2 MiB window augmented by the BANK and PAGE registers in block blk_ds_mem_reg.

• Added DDR3 SDRAM signals to the design's top level.

• Combined top-level GPIO signals into a single record.

• MPTL timing constraints have been moved from .ucf files to .xcf files.

• Added DDR3 SDRAM timing and pin LOC constraints to .ucf files.

• Added CONFIG STEPPING = 0 constraints to .ucf files, so that generated .bit files should becompatible with any device stepping.

• Changed the names of the clock signals output by blk_clocks to better reflect their purpose,and added a new clock used by the DDR3 SDRAM interfaces.



• The DMA test in the testbench has been changed from 2-channel blocking to 1-channelnon-blocking.

• The testbench now instantiates several instances of a DDR3 SDRAM device model, andperforms tests of the DDR3 SDRAM interfaces.

(i) Simple example design:

• Added CONFIG STEPPING = 0 constraints to .ucf files, so that generated .bit files should becompatible with any device stepping.



(a) The Uber example design sometimes fails to meet timing constraints when placed and routed usingthe Xilinx ISE tools. The workaround is to rebuild the design, which usually results in timing closure.In Windows, change directory to %ADMXRC3_SDK%\hdl\vhdl\examples\uber and execute"nmake clean_<model>_<device> bit_<model>_<device>". In Linux, change directory to$ADMXRC3_SDK/hdl/vhdl/examples/uber and execute "make clean_<model>_<device> bit_<model>_<device>".

This issue is scheduled to be corrected in the next release of the SDK.

Release 1.2.0The Xilinx ISE 12.2 toolset was used to generate the prebuilt bitstreams (.BIT) files in this release of the SDK.

Corrections:

1 General:

(a) Corrected an issue where file permissions in previous releases of the package were not appropriatefor the type of each file. Changed the uid and gid of the owner of the files in the package to 0 (i.e.root).


(a) Fixed a bug in the FLASH utility where endian conversion was omitted for the 32-bit boot flag,resulting in the boot flag being set incorrectly on big-endian machines.

(b) Fixed a memory leak in sampleParseCommandLine when it gets the ADMXRC3_SDK environmentvariable.


(a) Modelsim .do scripts now work correctly when executed in a Linux environment, as the'gen_today_pkg.bat' and 'gen_today_pkg.bash' scripts have been replaced by a TCL script'gen_today_pkg.tcl'.

(b) When executing 'make install' for the example FPGA designs in order to copy generated .BIT filesinto the $ADMXRC3_SDK/bit/ directory, spaces in the value of $ADMXRC3_SDK are now tolerated.

Enhancements:

4 General:

(a) Added support for VxWorks hosted on Windows or Linux.

5 Documentation:

(a) The SDK User Guide now includes information about VxWorks support and the VxWorks exampleapplications.




(a) Added VxWorks versions of most example applications.

(b) Added calls to sampleCleanupCommandLine to the example applications so that they no longerleak memory. This doesn't matter much unless using VxWorks, since VxWorks does notautomatically reclaim leaked memory when certain types of program terminate.

(c) Added command-line options to the INFO utility for showing information about I/O modules, Flashmemory banks and sensors.

(d) Changed the SIMPLE example to exit on CTRL-Z (Windows) or CTRL-D (Linux & VxWorks) insteadof entering 0x55AA.


(a) The header file <admxrc3.h> can now be included in a VxWorks application.


(a) The way that the MPTL clock and reference clock are input at the top level of the SIMPLE FPGAdesign has been simplified. The record type containing a bundle of possible clocks, of which onlyone clock is used, has been replaced by a single clock input. The .UCF file ensures that the correctdevice pins are used for this clock.

(b) The clock generation block blk_clocks.vhd in the UBER FPGA design has been improved:

• The MMCM parameters have been changed to allow a greater range of frequencies to beoutput.

• Two outputs intended for off-chip memory clocking have been added, one being 2x thefrequency of the other.

• The pll_usr_clk signal has been changed to 80 MHz and renamed pll_reg_clk to better reflectits usage, since it is used for clocking the register blocks in the design.

• The way the clock for the MPTL core is input from I/O pins has been simplified.

(c) The autogenerated VHDL file containing the build date for the UBER FPGA design is now generatedin the directory specific to the model being targetted, and its filename contains the model-devicecombination. This should (in theory) permit simultaneous builds of an FPGA design for more thanone model-device combination without risk of the builds interfering with each other. For example, forUBER targetting an ADM-XRC-6T1 with a 6VLX365T device, the generated file is$ADMXRC3_SDK/hdl/vhdl/examples/uber/admxrc6t1/today_pkg_admxrc6t1_6vlx365t.vhd.

(d) The MPTL cores for the ADM-XRC-6T1 in $ADMXRC3_SDK/hdl/vhdl/common/mptl/admxrc6t1 havebeen updated. FPGA designs using these cores should be rebuilt.

(e) Some model-specific signals used at the top level of the example FPGA designs have beencombined into the new record types mptl_sb_b2t_t and mptl_sb_t2b_t, representing sidebandsignals related to the MPTL. This change abstracts these bundles of signals as the details arenormally not of interest to end users.

(f) The MPTL wrapper mptl_if_target_wrap has a new input signal ocp_ready. This signal is assertedby the target FPGA design to indicate that it is ready to accept OCP transactions. The purpose ofthe signal is to hold off software on the host, by delaying return from theADMXRC3_ConfigureFrom* functions, until the target FPGA is ready (i.e. PLLs locked, IODELAYscallibrated etc.).

Release 1.1.0This is the first release of the ADM-XRC Gen 3 SDK for Linux.



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ADM-XRC Gen 3 SDK 1.7.0 for Linux Release Note V1.0

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