Addressing the Energy Efficiency Challenges of The Enabler ...soiconsortium.eu/wp-content/uploads/2018/10/201809... · Addressing the Energy Efficiency Challenges of IoT end points

The Enab le r o f Low-Power Sys tems-on -Ch ip !

Addressing the Energy Efficiency Challenges of

IoT end points FREDERIC RENOUX – SOI CONSORTIUM JAPAN – OCT. 2018

CORPORATE ID

Incorporated in 1985

150 highly qualified engineers to enable the design of Energy Efficient SoCs

> 600 Silicon IPs available at 180 nm to 22 nm in multiple foundries

• Power Management • Standard Cell libraries • Memory Compilers • Audio CODECs/ADCs/DACs and Triggers • Oscillators

Serving more than 500 companies worldwide, incl. more than 80 companies in Asia

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Renown for quality and support excellence

ENERGY-EFFICIENCY, THE NEW METRIC

•  Performance is not anymore the only constraint •  Power consumption has to be in the equation

Source:IBM,SemiconWest2018

Cloud Already developped

(More’s Moore driven)

Edge Emerging

Multiple techno/standards

Very Edge Future

Source:IMEC,ITF2018

Mops/µW

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Empty space for

now

A WORLD OF OPPORTUNITY, BUT

« There will be trillions of these IoT devices out there »

Jensen Huang, CEO of NVidia

« The speech and voice recognition market is expected to be valued at USD 6.19 Billion in 2017 and is likely to reach USD 18.30 Billion by 2023, at a CAGR of 19.80% between 2017 and 2023.»

Markets and Trends

« One of today’s technology most significant challenges is how to create a SOC that meets the conflicting consumer demand for devices with both high performance and extended battery life »

Samsung Semiconductor business

« …Power management is another feature, which in some cases may be the determining factor for whether a product (MCU) does well or fails because it affects battery life. Some of these MCUs have more than 16 low-power states, but to transition from one power state to the next is complex. »

Andrew Caples, Mentor a Siemens business

« The IoT technology market is expected to grow from USD 176.00 Billion in 2016 to USD 639.74 Billion by

2022, at a CAGR of 25.1% during the forecast period. »

Markets and Trends

Design Technology Disconnect

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THE CHALLENGE

Forbidden zone ?

How to make your AIoT SoC the most competitive? Performance Power x area

Time x costs

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Manageable complexity High complexity

Best value

FD-SOI OPPORTUNITY FOR BEST ENERGY EFFICIENCY

3x frequency at same Vdd ~250mV Vdd gain at same speed

Leakage Optimized Power Modes

32 bits DSP

Source: Ivan Miro-Panades, S3S tutorial

2017

Process Variations Mitigation

Leakage limit

IDD

Q

SS FF

Trimmed

Untrimmed

IDD

Q B

BG

EN @

EW

S/R

oom

Source: P. Flatresse, ST, ICICDT17

Le

akag

e

Frequency

  RemovedworstcasecornersforP,V,TandAgingduringdesign

  EnhancedchipPPA

  Noimpactonreliability

  Noneedforexternalvoltageregulator

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BODY BIASING CONTRIBUTION

Ener

gy e

ffici

ency

gai

n

Ultra Low Voltage High Perf General Purpose Low Power

Benchmark vs no BB

> 1.5GHz ~1GHz 200MHz < 50MHz

300%

600%

100%

20%

ENERGY EFFICIENCY SYSTEM DESIGN PLATFORM

Lower power IP impact

FinFET

Planar Bulk

FD-SOI

DolphinIntegration

Performance Power x area

Time x costs Manageable complexity High complexity

Forbidden zone

More advanced process impact

More advanced power

architecture impact

Maximum Body Biasing

impact

To enable Cost-Effective design of most Energy Efficient SoCs

Up to + 600% EE @ Low Voltage with BB Up to +100% EE @ Nominal voltage with BB

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EE SYSTEM DESIGN PLATFORM – PHASE #1

Key features

•  Complete solution supporting advanced power architectures and LP techniques, DVFS, AVS, BB, NTV, power domain partitioning…

•  State-of-the-art IPs: EE, small area, low fabrication costs, Low BoM costs…

•  Configurable and scalable to any SoC complexity and current requirements (up to 128 power domains…)

•  Compliant with pure logic design flow + standardized IP interface for smooth SoC int.

•  Workable with third-party silicon IPs

•  Built-in safety features to prevent SoC failures

•  Based on silicon proven IP architectures…

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Power Island#1

Power Island#2

IOs Power

Island#3

Voltage Regulators (LDO/DC-DC)

Power

Gating

Power

Gating

Power

Gating

Power

Gating

ePMU/ACU

monitor monitor

monitor monitor

Up to 5.5 V input

voltage Down to 0.6 V

SoC

Enablement of advanced SoC power architecture to

bridge the complexity gap

FD-SOI PHASE #1 – since 2016

TO MAKE THE HARD BODY BIASING EASY

Enhanced EE System Design Platform

+  Body Bias Generators

➙  Ultra low power (10 uA)…

+  Monitors

➙  High accuracy In-Situ Monitors…

+  Fully integration

➙  Embedded regulation loop for process, temperature & aging compensation

➙  Workable with any standard-cell library & memory…

+  Design methodology & support

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Enablement of Adaptive Body Biasing as turnkey solution for

best Energy Efficiency without risks

FD-SOI PHASE #2 – going-on

Power Island#1

Power Island#2

IOs Power

Island#3

Voltage Regulators (LDO/DC-DC)

Power

Gating

Power

Gating

Power

Gating

Power

Gating

ePMU/ACU

monitor monitor

monitor monitor

BB gen

BB gen

BB gen

BB gen SoC

Up to 5.5 V input voltage

Down to 0.4 V

BACKBONE TO DESIGN COST-EFFECTIVELY EE SOCS Under copyrights 2018/10/24 Page 9

Adaptive Body Biasing (ABB) System Design Platform

EE TTM

Risk Area

Fab/BoM costs

EE System Design Platform with built-in ABB support with roadmap for further TTM and cost improvements

EE improvement TTM acceleration

Risk Minimization

Area reduction

Fab/BoM costs Minimization

EE System Design Platform w/o ABB

EE TTM

Risk Area

Fab/BoM costs

BACKBONE TO DESIGN COST-EFFECTIVE EE SOCS

•  World best-in-class ENERGY EFFICIENCY Sleep mode below 1 uA at 28/22 nm Up to 95% efficiency in active modes Twice faster mode transition time

•  No need for advanced LP or BB expertise for best TTM

Usable with pure logic design flow without requiring analog exp.

Design guidance with know-how transfer

•  Reduced silicon and system COSTS

•  Lowered design & fab. RISKS Built-in Adaptive BB control In-rush current under control (even after tape-out) Start-up and mode transition safety Preventing risk of ESD issue during IO wake-up…

$ $

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SUCCESS STORY ILLUSTRATION

CATALOG OF SILICON IPS FOR ENERGY-EFFICIENCY

SUPPORT FROM SOC ARCHITECTURAL EXPERTS

COOPERATIVE APPROACH FOR BEST

PPA WITH FIRST TIME SILICON SUCCESS

SOC DESIGN

Optimized Power Architecture

Energy Efficiency System Design

Platform

GAP8

Consistent and complete set of IP deliverables

SUPPORT FROM SOC INTEGRATION EXPERTS

Streamlined and secured integration

Industry’s lowest power IoT application processor,

enabling groundbreaking Artificial Intelligence at the very edge (55 nm)

ü  200 MOPS at 3 mW

ü  Minimum 2 uA standby current

ü  Energy efficiency : 15 GOPS for 70 mW

ü  2 DVFS domains

ü  Fast switching (from us to sub ms) between 6

operating modes

ü  Designed in less than 18 months

ü  First Time Silicon Success

Read or listen the insights of Eric Flamand – Greenwaves’ CTO – on Dolphin’s power management offering – DOLPHIN’s web site

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ENERGY-EFFICIENCY, THE NEW METRIC

Cloud Already developped

(More’s Moore driven)

Edge Emerging

Multiple techno/standards

Very Edge Future

Source:IMEC,ITF2018

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Frederic Renoux

Executive VP Sales

Mobile: + 33 772 451 540

[email protected]