AD9642/AD9634/AD6672 User Guide - analog.com · dual switching power supply to provide power to the DRVDD and AVDD rails of the ADC. To configure the board to operate from the ADP2114,

AD9642/AD9634/AD6672 User GuideUG-386

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the AD9642/AD9634/AD6672 Analog-to-Digital Converters

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 26

FEATURES Full featured evaluation board for the

AD9642/AD9634/AD6672 SPI interface for setup and control External or AD9523 clocking option Balun/transformer or amplifier input drive option LDO regulator power supply VisualAnalog and SPI controller software interfaces

EQUIPMENT NEEDED Analog signal source and antialiasing filter Sample clock source (if not using the on-board oscillator)

2 switching power supplies (6.0 V, 2.5 A), CUI EPS060250UH-PHP-SZ, provided

PC running Windows® 98 (2nd ed.), Windows 2000, Windows ME, or Windows XP

USB 2.0 port recommended (USB 1.1 compatible) AD9642, AD9634, or AD6672 evaluation board HSC-ADC-EVALCZ FPGA-based data capture kit

SOFTWARE NEEDED VisualAnalog SPI controller

DOCUMENTS NEEDED AD9642, AD9634, or AD6672 data sheet HSC-ADC-EVALCZ data sheet AN-905 Application Note, VisualAnalog Converter Evaluation

Tool Version 1.0 User Manual AN-878 Application Note, High Speed ADC SPI Control Software AN-877 Application Note, Interfacing to High Speed ADCs via SPI AN-835 Application Note, Understanding ADC Testing and

Evaluation

GENERAL DESCRIPTION This user guide describes the AD9642, AD9634, and AD6672 evaluation board, which provides all of the support circuitry required to operate the AD9642, AD9634, and AD6672 in their various modes and configurations. The application software used to interface with the devices is also described.

The AD9642, AD9634, and AD6672 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at http://www.analog.com/fifo. For additional information or questions, send an email to [email protected].

TYPICAL MEASUREMENT SETUP 10

593-

001

Figure 1. AD9642, AD9634, or AD6672 Evaluation Board (on Left) and HSC-ADC-EVALCZ Data Capture Board (on Right)

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http://www.analog.com/AD9642?doc=UG-386.pdf






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mailto:[email protected]





UG-386 AD9642/AD9634/AD6672 User Guide

TABLE OF CONTENTS Features .............................................................................................. 1 Equipment Needed ........................................................................... 1 Software Needed ............................................................................... 1 Documents Needed .......................................................................... 1 General Description ......................................................................... 1 Typical Measurement Setup ............................................................ 1 Revision History ............................................................................... 2 Evaluation Board Hardware ............................................................ 3

Power Supplies .............................................................................. 3 Input Signals .................................................................................. 3

Output Signals ...............................................................................4 Default Operation and Jumper Selection Settings ....................4

Evaluation Board Software Quick Start Procedures .....................6 Configuring the Board .................................................................6 Using the Software for Testing .....................................................6

Evaluation Board Schematics and Artwork ................................ 13 Ordering Information .................................................................... 22

Bill of Materials ........................................................................... 22 Related Links ................................................................................... 24

REVISION HISTORY 11/14—Rev. 0 to Rev. A

Changes to Setting Up the SPI Controller Software Section and Deleted Figure 10 .............................................................................. 8

4/12—Revision 0: Initial Version

Rev. A | Page 2 of 26

AD9642/AD9634/AD6672 User Guide UG-386


EVALUATION BOARD HARDWARE The AD9642, AD9634, and AD6672 evaluation board provides all of the support circuitry required to operate these parts in their various modes and configurations. Figure 2 shows the typical bench characterization setup used to evaluate the ac performance of the AD9642, AD9634, or AD6672. It is critical that the signal sources used for the analog input and the clock have very low phase noise (<1 ps rms jitter) to realize the opti-mum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the inte-grated or broadband noise at the input is necessary to achieve the specified noise performance.

See the Evaluation Board Software Quick Start Procedures section to get started, and see Figure 18 to Figure 29 for the complete schematics and layout diagrams. These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters.

POWER SUPPLIES This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2.5 A maximum output. Connect the supply to a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The output from the supply is provided through a 2.1 mm inner diameter jack that connects to the printed circuit board (PCB) at P201. The 6 V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators (default configuration) that supply the proper bias to each of the various sections on the board.

The evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, remove the jumpers on the P104, P107, P108, and P105 header pins to disconnect the outputs from the on-board LDOs. This enables the user to bias each section of the board individually. Use P202 and P203 to connect a different supply for each section. A 1.8 V supply is needed with a 1 A current capability for DUT_AVDD and DRVDD; however, it is recommended that separate supplies be used for both analog and digital domains. An additional supply is also required to supply 1.8 V for digital support circuitry on the board, DVDD. This should also have a 1 A current capability and can be combined with DRVDD with little or no degradation in performance. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply is needed in addition to the other supplies. This 3.3 V supply, or 3P3V_ANALOG, should have a 1 A current capability. This 3.3 V supply is also used to support the optional input path amplifier (ADL5201) on Channel A and Channel B.

INPUT SIGNALS When connecting the clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA or HP 8644B signal generators or an equivalent. Use a 1 m shielded, RG-58, 50 Ω coaxial cable for connecting to the evalua-tion board. Enter the desired frequency and amplitude (see the Specifications section in the data sheet of the respective part).

WALL OUTLET100V TO 240V AC

47Hz TO 63HzSWITCHINGPOWERSUPPLY

SWITCHINGPOWERSUPPLY

SIGNAL SYNTHESIZER

SIGNAL SYNTHESIZER

OPTIONAL CLOCK SOURCE

ANALOGFILTER

PCRUNNING ADC

ANALYZEROR VISUAL ANALOG

USER SOFTWARE

6V DC2.5A MAX

6V DC2.5A MAX

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Figure 2. Evaluation Board Connection







http://www.analog.com/adl5201?doc=UG-386.pdf

UG-386 AD9642/AD9634/AD6672 User Guide When connecting the analog input source, use of a multipole, narrow-band, band-pass filter with 50 Ω terminations is recom-mended. Analog Devices, Inc., uses TTE and K&L Microwave, Inc., band-pass filters. The filters should be connected directly to the evaluation board.

If an external clock source is used, it should also be supplied with a clean signal generator as previously specified. Typically, most Analog Devices evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave input for the clock.

OUTPUT SIGNALS The default setup uses the Analog Devices high speed converter evaluation platform (HSC-ADC-EVALCZ) for data capture. The output signals from Channel A and Channel B for the AD9642, AD9634, and AD6672 are routed through P601 and P602, respectively, to the FPGA on the data capture board.

DEFAULT OPERATION AND JUMPER SELECTION SETTINGS This section explains the default and optional settings or modes allowed on the AD9642/AD9634/AD6672 evaluation board.

Power Circuitry

Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P201.

Analog Input

The A and B channel inputs on the evaluation board are set up for a double balun-coupled analog input with a 50 Ω impedance. This input network is optimized to support a wide frequency band. See the AD9642, AD9634, and AD6672 data sheets for additional information on the recommended networks for different input frequency ranges. The nominal input drive level is 10 dBm to achieve 2 V p-p full scale into 50 Ω. At higher input frequencies, slightly higher input drive levels are required due to losses in the front-end network.

Optionally, Channel A and Channel B inputs on the board can be configured to use the ADL5201 digitally controlled, variable gain wide bandwidth amplifier. The ADL5201 component is included on the evaluation board at U401. However, the path into

and out of the ADL5201 can be configured in many different ways depending on the application; therefore, the parts in the input and output path are left unpopulated. See the ADL5201 data sheet for additional information on this part and for configuring the inputs and outputs. The ADL5201, by default, is held in power-down mode but can be enabled by adding 1 kΩ resistors at R427 and R428 to enable Channel A and Channel B, respectively.

Clock Circuitry

The default clock input circuit that is populated on the AD9642/ AD9634/AD6672 evaluation board uses a simple transformer-coupled circuit with a high bandwidth 1:1 impedance ratio transformer (T503) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The trans-former converts the single-ended input to a differential signal that is clipped by CR503 before entering the ADC clock inputs.

The board is set by default to use an external clock generator. An external clock source capable of driving a 50 Ω terminated input should be connected to J506.

A differential LVPECL clock driver output can also be used to clock the ADC input using the AD9523 (U501). To place the AD9523 into the clock path, populate R541 and R542 with 0 Ω resistors and remove C532 and C533 to disconnect the default clock path inputs. In addition, populate R533 and R534 with 0 Ω resistors, remove R522 and R523 to disconnect the default clock path outputs, and insert AD9523 LVPECL Output 2. The AD9523 must be configured through the SPI controller software to set up the PLL and other operation modes. Consult the AD9523 data sheet for more information about these and other options.

PDWN

To enable the power-down feature, Bits[1:0] of Register 0x08 must be written for the desired power-down mode.

OEB

To disable the digital output pins and place them in a high imped-ance state, Bit 4 of Register 0x14 must be written.

AD9642/AD9634/AD6672

15Ω0.1µF2V p-pVIN+

VIN– VCM

3.9pF

3.9pF

15Ω0.1µF

S0.1µF

3.9pF

36Ω

36ΩSPA P

49.9Ω

49.9Ω

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Figure 3. Default Analog Input Configuration of the AD9642/AD9634/AD6672












http://www.analog.com/ADL5201?doc=UG-386.pdf
















AD9642/AD9634/AD6672 User Guide UG-386 Switching Power Supply

Optionally, the ADC on the board can be configured to use the ADP2114 dual switching power supply to provide power to the DRVDD and AVDD rails of the ADC. To configure the board to operate from the ADP2114, the following changes must be incorporated (see the Evaluation Board Schematics and Artwork and the Bill of Materials sections for specific recommendations for part values):

1. Install R204 and R221 to enable the ADP2114. 2. Install R216 and R218.

3. Install L201 and L202. 4. Remove JP201 and JP203. 5. Remove jumpers from across Pin 1 and Pin 2 on P107 and

P108, respectively. 6. Place jumpers across Pin 1 and Pin 2 of P106 and P109,

respectively.

Making these changes enables the switching converter to power the ADC. Using the switching converter as the ADC power source is more efficient than using the default LDOs.


http://www.analog.com/ADP2114?doc=UG-386.pdf





EVALUATION BOARD SOFTWARE QUICK START PROCEDURES This section provides quick start procedures for using the AD9642/ AD9634/AD6672 evaluation board. Both the default and optional settings are described.

CONFIGURING THE BOARD Before using the software for testing, configure the evaluation board as follows:

1. Connect the evaluation board to the data capture board, as shown in Figure 1 and Figure 2.

2. Connect one 6 V, 2.5 A switching power supply (such as the CUI, Inc., EPS060250UH-PHP-SZ that is supplied) to the AD9642/AD9634/AD6672 board.

3. Connect another 6 V, 2.5 A switching power supply (such as the CUI EPS060250UH-PHP-SZ that is supplied) to the HSC-ADC-EVALCZ board.

4. Connect the HSC-ADC-EVALCZ board (J6) to the PC with a USB cable.

5. On the ADC evaluation board, confirm that jumpers are installed on the P105, P108, P104, P107, and P110 headers.

6. Connect a low jitter sample clock to Connector J506. 7. Use a clean signal generator with low phase noise to provide

an input signal to the desired channel(s) at Connector J301 (Channel A) and/or Connector J303 (Channel B). Use a 1 m, shielded, RG-58, 50 Ω coaxial cable to connect the signal generator. For best results, use a narrow-band band-pass filter with 50 Ω terminations and an appropriate center frequency. (Analog Devices uses TTE, Allen Avionics, and K&L band-pass filters.)

USING THE SOFTWARE FOR TESTING Setting Up the ADC Data Capture

After configuring the board, set up the ADC data capture using the following steps:

1. Open VisualAnalog® on the connected PC. The appro-priate part type should be listed in the status bar of the VisualAnalog – New Canvas window. Select the template that corresponds to the type of testing to be performed (see Figure 4 where the AD9642 is shown as an example). The AD9642 is given as an example in this user guide. Similar settings are used for the AD9634. For the AD6672, the differences are noted where necessary in the steps that follow.

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Figure 4. VisualAnalog, New Canvas Window

2. After the template is selected, a message appears asking if the default configuration can be used to program the FPGA (see Figure 5). Click Yes, and the window closes.

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Figure 5. VisualAnalog Default Configuration Message

3. To change features to settings other than the default settings, click the Expand Display button, located on the bottom right corner of the window (see Figure 6) to see what is shown in Figure 7. Detailed instructions for changing the features and capture settings can be found in the AN-905 Application Note, VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual. After the changes are made to the capture settings, click the Collapse Display button.

EXPAND DISPLAY BUTTON

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Figure 6. VisualAnalog Window Toolbar, Collapsed Display













http://www.analog.com/an-905



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Figure 7. VisualAnalog, Main Window

Setting Up the SPI Controller Software

After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:

1. Open the SPI controller software by going to the Start menu or by double-clicking the SPIController software desktop icon. If prompted for a configuration file, select the appropriate one. If not, check the title bar of the window to determine which configuration is loaded. If necessary, choose Cfg Open from the File menu and select the appropriate file based on your part type. Note that the CHIP ID(1) section should be filled to indicate whether the correct SPI controller configuration file is loaded (see Figure 8).

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Figure 8. SPI Controller, CHIP ID(1) Section



2. Click the New DUT button in the SPIController window (see Figure 9).

NEW DUT BUTTON

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Figure 9. SPI Controller, New DUT Button

3. In the ADCBase 0 tab of the SPIController window, find the CLK DIV(B) section (see Figure 10). If using the clock divider, use the drop-down box to select the correct clock divide ratio, if necessary. See the appropriate part data sheet; the AN-878 Application Note, High Speed ADC SPI Control Software; and the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, for additional information. Note that other settings can be changed on the ADCBase 0 tab (see Figure 10). See the appropriate part data sheet; the AN-878 Application Note, High Speed ADC SPI Control Software; and the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, for additional information on the available settings.

Figure 10. SPI Controller, CLK DIV(B) Section







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Figure 11. SPI Controller, Example ADCBase 0 Tab—NSR Settings for the AD6672

4. If using the noise shaping requantizer (NSR) feature of the AD6672, the settings in the ADCBase 0 tab must be changed (see Figure 11). The NSR Enable checkbox must be selected under the NOISE SHAPED REQUANTIZER 1(3C) section. This enables the circuitry in the AD6672. To select the bandwidth mode, use the NSR Mode drop-down box in the NOISE SHAPED REQUANTIZER 1(3C) section. Upon selecting the bandwidth mode, select the desired tuning word in the NSR Tuning drop-down menu under the NOISE SHAPED REQUANTIZER TUNING(3E) section.

5. Click the Run button in the VisualAnalog toolbar (see Figure 12).

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Figure 12. Run Button (Encircled in Red) in VisualAnalog Toolbar, Collapsed Display






Adjusting the Amplitude of the Input Signal

The next step is to adjust the amplitude of the input signal for each channel as follows:

1. Adjust the amplitude of the input signal so that the fundamen-tal is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog Graph window.) See Figure 14.

2. Repeat this procedure for Channel B if desired. 3. Click the Save disk icon within the Graph window to save

the performance plot data as a .csv formatted file. See Figure 13 for an example.

0

–1400 25 50 75 100 125

AM

PLIT

UD

E (d

BFS

)

FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

250MSPS90.1MHz @ –1dBFSSNR = 71dB (72dBFS)SFDR = 89dBc

THIRD HARMONIC

SECOND HARMONIC

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Figure 13. Typical FFT, AD9642

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Figure 14. Graph Window of VisualAnalog (AD9642)





4. If operating the AD6672 with NSR enabled, certain options in VisualAnalog must be enabled. Click the button circled

in the FFT Analysis box (see Figure 15) in VisualAnalog to bring up the options for setting the NSR.

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Figure 15. VisualAnalog, Main Window—Showing FFT Analysis for AD6672





5. Configure the settings in the FFT analysis to match the settings selected for the NSR in the SPI controller (see Figure 16).

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Figure 16. VisualAnalog, FFT Analysis Settings for AD6672

6. The result should show an FFT plot that looks similar to Figure 17.

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Figure 17. Graph Window of VisualAnalog, NSR Enabled, AD6672

7. The amplitude shows approximately 0.6 dB lower than when the NSR is disabled. The NSR circuitry introduces this loss. An amplitude of −1.6 dBFS with NSR enabled is analogous to an amplitude of −1.0 dBFS with NSR disabled.

8. Repeat Step 3 to save the graph in a .csv file format.

Troubleshooting Tips

If the FFT plot appears abnormal, do the following:

If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure that you are not overdriving the ADC. Reduce the input level if necessary.

In VisualAnalog, click the Settings button in the Input Formatter block (see Figure 7). Check that Number Format in the settings of the Input Formatter block is set to the correct encoding (offset binary by default). Repeat for the other channel.

If the FFT appears normal but the performance is poor, check the following:

Make sure that an appropriate filter is used on the analog input.

Make sure that the signal generators for the clock and the analog input are clean (low phase noise).

Change the analog input frequency slightly if noncoherent sampling is being used.

Make sure that the SPI configuration file matches the product being evaluated.

If the FFT window remains blank after Run (see Figure 12) is clicked, do the following:

Make sure that the evaluation board is securely connected to the HSC-ADC-EVALCZ board.

Make sure that the FPGA has been programmed by verifying that the DONE LED is illuminated on the HSC-ADC-EVALCZ board. If this LED is not illuminated, make sure that the U4 switch on the board is in the correct position for USB CONFIG.

Make sure that the correct FPGA program was installed by clicking the Settings button in the ADC Data Capture block in VisualAnalog. Then select the FPGA tab and verify that the proper FPGA bin file is selected for the part.

If VisualAnalog indicates that the data capture timed out, do the following:

Make sure that all power and USB connections are secure. Probe the DCO signal at the ADC on the evaluation board

and confirm that a clock signal is present at the ADC sampling rate.







EVALUATION BOARD SCHEMATICS AND ARTWORK

ADD 1UF AT DUT PIN #3

AD9642/AD9634 ENG (SOCKET)

DUT

THE FOOTPRINT FOR THIS SOCKED NEEDS TO BE CHECKED AGAINST THE DRAWING

LAYOUT: DECOUPLING QUANTITY MAY VARY LAYOUT DEPENDI

1

TP101

1

TP102

1

TP105

1

TP103

1

TP104

C122

1

TP_KPIBIAS

PAD 9

87654

323130

3

2928272625

24

23

22

21

20

2

19

18

17

16151413121110

1

U1010

C105

C113

C112

C111

C110

C109

C103

C101

C121

C117

C118

C107

D12/D13+

D12/D13-

CLK-

D0/D1+

D2/D3-

SG-MLF32A-7004

D10/D11+

D10/D11-

DRVDD

D6/D7+

D8/D9-

D8/D9+

D6/D7-

D4/D5+

D4/D5-

D2/D3+

D0/D1-

AVDD

DUT_CSB

DCO+

VIN+

VIN-

DUT_SDIO

DUT_SCLK

0.1UF

0.1UF

DRVDD

AVDD

1UF

0.1UF

1UF

VCM

AVDD

AVDD

0.1UF

VCM

1UF

0.1UF

0.1UF

1UF

1UF

KP_VDDIO

CLK+

DRVDD

DCO-

0.1UF

0.1UF

10593-019

Figure 18. Device Under Test and Related Circuits



POWER

TO EVALUATE SHARING OF AVDD AND DVDD

SUPPLY

SWITCHING

OPTIONAL

C242

C205 C208

C229C226

C218

C217

C215

C243

C241

C230

C228

C227

C225

C209

C207C204

C206

C239

C235C233C231

51

42

3

U207

21E217

21

P110

51

42

3

U203

51

42

3

U202

21

P109

21

P1082

1

P107

21

P106

21

P1052

1

P104

R210

21E2092

1E208

21JP2032

1JP201

R217

C221

21E210

R216

C220

L201

R219

21E211

C224

C223

R218

L202

R215

C219

R220

C222

C213

R214

C214

R213

R208

R207

C216

R206

C212

C211

C210

R205

R204

R209

U206

R212

R211

R221

R222

654321

P202

4321

P203

21E216

NP

C240

AC

CR204

AC

CR206

2 1

E203

21E204

21E212 2

1E213 2

1E214

2 1

E206

87

PAD

6543

2

1

U205

21E207

AC

CR205

21E205

21E202

87

PAD

6543

2

1

U204

R201

321

P201

NP

C201

21F201

ACCR201

CR203

AC

CR202

36 542

1

FL201

NP

C232

NP

C236NP

C234

LNJ314G8TRA (GREEN)

VIN

SK33A-TP

BNX016-01

3P3V_DIGITAL

4.7UF

ADP150AUJZ-3.3-R7

261

ADP150AUJZ-3.3-R7

100MHZ

3P3V_ANALOG

100MHZ

100MHZ

0.01UF

4.7UF

0.01UF

4.7UF

4.7UF

4.7UF

ADP1706ARDZ-1.8-R7

4.7UF

100MHZ

100MHZ

22UF

100MHZ

Z5.531.3425.0

0.1UF

0.1UF0.1UF

10UF

0.1UF

100MHZ

1P8V_CLOCK

100MHZ

S2A-TP

0

DNI

100MHZ

ADP2114_PRELIM

VOUTB

EN2

VOUTA

EN1

SW_FREQ

0

100MHZ

VIN

10UF

DNI

DNI

2.2UH

DNI

DNI

2200PF

100PF

VOUTB

TBD0603

2.2UH

S2A-TP

100MHZ

DNI

100MHZ

DRVDD

AVDD

DNI

Z5.531.3625.0

10UF

100MHZ

100MHZ

22UF

1UF

1.00K

27K

0

10

DNI

0

VOUTA

EN2

VIN

EN1

22UF

1.00K

DNI0

15K

15K

0

22UF

0

DRVDD

3P3V_DIGITAL

DNI

VIN

100K 13K

22UF

22UF

TBD0603

100PF

0

TBD0603

100MHZ

10UF10UF

10.5K 1500PF

DNI

4.64K

0.01UF

0.01UF

4.7UF

0.01UF

4.7UF

DNI

DNI

4.7UF

0.01UF

DNI

ADP1706ARDZ-1.8-R7

TBD0603

4.7UF

0.01UF

DNI

3P3V_ANALOG

S2A-TP

1.1A

PJ-202A

AVDD

100K

ADP150AUJZ-1.8-R7

GND

NC

VOUT

EN

VIN

GND

NC

VOUT

EN

VIN

GND

NC

VOUT

EN

VIN

VIN6

VIN5

VIN4

VIN3

VIN2

VIN1

VDD

PAD

PGND4

PGND3

PGND2

PGND1

GND

SS2

FB2

V2SET

SW4

SW3

COMP2

PGOOD2

SW2

SW1

COMP1

PGOOD1

EN2

SS1

FB1

V1SET

EN1

OPCFG

SYNC_CLKOUT

FREQ

SCFG

PAD

SS

IN GND1

SENSE

OUT

EN

IN2

OUT2

PAD

SS

IN GND1

SENSE

OUT

EN

IN2

OUT2

10593-020

Figure 19. Board Power Input and Supply



SHARE PADS

ANALOG INPUT

SHARE PADS

LAYOUT: SMA'S SHOULD BE PLACED 540 MILS CENTER TO CENTER

PASSIVE PATH

AIN

DNI 2

J302

1

35

C314

64 2

31

T301

L301

R304

4

R305

R306

R310

R307R308

R309

R303

R302

R301

54

32

1J301

5

4 3

1

T303

543 1

T302

C306

C305

C301

R320

R319

C303

R317

C302

R318

C304

R315

R313

R316

R314

R311

R312

DNI

DNI

ADT1-1WT+

DNI

0.1UF

0

0

MABA-007159-000000

AMP_IN+

0.1UF

MABA-007159-000000

0

AMP_OUT+

AMP_OUT-

36

82NH

VCM

DNI

0.1UF

0.1UF

36

49.9

DNI

0

00

DNI

DNI

DNI

DNI

DNI

49.9

0

49.9

8.2PF

8.2PF

0

DNI

33

33

VIN+

49.9

8.2PF

0

0

0

VIN-

AMP_IN-

DNI

0

SECPRI

SEC

PRI

10593-021

Figure 20. Passive Analog Input Circuits



THESE RLCS ARE PLACE HOLDERS... PLACE CORRECT VALUES & COMPONENTS...

ACTIVE PATH

5 431T401

L405

L403

L401

R410

C406

NPC405

C404

R408

R412

R409

L406

C410

L404

C409

L402C408

R411

C407

21JP401

C403

1110

1 2 43

9

8765

PAD16151413

12

U401

R403 R404

C401

R401

R405

21

P401

R407

R406

C402

R402

JPR0402

3P3V_ANALOG

ADL5562_PRELIM

PD_N_A

DNI

0.1UF

1.00K

DNI

0

0

DNI

MABA-007159-000000

VCM

AMP_OUT+

DNI

DNI

0 DNI

DNI

5PF

DNI

DNI

DNI

DNI

120NH

120NH

DNI

82NH

AMP_OUT-

DNI

82NH

40.2

DNI

5PF

0.1UF

DNI

1.00K120NH

0

3P3V_ANALOG

0

1.1K

PD_N_A0

10UF

120NH

DNI

0.1UF

0.1UF

AMP_IN+

AMP_IN-

0.1UF

VCM

0

40.2

0.1UF

DNI

DNI

DNI

0.1UF

SEC

PRI

PAD

GND

ENBL

VON

VOP

VCOM

VCC

VIN2

VIN1

VIP1

VIP2

10593-022

Figure 21. Optional Active Input Circuits



PECL/CML/LVDS CLK CIRCUITRY

ACTIVE CLOCK PATH

5

4 3

1

T501

C510

C509

C521

C520

C516

C515C514

C548

C546

C545

C543

C544

C542

C541

C540

C547

C539

C538

C536

C537

C535

C519

C518

C517

C505

C506

C507

C504C502

C501

C513

C512

C531

L507

C530

54

32

1J503

R521

R520

R546

R519

R545

R544

R536

R535

R532

R531

R527

R526

R525

R524

7170

42

48

54

63

30

36

69

18

132

39

45

51

60

27

33

66

17

5556

232221

19

6543

24

16

72

15

PAD

37

38

40

41

43

44

46

47

49

50

52

53

5859

6162

64

2526

2829

3132

3435

65

6768

1098

117

14

121

57

20

U501

21E502

L506

1

TP505

1

TP504

21E501

C527

C534

C526

C525

C524

L501

L502

L503

L504

L505

R501

R510

R511

R512

R518

R517

R515

R516

1TP501

R509

C508

C511

R507

R508

CR501

CR502

R505

R503 R604

R502

C503

R506

R513

R514

46

5 2

31

U300

61

54

3

Y501

1

TP502

1

TP503

5432

1J502

0.1UF

DNI

MABA-007159-000000

0.1UF

100

49.9

DNI49.9

0.1UF

45OHMS

45OHMS

DNI

100

0.1UF

STATUS1/SP1

DNI

3.3V_OUT_4-13

CYP_SDO

USB_CSB2

3.3V_REF

3.3V_OUT_4-13

0.001UF

0.001UF

DNI

0.1UF

0.1UF

0.1UF

0.1UF

SI04

0.1UF

3.3V_OUT_0-3

1.8V_OUT_0-13

200

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1.8V_OUT_0-13

0.1UF

1.8V_OUT_0-13

0.1UF

0.1UF

3.3V_OUT_4-13

0.1UF

0.1UF

1.8V_OUT_0-13

3.3V_OUT_0-3

0.1UF

100

49.9CLK_IN-

0.1UF

49.9

0.1UF

0.1UF

60-800MHZ

0.1UF

3.3V_PLL1

0.33UF

0.47UF

100

OUT0OUT0_N

OUT2_N

3.3V_OUT_4-13

1.8V_OUT_0-13

OUT13

OUT13_N

CYP_SDI

SYNCB

PDB

3.3V_PLL2

3.3V_PLL1

DNI

CLK_OUT+

OUT2

10UF

3.3V_PLL1

10UF

3.3V_OUT_0-3

3.3V_OUT_4-13

3.3V_OUT_4-13

DNI

3.3V_OUT_0-3

100

100

100

STATUS0/SP0

100

100

3P3V_ANALOG

1K

10K

10K

1UH

49.9

100

100

10K

10K

200

LNJ314G8TRA (GREEN)

1UH

1UH

1UH

100

1UH

10K

100

VCXO_CTRL

0DNI

0

TBD0402

3.3V_REF

100

10K

RESETB

3.3V_REF

49.9

LNJ314G8TRA (GREEN)

3P3V_DIGITAL

0.47UF

0.47UF

3.3V_REF

10UF

10UF

10UF

10UF

1UH

3.3V_PLL2

NC7WZ16P6X

3.3V_OUT_4-13

12PF

0.33UF

CYP_SCLK

3.9NH

CLK_OUT-

EEPROM_SEL

1P8V_CLOCK

AD9523

0.1UF

CLK_IN+

SECPRI

VDD_1_8_OUT6_7

VDD_1_8_OUT4_5

VDD_1_8_OUT2_3

VDD_1_8_OUT0_1

SCLK_SCL

PADPLL1_OUT

ZD_IN_NZD_IN

OUT0OUT0_N

VDD3_OUT0_1OUT1

OUT1_N

OUT2OUT2_N

VDD3_OUT2_3OUT3

OUT3_NEEPROM_SEL

STATUS0_SP0STATUS1_SP1

OUT4

OUT4_N

VDD3_OUT4_5

OUT5

OUT5_N

OUT6

OUT6_N

VDD3_OUT6_7

OUT7

OUT7_N

VDD_1_8_OUT8_9

OUT8

OUT8_N

VDD3_OUT8_9

OUT9

OUT9_N

VDD_1_8_OUT10_11OUT10OUT10_NVDD3_OUT10_11OUT11OUT11_NVDD_1_8_OUT12_13OUT12OUT12_NVDD3_OUT12_13OUT13OUT13_NREF_TESTSDO

SDIO_SDA

CS_NRESET_N

VDD3_REF

SYNC_N

REF_SEL

PD_N

LDO_VCO

VDD3_PLL2

LDO_PLL2

LF2_EXT_CAP

OSC_IN_N

OSC_IN

OSC_CTRL

LF1_EXT_CAP

REFB_N

REFB

REFA_N

REFA

VDD3_PLL1

LDO_PLL1

Y2

Y1

A2

A1

GND

VCC

OUT-

OUT+

VC

VCC GND

LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER

LAYOUT: SHARE PADS WITH ACTIVE CLOCK PATH R'S

PASSIVE CLOCK

CLK

R543

5 431T503

R528

C533

C532

C523

C529

C522

R523

R522

R542R541

R533 R534

R539

12

3

CR503

R540

R537

R529

54

32

1J505

6 42

3 1

T502

R538

R530

54

32

1J506

CLK-

CLK+

DNI

100

MABA-007159-000000

33

0

0

33

DNI 0

0

390PF

DNI

390PF

DNI

390PF

49.9

DNI

DNI 49.9

CLK_IN+

0

DNI

390PF

ADT1-1WT+ 0.1UF

DNI0

0

CLK_OUT+

CLK_IN-

0

DNI

DNI

0

DNI

CLK_OUT-

DNI

SEC

PRI

10593-023

Figure 22. Default and Optional Clock Input Circuits



LAYOUT: ROUTE ALL TRACES TO THETYCO CONN ON TOP OF BOARD

SPI & FPGA CONN.

USING FIFO5(UNUSED PINS REMOVED)

NOTE: THIS SYMBOL IS DRAWN GIVEN INPUT 1 LOGIC

LAYOUT: PLACE C602 NEAR DUT

C604

C601

C603

C602

R645

R644

R643

R646

R637

R636

R635

R633

R629

1

TP_DUT_SDIO

1

TP_CYP_SDIO

1

TP612

1

TP611

1

TP610

1

TP_DUT_SCLK1

TP_DUT_CSB

1

TP609

1

TP608

1

TP607

1

TP606

1

TP605

R628

R627

B9B8B7B6B5B4B3B2

B10

B1

P602

A9A8A7A6A5A4A3A2

A10

A1

P602

C9C8C7C6C5C4C3C2

C10

C1

P602

D9D8D7D6D5D4D3D2

D10

D1

P602

BG9BG8BG7BG6BG5BG4BG3BG2

BG10

BG1

P602

DG9DG8DG7DG6DG5DG4DG3DG2

DG10

DG1

P602

R606

R616

R608

B9B8B7B6B5B4B3B2

B10

B1

P601

A9A8A7A6A5A4A3A2

A10

A1

P601

D9D8D7D6D5D4D3D2

D10

D1

P601

C9C8C7C6C5C4C3C2

C10

C1

P601

DG9DG8DG7DG6DG5DG4DG3DG2

DG10

DG1

P601

BG9BG8BG7BG6BG5BG4BG3BG2

BG10

BG1

P601

R613

R609

R605

R603

R626

4

6

5

2

3

1

U602

42

1

3

U603

79

10

8

U603

14

12

11

13

U603

R615

1719

20

18

U603

5

16

15 6

U603

R602

R612

R611

R601

R610

4

6

5

2

3

1

U601

D2/D3+

DNI

D6/D7-

D10/D11-D4/D5+

D10/D11-

100

D12/D13+

D12/D13-

D12/D13-

D12/D13+

D8/D9+

D10/D11+D6/D7+

D10/D11+

D0/D1-D4/D5-D8/D9-

D8/D9-D8/D9+

D4/D5+D0/D1+

D6/D7+

D6/D7-

D4/D5-

100

100 DNI

100

DCO-

D2/D3-D2/D3+D2/D3-

100

DNI

DCO+

100

D0/D1-D0/D1+

DNI

10K

3P3V_DIGITAL

1.1K

CYP_SDIO

KP_VDDIO

DNI

3P3V_DIGITAL

0.1UF

DNI

00

ADG734BRUZ

DCO+DNI

DNI

DNI

CYP_SDO

DNI

0

DNI

DNI

DNI

CYP_SCLK

10K

1.1K

CYP_CSB

100K

DNI

DNI

DRVDD

10K

1.1K

DNI

USB_CSB2

10K

DUT_SDIOCYP_SDI

6469169-1

0

0

NC7WZ16P6X

CYP_CSBCYP_CSB2

DNI

FPGA_SCLKDUT_CSB

DNI

ADG734BRUZ

DNI DNI

ADG734BRUZ

10K

FAST_SPI_EN

DNI

DUT_SCLK

ADG734BRUZ

DNI

FAST_SPI_EN

ADG734BRUZ

3P3V_DIGITAL

DRVDD

DRVDD0.1UF

DRVDD

NC7WZ07P6X

FPGA_CSB100K

DCO-

DNI

DNI100

100

DNI

DNI

DNI

0.1UF

DNI0.1UF

100K

CYP_CSB2

3P3V_DIGITAL

DNI

10K

FAST_SPI_ENCYP_SDOCYP_SDI

CYP_SCLKFPGA_SCLKFPGA_CSB

FPGA_SDIO

FPGA_SDIO

Y2

Y1

A2

A1

GND

VCCSB

D

IN

SB

D

IN

SB

D

IN

SB

D

IN

VSS

GND

NC15

VDD

PLUG HEADER

PLUG HEADER

PLUG HEADER

PLUG HEADER

PLUG HEADER

PLUG HEADER

PLUG HEADER

PLUG HEADER

PLUG HEADER

PLUG HEADER

PLUG HEADER

PLUG HEADER

VCC

Y1A1

A2

GND

Y2

1059

3-02

4

Figure 23. SPI Configuration Circuit and FIFO Board Connector Circuit



1059

3-02

5

Figure 24. Top Side

1059

3-02

6

Figure 25. Ground Plane (Layer 2)



1059

3-02

7

Figure 26. Power Plane (Layer 3)

1059

3-02

8

Figure 27. Power Plane (Layer 4)



1059

3-02

9

Figure 28. Ground Plane (Layer 5)

1059

3-03

0

Figure 29. Bottom Side



ORDERING INFORMATION BILL OF MATERIALS

Table 1. AD9642/AD9634/AD6672 Bill of Materials Item Qty Reference Designator Description Manufacturer/Part No. 1 1 N/A Printed circuit board, AD9642 engineering

board AD9642EE01A

2 13 C101, C103, C105, C109 to C113, C514 to C516, C520, C521

0.1 µF capacitor ceramic X5R 0201 Murata GRM033R60J104KE19D

3 6 C107, C117, C118, C121, C122, C212 1 µF capacitor mono ceramic 0402 Murata GRM155R60J105KE19D 4 6 C201, C232, C234, C236, C240, C405 10 µF capacitor tantalum AVX TAJA106K010RNJ 5 10 C204, C206, C207, C209, C225,

C227, C228, C230, C241, C243 4.7 µF capacitor monolithic ceramic X5R Murata GRM188R60J475KE19

6 6 C210, C211, C220, C221, C223, C224 22 µF capacitor ceramic chip Murata GRM21BR60J226ME39L 7 1 C213 2200 pF capacitor ceramic X7R 0402 Phycomp (YAGEO)

CC0402KRX7R9BB222 8 2 C214, C216 100 pF capacitor chip mono ceramic C0G

0402 Murata GRM1555C1H101JD01D

9 1 C215 1500 pF capacitor ceramic X7R 0402 Murata GRM155R71H152KA01D 10 4 C217, C218, C226, C229 0.01 µF capacitor ceramic X7R 0402 Murata GRM155R71H103KA01D 11 36 C231, C233, C235, C239, C301,

C305, C306, C401 to C404, C501, C502, C504 to C507, C517 to C519, C535 to C548, C601, C604

0.1 µF capacitor ceramic X7R 0402 Murata GRM155R71C104KA88D

12 3 C302 to C304 3.9 pF capacitor ceramic NP0 0402 Murata GRM1555C1H3R9CZ01D 13 2 C503, C508 0.33 µF capacitor ceramic X5R Murata GRM155R61A334KE15D 14 2 C509, C510 0.001 µF capacitor ceramic monolithic Murata GRM155R71H102KA01D 15 3 C511 to C513 0.47 µF capacitor chip CER X7R 0603 Murata GCM188R71C474KA55D 16 3 C523, C532, C533 390 pF capacitor ceramic C0G 0402 Murata GRM1555C1H391JA01D 17 6 C524 to C527, C530, C534 10 µF capacitor ceramic monolithic Murata GRM21BR61C106KE15L 18 1 C531 12 pF capacitor ceramic C0G 0402 Murata GRM1555C1H120JZ01D 19 1 CR201 S1AB-13 diode rectifier GPP SMD Diode Incorp S1AB-13 20 1 CR202 SK33A-TP diode Schottky 3-amp rectifier MCC SK33A-TP 21 3 CR204 to CR206 S2A-TP diode recovery rectifier MICRO Commercial Components CORP

S2A-TP 22 2 CR501, CR502 LNJ314G8TRA (green) LED green surface

mount Panasonic LNJ314G8TRA

23 1 CR503 HSMS-2812BLK diode Schottky dual series Avago HSMS-2812BLK 24 13 E202, E204, E205, E207 to E214,

E216, E217 100 MHZ inductor ferrite bead Panasonic EXC-ML20A390U

25 2 E501, E502 45 Ω chip bead core Panasonic EXCCL3225U1 26 1 F201 1.1 A fuse poly-switch PTC device 1812 TYCO Electronics NANOSMDC110F-2 27 1 FL201 BNX016-01 FLTR noise suppression LC

combined type Murata BNX016-01

28 2 J301, J506 SMA-J-P-X-ST-EM1 CONN-PCB SMA ST edge mount

Samtec SMA-J-P-X-ST-EM1

29 2 JP201, JP203 0 Ω resistor JMPR SMD 0805 (SHRT) Panasonic ERJ-6GEYJ0.0 30 6 L501 to L506 1 µH inductor SMT power Coil-Craft ME3220-102MLB 31 1 L507 3.9 nH inductor SM Murata LQG15HN3N9S02D 32 8 P104 to P110, P401 TSW-102-08-G-S CONN-PCB header

2 POS Samtec TSW-102-08-G-S

33 1 P201 PJ-202A CONN-PCB DC power jack SM CUI Stack PJ-202A 34 1 P202 Z5.531.3625.0 CONN-PCB header

6-position Wieland Z5.531.3625.0

35 1 P203 Z5.531.3425.0 CONN-PCB, pluggable header

Wieland Z5.531.3425.0







Item Qty Reference Designator Description Manufacturer/Part No. 36 2 P601, P602 6469169-1 CONN_PCB 60PIN RA connector TYCO 6469169-1 37 1 R201 261 resistor film chip thick NIC COMP CORP NRC06F2610TRF 38 2 R205, R222 1.00 kΩ resistor precision thick film chip

R0402 Panasonic ERJ-2RKF1001X

39 1 R206 10 Ω resistor precision thick film chip R0402 Panasonic ERJ-2RKF10R0X 40 5 R207, R208, R602, R611, R612 100 kΩ resistor precision thick film chip


41 1 R209 27 kΩ resistor chip SMD 0402 Panasonic ERJ-2RKF2702X 42 1 R210 4.64 Ω resistor precision thick film chip


43 2 R211, R212 15 kΩ resistor chip SMD 0402 Panasonic ERJ-2RKF1502X 44 1 R213 13 kΩ resistor film SMD 0402 Yageo 9C04021A1302FLHF3 45 1 R214 10.5 kΩ resistor precision thick film chip


46 14 R217, R219, R302, R303, R307, R319, R320, R404, R405, R506, R522, R523, R528, R537

0 Ω resistor film SMD 0402 Panasonic ERJ-2GE0R00X

47 2 R313, R314 36 Ω resistor film SMD 0402 Panasonic ERJ-2GEJ360X 48 2 R315, R316 15 Ω resistor film SMD 0402 Panasonic ERJ-2RFK15R0X 49 6 R317, R318, R501, R503, R505, R604 49.9 Ω resistor precision thick film chip

R0402 Panasonic ERJ-2RKF49R9X

50 2 R401, R402 40.2 Ω resistor precision thick film chip R0402

Panasonic ERJ-2RKF40R2X

51 4 R407, R603, R605, R626 1.1 kΩ resistor film SMD 0402 Panasonic ERJ-2GEJ112X 52 1 R507 TBD0402 do not install (TBD_R0402) TBD0402 53 10 R509, R515 to R519, R601, R609,

R610, R615 10 kΩ resistor precision thick film chip R0402

Panasonic ERJ-2RKF1002X

54 13 R510, R511, R524 to R527, R531, R532, R535, R536, R544 to R546

100 Ω resistor precision thick film chip R0201

Panasonic ERJ-1GEF1000C

55 2 R513, R514 200 Ω resistor precision thick film chip R0402

Panasonic ERJ-2RKF2000X

56 4 R606, R613, R616, R628 0 Ω resistor thick film chip Multicomp 0402WGF0000TCE 57 5 T302, T303, T401, T501, T503 MABA-007159-000000 XFMR RF 1:1 MACOM MABA-007159-000000 58 1 U1010 SG-MLF32A-7004 socket 32P MLF direct

mount Ironwood Electronics SG-MLF32A-7004

59 2 U202, U203 ADP150AUJZ-3.3-R7 IC CMOS linear regulator LDO 3.3 V

Analog Devices ADP150AUJZ-3.3-R7

60 2 U204, U205 ADP1706ARDZ-1.8-R7 IC low dropout CMOS linear regulator

Analog Devices ADP1706ARDZ-1.8-R7

61 1 U206 ADP2114 IC dual configurable synchronous PWM step-down regulator

Analog Devices ADP2114

62 1 U207 ADP150AUJZ-1.8-R7 IC CMOS linear regulator LDO 1.8 V

Analog Devices ADP150AUJZ-1.8-R7

63 2 U300, U602 NC7WZ16P6X IC tiny logic UHS dual buffer Fairchild NC7WZ16P6X 64 1 U401 ADL5562 IC 2.6 GHZ ultralow distortion

DIFF IF/RF amp Analog Devices ADL5562

65 1 U601 NC7WZ07P6X IC tiny logic UHS dual buffer Fairchild NC7WZ07P6X 66 1 C602 0.1 µF capacitor ceramic X7R 0402 Murata GRM155R71C104KA88D 67 1 CR203 LNJ314G8TRA (green) LED green surface

mount Panasonic LNJ314G8TRA

68 1 R502 1 kΩ resistor ultraprecision ultrareliability MF chip

SUSUMU RG1005P-102-B-T5

69 2 R539, R540 33 Ω resistor high PRES, high stability Yageo RT0402DRE0733RL 70 1 U501 AD9523 IC Analog Devices AD9523 711 C205, C208, C242 0.01 µF capacitor ceramic X7R 0402 Murata GRM155R71H103KA01D 721 C219, C222 TBD0603 do not install (TBD_C0603) TBD0603


http://www.analog.com/adp150?doc=UG-386.pdf













Item Qty Reference Designator Description Manufacturer/Part No. 731 C314, C406 to C408, C529, C603 0.1 µF capacitor ceramic X7R 0402 Murata GRM155R71C104KA88D 741 C409, C410 5 pF capacitor Panasonic ECU-E1H050CCQ 751 C522 390 pF capacitor ceramic C0G 0402 Murata GRM1555C1H391JA01D 761 E203, E206 100 MHZ inductor ferrite bead Panasonic EXC-ML20A390U 771 J302, J502, J503, J505 SMA-J-P-X-ST-EM1 CONN-PCB SMA ST edge

mount Samtec SMA-J-P-X-ST-EM1

781 L201, L202 2.2 µH inductor SM Toko FDV0630-2R2M 791 L301, L405, L406 82 nH inductor SM Murata LQW18AN82NG00D 801 L401 to L404 120 nH inductor SM Panasonic ELJ-RER12JF3 811 R204, R216, R218, R221, R305, R306,

R308 to R312, R403, R406, R408, R409, R412, R508, R533, R534, R538, R541, R542, R608

0 Ω resistor film SMD 0402 Panasonic ERJ-2GE0R00X

821 R215, R220 TBD0603 do not install (TBD_R0603) TBD0603 831 R301, R304, R520, R521, R529, R530 49.9 Ω resistor PREC thick film chip R0402 Panasonic ERJ-2RKF49R9X 841 R410, R411 1.00 kΩ resistor PREC thick film chip R0402 Panasonic ERJ-2RKF1001X 851 R512, R633, R635 to R637, R643 to

R646 100 Ω resistor PREC thick film chip R0201 Panasonic ERJ-1GEF1000C

861 R543 100 Ω resistor film SMD 0402 Venkel CR0402-16W-1000FPT 871 R627, R629 10 kΩ resistor PREC thick film chip R0402 Panasonic ERJ-2RKF1002X 881 T301, T502 ADT1-1WT+ XFMR RF Mini Circuits ADT1-1WT+ 891 U603 Quad SPDT switches IC CMOS Analog Devices ADG734BRUZ 901 Y501 60 MHz to 800 MHz IC oscillator voltage

controlled OSC Epson Toyocom TCO-2111

1 Do not install.

RELATED LINKS Resource Description AD6672 Product Page, 11-Bit, 250 MSPS, 1.8 V IF Diversity Receiver AD9634 Product Page, 12-bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC) AD9642 Product Page, 14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC) ADP2114 Product Page, Configurable, Dual 2 A/Single 4 A, Synchronous Step-Down DC-to-DC Regulator AD9523 Product Page, 14-Output, Low Jitter Clock generator ADG734 Product Page, CMOS, 2.5 Ω Low Voltage, Quad SPDT Switch AN-878 Application Note, High Speed ADC SPI Control Software AN-877 Application Note, Interfacing to High Speed ADCs via SPI AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation AN-905 Application Note, VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual


http://www.analog.com/adg734?doc=UG-386.pdf


http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9272/products/product.html





http://www.analog.com/adg734?doc=UG-386.pdf






NOTES



NOTES

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

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