AD6645 14-Bit, 80 MSPS/105 MSPS A/D Converter … · 14-Bit, 80 MSPS/105 MSPS A/D Converter AD6645 Rev. D ... Last Content Update: 11/01/2016 ... Defined Radio Design Resources ...

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14-Bit, 80 MSPS/105 MSPSA/D Converter

AD6645

Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.

FEATURES SNR = 75 dB, fIN 15 MHz, up to 105 MSPS SNR = 72 dB, fIN 200 MHz, up to 105 MSPS SFDR = 89 dBc, fIN 70 MHz, up to 105 MSPS 100 dBFS multitone SFDR IF sampling to 200 MHz Sampling jitter: 0.1 ps 1.5 W power dissipation Differential analog inputs Pin compatible to AD6644 Twos complement digital output format 3.3 V CMOS compatible Data-ready for output latching

APPLICATIONS Multichannel, multimode receivers Base station infrastructures AMPS, IS-136, CDMA, GSM, W-CDMA Single channel digital receivers Antenna array processing Communications instrumentation Radars, infrared imaging Instrumentation

GENERAL DESCRIPTION The AD6645 is a high speed, high performance, monolithic 14-bit analog-to-digital converter (ADC). All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The AD6645 provides CMOS-compatible digital outputs. It is the fourth

generation in a wideband ADC family, preceded by the AD9042 (12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS, IF sampling), and the AD6644 (14-bit, 40 MSPS/65 MSPS).

Designed for multichannel, multimode receivers, the AD6645 is part of the Analog Devices, Inc., SoftCell® transceiver chipset. The AD6645 maintains 100 dB multitone, spurious-free dynamic range (SFDR) through the second Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio (SNR) is 74.5 dB through the first Nyquist band.

The AD6645 is built on the Analog Devices extra fast complementary bipolar (XFCB) process and uses an innovative, multipass circuit architecture. Units are available in thermally enhanced 52-lead PowerQuad 4 (LQFP_PQ4) and 52-lead exposed pad (TQFP_EP) packages specified from −40°C to +85°C at 80 MSPS and −10°C to +85°C at 105 MSPS.

PRODUCT HIGHLIGHTS 1. IF Sampling. The AD6645 maintains outstanding ac

performance up to input frequencies of 200 MHz, suitable for multicarrier 3G wideband cellular IF sampling receivers.

2. Pin Compatibility. The ADC has the same footprint and pin layout as the AD6644 14-bit, 40 MSPS/65 MSPS ADC.

3. SFDR Performance and Oversampling. Multitone SFDR performance of 100 dBFS can reduce the requirements of high end RF components and allows the use of receive signal processors, such as the AD6620, AD6624/AD6624A, or AD6636.

FUNCTIONAL BLOCK DIAGRAM

5

6

5

AD6645

AIN

AIN

VREF

ENCODE

ENCODE

GND DMID OVR DRY D13MSB

D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0LSB

ADC3TH5TH4

DAC2ADC2

TH3A2

DAC1

DIGITAL ERROR CORRECTION LOGIC

TH2

ADC1

TH1A1

2.4V

INTERNALTIMING

DVCCAVCC

0264

7-00

1

Figure 1.

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AD6645* Product Page Quick LinksLast Content Update: 11/01/2016

Comparable PartsView a parametric search of comparable parts

Evaluation Kits• AD6645 Evaluation Board

DocumentationApplication Notes• AN-1142: Techniques for High Speed ADC PCB Layout• AN-282: Fundamentals of Sampled Data Systems• AN-345: Grounding for Low-and-High-Frequency Circuits• AN-501: Aperture Uncertainty and ADC System

Performance• AN-586: LVDS Outputs for High Speed A/D Converters• AN-715: A First Approach to IBIS Models: What They Are

and How They Are Generated• AN-737: How ADIsimADC Models an ADC• AN-741: Little Known Characteristics of Phase Noise• AN-756: Sampled Systems and the Effects of Clock Phase

Noise and Jitter• AN-807: Multicarrier WCDMA Feasibility• AN-808: Multicarrier CDMA2000 Feasibility• AN-835: Understanding High Speed ADC Testing and

Evaluation• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual• AN-935: Designing an ADC Transformer-Coupled Front

EndData Sheet• AD6645: 14-Bit, 80 MSPS/105 MSPS A/D Converter Data

Sheet

Software and Systems Requirements• Military Part Cross-Reference Guide• Military Products by Function• Military Products by GENERIC Part Number

Tools and Simulations• Visual Analog• AD6645 IBIS Models

Reference Designs• CN0109

Reference MaterialsCustomer Case Studies• Ball Aerospace Case StudyTechnical Articles• Buffer Adapts Single-ended Signals for Differential Inputs• Cascaded Transformers Achieve Better Frequency

Performance in High-Speed ADC• Converters for 3G are Optimized for Cost, Size and Power• Correlating High-Speed ADC Performance to Multicarrier

3G Requirements• DNL and Some of its Effects on Converter Performance• MS-2210: Designing Power Supplies for High Speed ADC• MS-2735: Maximizing the Dynamic Range of Software-

Defined Radio

Design Resources• AD6645 Material Declaration• PCN-PDN Information• Quality And Reliability• Symbols and Footprints

DiscussionsView all AD6645 EngineerZone Discussions

Sample and BuyVisit the product page to see pricing options

Technical SupportSubmit a technical question or find your regional support number

* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified.

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AD6645

Rev. D | Page 2 of 24

TABLE OF CONTENTS Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

DC Specifications ......................................................................... 3

Digital Specifications ................................................................... 4

AC Specifications .......................................................................... 4

Switching Specifications .............................................................. 5

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

Explanation of Test Levels ............................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions ..............................8

Typical Performance Characteristics ..............................................9

Equivalent Circuits ......................................................................... 14

Terminology .................................................................................... 15

Theory of Operation ...................................................................... 17

Applying the AD6645 ................................................................ 17

Layout Information ........................................................................ 19

Jitter Considerations .................................................................. 19

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY 10/08—Rev. C to Rev. D Added TQFP_EP Package ............................................ Throughout Renamed Thermal Characteristics Section Thermal Resistance Section ................................................................................................ 7 Added Table 6; Renumbered Sequentially .................................... 7 Moved Equivalent Circuits Section .............................................. 14 Moved Terminology Section ......................................................... 15 Changes to Table 9 .......................................................................... 20 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 12/06—Rev. B to Rev. C Updated Format .................................................................. Universal Changes to Specifications ................................................................ 3 Changes to Jitter Considerations Section .................................... 19 Changes to Table 8, Bill of Materials ............................................ 20 Changes to Figure 43, Evaluation Board Schematic .................. 21 Changes to Figure 44 and Figure 46 ............................................. 22 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23

7/03—Rev. A to Rev. B. Changes to Title ................................................................................ 1 Changes to Features .......................................................................... 1 Changes to Product Description ..................................................... 1 Changes to Specifications ................................................................. 3 Changes to Absolute Maximum Ratings ........................................ 7 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 20 6/02—Rev. 0 to Rev. A. Change to DC Specifications ........................................................... 3

Page 4

AD6645

Rev. D | Page 3 of 24

SPECIFICATIONS DC SPECIFICATIONS AVCC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted.

Table 1. AD6645ASQ-80/AD6645ASV-80 AD6645ASQ-105/AD6645ASV-105 Parameter Temp Test Level Min Typ Max Min Typ Max Unit RESOLUTION 14 14 Bits ACCURACY

No Missing Codes Full II Guaranteed Guaranteed Offset Error Full II −10 +1.2 +10 −10 +1.2 +10 mV Gain Error Full II −10 0 +10 −10 0 +10 % FS Differential Nonlinearity (DNL) Full II −1.0 ±0.25 +1.5 −1.0 ±0.5 +1.5 LSB Integral Nonlinearity (INL) Full V ±0.5 ±1.5 LSB

TEMPERATURE DRIFT Offset Error Full V 1.5 1.5 ppm/°C Gain Error Full V 48 48 ppm/°C

POWER SUPPLY REJECTION RATIO (PSRR)

25°C V ±1.0 ±1.0 mV/V

REFERENCE OUT (VREF)1 Full V 2.4 2.4 V ANALOG INPUTS (AIN, AIN)

Differential Input Voltage Range Full V 2.2 2.2 V p-p Differential Input Resistance Full V 1 1 kΩ Differential Input Capacitance 25°C 1.5 1.5 pF

POWER SUPPLY Supply Voltages

AVCC Full II 4.75 5.0 5.25 4.75 5.0 5.25 V DVCC Full II 3.0 3.3 3.6 3.0 3.3 3.6 V

Supply Current IAVCC (AVCC = 5.0 V) Full II 275 320 275 320 mA IDVCC (DVCC = 3.3 V) Full II 32 45 32 45 mA

Rise Time2 AVCC Full IV 250 5.0 250 ms

POWER CONSUMPTION Full II 1.5 1.75 1.5 1.75 W 1 VREF is provided for setting the common-mode offset of a differential amplifier, such as the AD8138, when a dc-coupled analog input is required. VREF should be

buffered if used to drive additional circuit functions. 2 Specified for dc supplies with linear rise time characteristics.

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AD6645

Rev. D | Page 4 of 24

DIGITAL SPECIFICATIONS AVCC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted.

Table 2. Test AD6645ASQ-80/AD6645ASV-80 AD6645ASQ-105/AD6645ASV-105 Parameter Temp Level Min Typ Max Min Typ Max Unit ENCODE INPUTS (ENCODE, ENCODE)

Differential Input Voltage1 Full IV 0.4 0.4 V p-p Differential Input Resistance 25°C V 10 10 kΩ Differential Input Capacitance 25°C V 2.5 2.5 pF

LOGIC OUTPUTS (D13 to D0, DRY, OVR) Logic Compatibility CMOS CMOS Logic 1 Voltage (DVCC = 3.3 V)2 Full II 2.85 DVCC − 2 2.85 DVCC − 2 V Logic 0 Voltage (DVCC = 3.3 V)2

Full II 0.2 0.5 0.2 0.5 V Output Coding Twos complement Twos complement DMID Full V DVCC/2 DVCC/2 V

1 All ac specifications tested by driving ENCODE and ENCODE differentially. 2 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrades performance.

AC SPECIFICATIONS

All ac specifications tested by driving ENCODE and ENCODE differentially. AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, unless otherwise noted.

Table 3.

Test AD6645ASQ-80/ AD6645ASV-80

AD6645ASQ-105/ AD6645ASV-105

Parameter Temp Level Min Typ Max Min Typ Max Unit Conditions SNR

Analog Input @ −1 dBFS 25°C V 75.0 75.0 dB At 15.5 MHz Full II 72.5 74.5 dB At 30.5 MHz 25°C I 72.5 74.5 dB At 37.7 MHz Full II 72.0 73.5 72.0 73.5 dB At 70.0 MHz 25°C V 73.0 73.0 dB At 150.0 MHz 25°C V 72.0 72.0 dB At 200.0 MHz SINAD

Analog Input @ −1 dBFS 25°C V 75.0 75.0 dB At 15.5 MHz Full II 72.5 74.5 dB At 30.5 MHz 25°C I 72.5 74.5 dB At 37.7 MHz Full V 73.0 73.0 dB At 70.0 MHz 25°C V 68.5 67.5 dB At 150.0 MHz 25°C V 62.5 62.5 dB At 200.0 MHz WORST HARMONIC (SECOND OR THIRD)

Analog Input @ −1 dBFS 25°C V 93.0 93.1 dBc At 15.5 MHz Full II 85.0 93.0 dBc At 30.5 MHz 25°C I 85.0 93.0 dBc At 37.7 MHz Full V 89.0 87.0 dBc At 70.0 MHz 25°C V 70.0 70.0 dBc At 150.0 MHz 25°C V 63.5 63.5 dBc At 200.0 MHz

Page 6

AD6645

Rev. D | Page 5 of 24

Test AD6645ASQ-80/ AD6645ASV-80

AD6645ASQ-105/ AD6645ASV-105

Parameter Temp Level Min Typ Max Min Typ Max Unit Conditions WORST HARMONIC (FOURTH OR HIGHER)

Analog Input @ −1 dBFS 25°C V 96.0 96.0 dBc At 15.5 MHz Full II 85.0 95.0 dBc At 30.5 MHz 25°C I 86.0 95.0 dBc At 37.7 MHz Full V 90.0 90.0 dBc At 70.0 MHz 25°C V 90.0 90.0 dBc At 150.0 MHz 25°C V 88.0 88.0 dBc At 200.0 MHz TWO-TONE SFDR 25°C V 100 98.0 dBFS At 30.5 MHz1, 2

25°C V 100 98.0 dBFS At 55.0 MHz1, 3

25°C V 98.0 dBFS At 70.0 MHz1, 4

TWO-TONE IMD REJECTION2, 3

F1, F2 @ −7 dBFS 25°C V 90 90 dBc ANALOG INPUT BANDWIDTH 25°C V 270 270 MHz 1 Analog input signal power swept from −10 dBFS to −100 dBFS. 2 F1 = 30.5 MHz, F2 = 31.5 MHz. 3 F1 = 55.25 MHz, F2 = 56.25 MHz. 4 F1 = 69.1 MHz, F2 = 71.1 MHz.

SWITCHING SPECIFICATIONS

AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, unless otherwise noted.

Table 4.

Test AD6645ASQ-80/ AD6645ASV-80

AD6645ASQ-105/ AD6645ASV-105

Parameter Symbol Temp Level Min Typ Max Min Typ Max Unit ENCODE INPUT PARAMETERS1

Maximum Conversion Rate Full II 80 105 MSPS Minimum Conversion Rate Full IV 30 30 MSPS ENCODE Pulse Width High, tENCH

2 Full IV 5.625 4.286 ns Full V 6.25 4.75 ns ENCODE Pulse Width Low, tENCL

2 Full IV 5.625 4.286 ns

Full V 6.25 4.75 ns ENCODE Period1

tENC Full V 12.5 9.5 ns ENCODE/DATA-READY

ENCODE Rising to Data-Ready Falling tDR Full V 1.0 2.0 3.1 1.0 2.0 3.1 ns ENCODE Rising to Data-Ready Rising tE_DR Full V tENCH + tDR tENCH + tDR ns 50% Duty Cycle Full V 7.3 8.3 9.4 5.7 6.75 7.9 ns

ENCODE/DATA (D13:0), OVR ENCODE to DATA Falling Low tE_FL Full V 2.4 4.7 7.0 2.4 4.7 7.0 ns ENCODE to DATA Rising Low3 tE_RL Full V 1.4 3.0 4.7 1.4 3.0 4.7 ns ENCODE to DATA Delay3 (Hold Time) tH_E Full V 1.4 3.0 4.7 1.4 3.0 4.7 ns ENCODE to DATA Delay (Setup Time) tS_E Full V tENC −

tE_FL(max) tENC −

tE_FL(max) ns

tENC − tE_FL(typ)

tENC − tE_FL(typ)

ns

tENC − tE_FL(min)

tENC − tE_FL(min)

ns

50% Duty Cycle Full V 5.3 7.6 10.0 2.3 4.8 7.0 ns

Page 7

AD6645

Rev. D | Page 6 of 24

Test AD6645ASQ-80/ AD6645ASV-80

AD6645ASQ-105/ AD6645ASV-105

Parameter Symbol Temp Level Min Typ Max Min Typ Max Unit DATA-READY (DRY4)/DATA(D13:0),, OVR

Data-Ready to DATA Delay (Hold Time) tH_DR Full V Note 55 Note 55

50% Duty Cycle Full V 6.6 7.2 7.9 5.1 5.7 6.4 ns Data-Ready to DATA Delay (Setup Time) tS_DR Full V Note 55

Note 55 50% Duty Cycle Full V 2.1 3.6 5.1 0.6 2.1 3.5 ns

APERTURE DELAY tA 25°C V −500 −500 ps APERTURE UNCERTAINTY (JITTER) tJ 25°C V 0.1 0.1 ps rms 1 Several timing parameters are a function of tENC and tENCH. 2 Several timing parameters are a function of tENCL and tENCH. 3 ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the ADC, tE_RL = tH_E. 4 DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY. 5 Data-ready to DATA Delay (tH_DR and tS_DR) is calculated relative to rated speed grade and is dependent on tENC and duty cycle.

tS_DR

tA

AIN

N

N + 1

N + 2

N + 3

N + 4tENCtENCH tENCL

tE_FLtE_RL tE_DR tS_E tH_E

tDR

tH_DR

NN – 1N – 3D[13:0], OVR

DRY

N + 4N + 3N + 2N + 1NENCODE,ENCODE

N – 2

2647

-002

0 Figure 2. Timing Diagram

Page 8

AD6645

Rev. D | Page 7 of 24

ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Electrical

AVCC Voltage 0 V to 7 V DVCC Voltage 0 V to 7 V Analog Input Voltage 0 V to AVCC Analog Input Current 25 mA Digital Input Voltage 0 V to AVCC Digital Output Current 4 mA

Environmental Operating Temperature Range (Ambient)

AD6645-80 −40°C to +85°C AD6645-105 −10°C to +85°C

Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Storage Temperature Range (Ambient) −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE The heat sink of the AD6645ASVZ, 52-lead TQFP_EP (SV-52-1) package must be soldered to the PCB GND plane to meet thermal specifications.

Table 6. Thermal Characteristics Package Type Rating 52-Lead TQFP_EP

θJA (0 m/sec airflow)1, 2, 3 23°C/W, soldered heat sink θJMA (1.0 m/sec airflow)2, 3, 4, 5 17°C/W, soldered heat sink θJC

6, 7 2°C/W, soldered heat sink 52-Lead LQFP_PQ4

θJA (0 m/sec airflow)1, 2, 3 30°C/W, unsoldered heat sink θJMA (1.0 m/sec airflow)2, 3, 4, 5 24°C/W, unsoldered heat sink θJA (0 m/sec airflow)1, 2, 3 23°C/W, soldered heat sink θJMA (1.0 m/sec airflow)2, 3, 4, 5 17°C/W, soldered heat sink θJC

6, 7 2°C/W 1 Per JEDEC JESD51-2 (heat sink soldered to PCB). 2 2S2P JEDEC test board. 3 Values of θJA are provided for package comparison and PCB design

considerations. 4 Per JEDEC JESD51-6 (heat sink soldered to PCB). 5 Airflow increases heat dissipation, effectively reducing θJA. Furthermore, the

more metal that is directly in contact with the package leads from metal traces, throughholes, ground, and power planes, the more θJA is reduced.

6 Per MIL-STD-883, Method 1012.1. 7 Values of θJC are provided for package comparison and PCB design

considerations when an external heat sink is required.

Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approximation of TJ by the equation

TJ = TA + (θJA × PD)

where:

TA is the ambient temperature (°C).

PD is the power dissipation (W).

EXPLANATION OF TEST LEVELS I. 100% production tested.

II. 100% production tested at 25°C and guaranteed by design and characterization at temperature extremes.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization testing.

V. Parameter is a typical value only.

ESD CAUTION

Page 9

AD6645

Rev. D | Page 8 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES1. DNC = DO NOT CONNECT.2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND.

PIN 1IDENTIFIER

AD6645TOP VIEW

(Not to Scale)

1DVCC2GND3VREF4GND5ENCODE6ENCODE7GND8AVCC9AVCC

10GND11

14

AIN12AIN13GND

AV C

C

15

GN

D

16

AV C

C

17

GN

D

18

AV C

C

19

GN

D

20

C1

21

GN

D22

AV C

C23

GN

D24

C2

25

GN

D

26

AV C

C

27 GND

28 AVCC

29 GND

30 AVCC

31 DNC

32 OVR

33 DVCC

34 GND

35 DMID

36 D0 (LSB)

37

40

D1

38 D2

39 D3

D4

41

D5

42

GN

D

43

DV C

C

44

D6

45

D7

46

D8

47

D9

48

D10

49

D11

50

D12

51

D13

(MSB

)

52

DR

Y

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Figure 3. Pin Configuration

Table 7. Pin Function Descriptions Pin Number Mnemonic Description 1, 33, 43 DVCC 3.3 V Power Supply (Digital) Output Stage Only. 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34, 42

GND Ground.

3 VREF 2.4 V Reference. Bypass to ground with a 0.1 μF microwave chip capacitor. 5 ENCODE Encode Input. Conversion initiated on rising edge. 6 ENCODE Complement of ENCODE, Differential Input. 8, 9, 14, 16, 18, 22, 26, 28, 30 AVCC 5 V Analog Power Supply. 11 AIN Analog Input. 12 AIN Complement of AIN, Differential Analog Input.

20 C1 Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. 24 C2 Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. 31 DNC Do not connect this pin. 32 OVR Overrange Bit. A logic level high indicates analog input exceeds ±FS. 35 DMID Output Data Voltage Midpoint. Approximately equal to (DVCC)/2. 36 D0 (LSB) Digital Output Bit (Least Significant Bit); Twos Complement. 37 to 41, 44 to 50 D1 to D5, D6 to D12 Digital Output Bits in Twos Complement. 51 D13 (MSB) Digital Output Bit (Most Significant Bit); Twos Complement. 52 DRY Data-Ready Output. 53 (EPAD) Exposed Paddle (EPAD) Exposed Pad. Connect the exposed pad to GND.

Page 10

AD6645

Rev. D | Page 9 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

2

65

4

3

50 10 15 20 25 30 35 40

ENCODE = 80MSPSAIN = 2.2MHz @ –1dBFSSNR = 75.0dBSFDR = 93.0dBc

0264

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0Figure 4. Single Tone @ 2.2 MHz

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

26

5

4

3

50 10 15 20 25 30 35 40

ENCODE = 80MSPSAIN = 15.5MHz @ –1dBFSSNR = 75.0dBSFDR = 93.0dBc

0264

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Figure 5. Single Tone @ 15.5 MHz

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

2

65

4

3

50 10 15 20 25 30 35 40

ENCODE = 80MSPSAIN = 29.5MHz @ –1dBFSSNR = 74.5dBSFDR = 93.0dBc

0264

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Figure 6. Single Tone @ 29.5 MHz

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

26 5

4

3

ENCODE = 80MSPSAIN = 69.1MHz @ –1dBFSSNR = 73.5dBSFDR = 89.0dBc

50 10 15 20 25 30 35 40

0264

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Figure 7. Single Tone @ 69.1 MHz

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

2

6

54

3

ENCODE = 80MSPSAIN = 150MHz @ –1dBFSSNR = 73.0dBSFDR = 70.0dBc

50 10 15 20 25 30 35 40

0264

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4

Figure 8. Single Tone @ 150 MHz

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

2

6 54

3

ENCODE = 80MSPSAIN = 200MHz @ –1dBFSSNR = 72.0dBSFDR = 64.0dBc

50 10 15 20 25 30 35 40

0264

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5

Figure 9. Single Tone @ 200 MHz

Page 11

AD6645

Rev. D | Page 10 of 24

FREQUENCY (MHz)

SNR

(dB

)

72.0

72.5

73.0

73.5

74.0

74.5

75.0

75.5

0 10 20 30 40 50 60 70

T = –40°C

T = +85°C

T = +25°C

ENCODE = 80MSPS @ AIN = –1dBFSTEMP = –40°C, +25°C, +85°C

0264

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6

Figure 10. Signal-to-Noise Ratio (SNR) vs. Frequency

ANALOG INPUT FREQUENCY (MHz)

WO

RST

-CA

SE H

AR

MO

NIC

(dB

c)

80

82

84

86

88

90

92

94

T = +25°C

T = –40°C, +85°C

ENCODE = 80MSPS @ AIN = –1dBFSTEMP = –40°C, +25°C, +85°C

0 10 20 30 40 50 60 70

0264

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7

Figure 11. Worst-Case Harmonics vs. Analog Input Frequency

ANALOG FREQUENCY (MHz)

SNR

(dB

)

70

71

72

73

74

75

76

0 20 40 60 80 100 120 140 160 180 200

ENCODE = 80MSPS @ AIN = –1dBFSTEMP = 25°C

0264

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8

Figure 12. Signal-to-Noise Ratio (SNR) vs. Analog Frequency (IF)

ANALOG FREQUENCY (MHz)

HA

RM

ON

ICS

(dB

c)

60

65

70

80

90

100

75

85

95

WORST OTHER SPUR

HARMONICS(SECOND, THIRD)

ENCODE = 80MSPS @ AIN = –1dBFSTEMP = 25°C

0 20 40 60 80 100 120 140 160 180 200

0264

7-01

9

Figure 13. Harmonics vs. Analog Frequency (IF)

ANALOG INPUT POWER LEVEL (dBFS)

WO

RST

-CA

SE S

PUR

IOU

S (d

BFS

AN

D d

Bc)

0

10

20

30

40

50

60

70

80

90

100

110

dBc

120

dBFS

ENCODE = 80MSPSAIN = 30.5MHz

SFDR = 90dBREFERENCE LINE

–90 –80 –70 –60 –50 –40 –30 –20 –10 0

0264

7-02

0

Figure 14. Single-Tone SFDR @ 30.5 MHz

ANALOG INPUT POWER LEVEL (dBFS)

WO

RST

CA

SE S

PUR

IOU

S (d

BFS

AN

D d

Bc)

0

10

20

30

40

50

60

70

80

90

100

110

dBc

120

dBFS

–90 –80 –70 –60 –50 –40 –30 –20 –10 0

SFDR = 90dBREFERENCE LINE

ENCODE = 80MSPSAIN = 69.1MHz

0264

7-02

1

Figure 15. Single-Tone SFDR @ 69.1 MHz

Page 12

AD6645

Rev. D | Page 11 of 24

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

2F1

– F2

2F2

+ F1

2F1

+ F2

F2 –

F1

2F2

– F1

F1 +

F2

ENCODE = 80MSPSAIN = 30.5MHz,31.5MHz (–7dBFS)NO DITHER

50 10 15 20 25 30 35 40

0264

7-02

2

Figure 16. Two-Tone SFDR @ 30.5 MHz and 31.5 MHz

INPUT POWER LEVEL (F1 = F2 dBFS)

WO

RST

-CA

SE S

PUR

IOU

S (d

BFS

AN

D d

Bc)

0

10

20

30

40

50

60

70

80

90

100

110

dBc

dBFS

SFDR = 90dBREFERENCE LINE

ENCODE = 80MSPSF1 = 30.5MHzF2 = 31.5MHz

–77 –67 –57 –47 –37 –27 –17 –7

0264

7-02

3

Figure 17. Two-Tone SFDR @ 30.5 MHz and 31.5 MHz

ENCODE FREQUENCY (MHz)

65

70

80

90

WORST SPUR @ AIN = 2.2MHz

SNR @ AIN = 2.2MHz75

85

95

100

SNR

, WO

RST

-CA

SE S

PUR

IOU

S (d

B A

ND

dB

c)

15 30 45 60 75 90 105

0264

7-02

4

Figure 18. SNR, Worst-Case Spurious vs. Encode @ 2.2 MHz

2F2

– F1

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

F1 +

F2

2F1

– F2

2F2

+ F1

2F1

+ F2

F2 –

F1

ENCODE = 80MSPSAIN = 55.25MHz,56.25MHz (–7dBFS)NO DITHER

50 10 15 20 25 30 35 40

0264

7-02

5

Figure 19. Two-Tone SFDR @ 55.25 MHz and 56.25 MHz

INPUT POWER LEVEL (F1 = F2 dBFS)

WO

RST

-CA

SE S

PUR

IOU

S (d

BFS

AN

D d

Bc)

0

10

20

30

40

50

60

70

80

90

100

110

dBc

dBFS

SFDR = 90dBREFERENCE LINE

ENCODE = 80MSPSF1 = 55.25MHzF2 = 56.25MHz

–77 –67 –57 –47 –37 –27 –17 –7

0264

7-02

6

Figure 20. Two-Tone SFDR @ 55.25 MHz and 56.25 MHz

ENCODE FREQUENCY (MHz)

65

70

80

90WORST SPUR @ AIN = 69.1MHz

SNR @ AIN = 69.1MHz75

85

95

SNR

, WO

RST

-CA

SE S

PUR

IOU

S (d

B A

ND

dB

c)

15 30 45 60 75 90 105

0264

7-02

7

Figure 21. SNR, Worst-Case Spurious vs. Encode @ 69.1 MHz

Page 13

AD6645

Rev. D | Page 12 of 24

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

53

2

64

AM

PLIT

UD

E (d

BFS

)

ENCODE = 80.0MSPSAIN = 30.5MHz @ –29.5dBFSNO DITHER

50 10 15 20 25 30 35 40

0264

7-02

8Figure 22. 1 M Sample FFT Without Dither

ANALOG INPUT LEVEL (dBFS)

0

10

20

30

40

50

60

70

80

90

100

110

WO

RST

-CA

SE S

PUR

IOU

S (d

Bc)

90 80 70 60 50 40 30 20 10 0

SFDR = 90dBREFERENCE LINE

ENCODE = 80.0MSPSAIN = 30.5MHzNO DITHER

0264

7-02

9

Figure 23. SFDR Without Dither

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

26

5

4

3

ENCODE = 76.8MSPSAIN = 69.1MHz @ –1dBFSSNR = 73.5dBSFDR = 89.0dBc

50 10 15 20 25 30 35 40

0264

7-03

0

Figure 24. Single Tone @ 69.1 MHz, Encode = 76.8 MSPS

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

5 3

26

4

AM

PLIT

UD

E (d

BFS

)

50 10 15 20 25 30 35 40

ENCODE = 80.0MSPSAIN = 30.5MHz @ –29.5dBFSWITH DITHER @ –19.2 dBm

0264

7-03

1

Figure 25. 1 M Sample FFT with Dither

ANALOG INPUT LEVEL (dBFS)

0

10

20

30

40

50

60

70

80

90

100

110

WO

RST

-CA

SE S

PUR

IOU

S (d

Bc)

–90 –80 –70 –60 –50 –40 –30 –20 –10 0

SFDR = 90dBREFERENCE LINE

SFDR = 100dBREFERENCE LINE

ENCODE = 80.0MSPSAIN = 30.5MHzWITH DITHER @ –19.2dBm

0264

7-03

2

Figure 26. SFDR with Dither

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

2 6 543

ENCODE = 76.8MSPSAIN = W-CDMA @ 69.1MHz

0 5 10 15 20 25 30 35 40

0264

7-03

3

Figure 27. W-CDMA Tone @ 69.1 MHz, Encode = 76.8 MSPS

Page 14

AD6645

Rev. D | Page 13 of 24

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

50 10 15 20 25 30 35 40

ENCODE = 76.8MSPSAIN = 2W-CDMA @ 59.6MHz

0264

7-03

4

6 5 4 2 3

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)

ENCODE = 76.8MSPSAIN = W-CDMA @ 140MHz

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

50 10 15 20 25 30 35 40

0264

7-03

6

Figure 28. Two W-CDMA Carriers @ 59.6 MHz, Encode = 76.8 MSPS

Figure 30. W-CDMA Tone @ 140 MHz, Encode = 76.8 MSPS

2 3 6 4 5

AM

PLIT

UD

E (d

BFS

)

FREQUENCY (MHz)

ENCODE = 61.44MSPSAIN = W-CDMA @ 190MHz

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0

0264

7-03

7

FREQUENCY (MHz)

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

AM

PLIT

UD

E (d

BFS

)

ENCODE = 61.44MSPSAIN = 4W-CDMA @ 46.08MHz

0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0

0264

7-03

5

Figure 31. W-CDMA Tone @ 190 MHz, Encode = 61.44 MSPS

Figure 29. Four W-CDMA Carriers @ 46.08 MHz, Encode = 61.44 MSPS

Page 15

AD6645

Rev. D | Page 14 of 24

EQUIVALENT CIRCUITS

BUF T/H

BUF

BUF T/H

500Ω

AIN

AIN

500Ω

VREF

AVCCVCH

VCLVCH AVCC

VCL 0264

7-00

4

Figure 32. Analog Input Stage

LOADS

LOADS

10kΩ

10kΩ

10kΩ

10kΩ

ENCODEENCODE

AVCC

AVCCAVCCAVCC

0264

7-00

5

Figure 33. Encode Inputs

C1, C2

AVCC

AVCC

AVCC

VREF

CURRENTMIRROR

0264

7-00

6

Figure 34. Compensation Pin, C1 or C2

DVCC

CURRENTMIRROR

D0 TO D13,OVR, DRY

DVCC

VREF

CURRENTMIRROR

0264

7-00

7

Figure 35. Digital Output Stage

2.4V

AVCCAVCC

VREF

100µA

0264

7-00

8

Figure 36. 2.4 V Reference

10kΩ

DMID

10kΩ

DVCC

0264

7-00

9

Figure 37. DMID Reference

Page 16

AD6645

Rev. D | Page 15 of 24

TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay The delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.

Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer.

Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. The peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. The peak-to-peak differential is computed by rotating the inputs’ phase 180°and taking the peak measurement again. The difference is then computed between both peak measurements.

Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step.

Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the encode pulse should be left in a high state to achieve rated performance; pulse width low is the minimum time that the encode pulse should be left in a low state. See timing implications of changing tENCH in Table 4. At a given clock rate, these specifications define an acceptable encode duty cycle.

Full-Scale Input Power The full-scale input power is expressed in dBm and can be calculated by using the following equation:

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡ −

=− 001.0

2

log10 InputZrmsScaleFullV

ScaleFullPower

Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.

Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.

Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit.

Maximum Conversion Rate The encode rate at which parametric testing is performed.

Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Noise (for Any Range Within the ADC)

⎟⎠⎞

⎜⎝⎛ −−

××=10

10001.0 dBFSdBcdBmNOISE

SignalSNRFSZV

where:

Z is the input impedance.

FS is the full scale of the device for the frequency in question.

SNR is the value for the particular input level.

Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal noise and quantiza-tion noise.

Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels.

Power Supply Rejection Ratio (PSSR) The ratio of a change in input offset voltage to a change in power supply voltage.

Power Supply Rise Time The time from when the dc supply is initiated until the supply output reaches the minimum specified operating voltage for the ADC. The dc level is measured at the supply pin(s) of the ADC.

Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.

Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.

Page 17

AD6645

Rev. D | Page 16 of 24

Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, reported in dBc.

Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product, and may be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full scale).

Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics), reported in dBc.

Page 18

AD6645

Rev. D | Page 17 of 24

THEORY OF OPERATION The AD6645 ADC employs a three-stage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size.

As shown in the functional block diagram (see Figure 1), the AD6645 has complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4 V and should swing ±0.55 V around this reference (see ). Because AIN and Figure 32 AIN are 180° out of phase, the differential analog input signal is 2.2 V p-p.

Both analog inputs are buffered prior to the first track-and-hold, TH1. The high state of the encode pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives a 5-bit digital-to-analog converter, DAC1. DAC1 requires 14 bits of precision that is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1.

The first residual signal is applied to a second conversion stage consisting of a 5-bit ADC2, a 5-bit DAC2, and a pipeline TH4. The second DAC requires 10 bits of precision, which is met by the process with no trim. The input to TH5 is a second residual signal generated by subtracting the quantized output of DAC2 from the first residual signal held by TH4. TH5 drives a final 6-bit ADC3.

The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as twos complement.

APPLYING THE AD6645 Encoding the AD6645

The AD6645 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz analog input signals when using a high jitter clock source. See the AN-501 application note, Aperture Uncertainty and ADC System Performance, for complete details.

For optimum performance, the AD6645 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias.

Figure 38 shows one preferred method for clocking the AD6645. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit excessive amplitude swings from the clock into the AD6645 to approximately 0.8 V p-p differential. This helps to prevent the large voltage swings of the clock from feeding through to other portions of the AD6645 and limits the noise presented to the encode inputs.

ENCODE

ENCODE

T1-4T

AD6645

HSMS2812DIODES

0.1µF

CLOCKSOURCE

0264

7-03

8

Figure 38. Crystal Clock Oscillator, Differential Encode

If a low jitter clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins, as shown in Figure 39. The MC100EL16 (or same family) from ON Semiconductor offers excellent jitter performance.

ENCODE

ENCODE

AD6645

VT

VT

ECL/PECL

0.1µF

0.1µF

0264

7-03

9

Figure 39. Differential ECL for Encode

Driving the Analog Inputs

As with most new high speed, high dynamic range ADCs, the analog input to the AD6645 is differential. Differential inputs improve on-chip performance as signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. Second, they provide good rejection of common-mode signals, such as local oscillator feedthrough.

The AD6645 analog input voltage range is offset from ground by 2.4 V. Each analog input connects through a 500 Ω resistor to the 2.4 V bias voltage and to the input of a differential buffer (see Figure 32). The resistor network on the input properly biases the followers for maximum linearity and range. Therefore, the analog source driving the AD6645 should be ac-coupled to the input pins. Because the differential input impedance of the AD6645 is 1 kΩ, the analog input power requirement is only −2 dBm, simplifying the driver amplifier in many cases. To take full advantage of this high input impedance, a 20:1 RF transformer is required. This is a large ratio and can result in unsatisfactory performance. In this case, a lower step-up ratio can be used. The recommended method for driving the differential analog input of the AD6645 is to use a 4:1 RF transformer. For example, if RT is set to 60.4 Ω and RS is set to 25 Ω, along with a 4:1 impedance ratio transformer, the input would match to a 50 Ω source with a full-scale drive of 4.8 dBm. Series resistors (RS) on the secondary side of the transformer should be used to isolate the transformer from the A/D.

Page 19

AD6645

Rev. D | Page 18 of 24

This limits the amount of dynamic current from the A/D flowing back into the secondary of the transformer. The 50 Ω impedance matching can also be incorporated on the secondary side of the transformer, as shown in the evaluation board schematic (see Figure 43).

AIN

AINADT4-1WT

AD6645

ANALOG INPUTSIGNAL

RS

RS

0.1µF

RT

0264

7-04

0

Figure 40. Transformer-Coupled Analog Input Circuit

In applications where dc coupling is required, a differential output op amp, such as the AD8138, can be used to drive the AD6645 (see Figure 41). The AD8138 op amp provides single-ended-to-differential conversion, which reduces overall system cost and minimizes layout requirements.

AD6645AIN

AINAD8138

5V499Ω

499Ω

499Ω

499Ω

VREF

DIGITALOUTPUTS

25Ω

25Ω

VOCM

CF

CF

VIN

0264

7-04

1

Figure 41. DC-Coupled Analog Input Circuit

Power Supplies

Care should be taken when selecting a power source. The use of linear dc supplies with rise times of <45 ms is highly recommended. Switching supplies tend to have radiated components that can be received by the AD6645. Decouple each of the power supply pins as close to the package as possible using 0.1 μF chip capacitors.

The AD6645 has separate digital and analog power supply pins. The analog supplies are AVCC and the digital supply pins are DVCC. Although analog and digital supplies can be tied together, the best performance is achieved when the supplies are separate because the fast digital output swings can couple switching currents back into the analog supplies. Note that AVCC must be held within 5% of 5 V. The AD6645 is specified for DVCC = 3.3 V, a common supply for digital ASICs.

Digital Outputs

Care must be taken when designing the data receivers for the AD6645. It is recommended that the digital outputs drive a series resistor followed by a gate, such as the 74LCX574.

To minimize capacitive loading, there should be only one gate on each output pin. An example of this is shown in the evaluation board schematic of Figure 43. The digital outputs of the AD6645 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace have a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷ 1 ns) of dynamic current per bit flow in or out of the device. A full-scale transition can cause up to 140 mA (14 bits × 10 mA/bit) of current to flow through the output stages. Place the series resistors as close to the AD6645 as possible to limit the amount of current that can flow into the output stage. These switching currents are confined between ground and DVCC. Standard TTL gates should be avoided because they can add appreciably to the dynamic switching currents of the AD6645. Note that extra capacitive loading increases output timing and invalidates timing specifications. Digital output timing is guaranteed for output loads up to 10 pF. Digital output states for given analog input levels are shown in Table 8.

Grounding

For optimum performance, it is highly recommended that a common ground be used between the analog and digital power planes. The primary concern with splitting grounds is that dynamic currents may be forced to travel significant distances in the system before recombining back at the common source ground. This can result in a large, undesirable ground loop. The most common place for this to occur is on the digital outputs of the ADC. Ground loops can contribute to digital noise being coupled back onto the ADC front end. This can manifest itself as either harmonic spurs, or very high-order spurious products that can cause excessive spikes on the noise floor. This noise coupling is less likely to occur at lower clock speeds because the digital noise has more time to settle between samples. In general, splitting the analog and digital grounds can frequently contribute to undesirable EMI-RFI and should, therefore, be avoided.

Conversely, if not properly implemented, common grounding can actually impose additional noise issues because the digital ground currents ride on top of the analog ground currents in close proximity to the ADC input. To further minimize the potential for noise coupling, it is highly recommended that multiple ground return traces/vias be placed such that the digital output currents do not flow back toward the analog front end but are routed quickly away from the ADC. This does not require a split in the ground plane and can be accomplished by simply placing substantial ground connections directly back to the supply at a point between the analog front end and the digital outputs. In addition, the judicious use of ceramic chip capacitors between the power supply and ground planes helps to suppress digital noise. The layout should incorporate enough bulk capacitance to supply the peak current requirements during switching periods.

Page 20

AD6645

Rev. D | Page 19 of 24

LAYOUT INFORMATION The schematic of the evaluation board (see Figure 43) represents a typical implementation of the AD6645. A multi-layer board is recommended to achieve best results. It is highly recommended that high quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. The pinout of the AD6645 facilitates ease of use in the implementation of high frequency, high resolution design practices. All of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes.

Care should be taken when routing the digital output traces. To prevent coupling through the digital outputs into the analog portion of the AD6645, minimal capacitive loading should be placed on these outputs. It is recommended that a fanout of only one gate should be used for all AD6645 digital outputs.

The layout of the encode circuit is equally critical. Any noise received on this circuitry results in corruption in the digitization process and lower overall performance. The encode clock must be isolated from the digital outputs and the analog inputs.

Table 8. Twos Complement Output Coding AIN Level AIN Level Output State Output Code

VREF + 0.55 V VREF − 0.55 V Positive FS 01 1111 1111 1111

VREF VREF Midscale 00 … 0/11 … 1

VREF − 0.55 V VREF + 0.55 V Negative FS 10 0000 0000 0000

JITTER CONSIDERATIONS The SNR for an ADC can be predicted. When normalized to ADC codes, the following equation accurately predicts the SNR based on three terms: jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter.

( )2/12

22

2

22

2ε1

2log20

76.1

⎥⎥

⎦

⎤

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛ ××+⎢

⎣

⎡⎟⎠⎞

⎜⎝⎛ +

+××π

−=

nrmsNOISE

nrmsjANALOG

Vtf

SNR

where:

fANALOG is the analog input frequency.

tj rms is the rms jitter of the encode (rms sum of encode source and internal encode circuitry).

ε is the average DNL of the ADC (typically 0.41 LSB).

n is the number of bits in the ADC.

VNOISE rms is the voltage rms thermal noise that refers to the analog input of the ADC (typically 0.9 LSB rms).

For a 14-bit ADC, such as the AD6645, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. Figure 42 shows a family of curves that demonstrate the expected SNR performance of the AD6645 as jitter increases. The chart is derived from the preceding equation.

For a complete discussion of aperture jitter, see the AN-756 application note, Sampled Systems and the Effects of Clock Phase Noise and Jitter. The AN-756 application note can be found on www.analog.com.

JITTER (ps)

55

SNR

(dB

FS)

60

65

70

75

80

AIN = 110MHz

AIN = 150MHz

AIN = 190MHz

AIN = 30MHz

AIN = 70MHz

0 0.1 0.2 0.3 0.4 0.5 0.6

0264

7-04

2

Figure 42. SNR vs. Jitter

Page 21

AD6645

Rev. D | Page 20 of 24

Table 9. AD6645/PCB Bill of Materials Quantity 80 MSPS

Quantity 105 MSPS Reference ID Description Manufacturer Supplier Part No.

1 1 PCB Printed circuit board, AD6645 engineering evaluation board

PCSM 6645EE01D REV D

4 4 C1, C2, C31, C38 Capacitor, tantalum, SMT BCAPTAJC, 10 μF, 16 V, 10%

Kemet T491C106K016AS

8 8 C3, C7 to C10, C16, C301, C32

Capacitor, ceramic, SMT 0508, 0.1 μF, 16 V, 10%

Presidio Components 0508X7R104K16VP3

9 9 C4, C15, C22 to C26, C29, (C33)2, 3, (C34)2, 3, C39

Capacitor, ceramic, SMT 0805, 0.1 μF, 25 V, 10%

Panasonic ECJ-2VB1E104K

0 0 (C5, C6)2, 3 Capacitor, ceramic, SMT 0805,

0.01 μF, 50 V, 10% Panasonic ECJ-2YB1H103K

10 10 C11 to C14, C17 to C21, C40

Capacitor, ceramic, SMT 0508, 0.01 μF, 50 V, 0.2%

Presidio Components 0508X7R103M2P3

0 0 (C27, C28)2 Capacitor, ceramic, SMT 0805, limits

amp bandwidth as warranted

1 1 CR13 Diode, dual Schottky HSMS2812,

SOT-23, 30 V, 20 mA Panasonic MA716-(TX)

1 1 E1 Install jumper wire (across OPT_LAT and BUFLAT)

5 5 F1 to F5 EMI suppression ferrite chip, SMT 0805 Steward HZ0805E601R-00 1 1 J1 Header, 6-pin, pin strip, 5 mm pitch Wieland Z5.530.0625.0 1 1 J1 Pin strip, 6-pin, 5 mm pitch Wieland 25.602.2653.0 1 1 J2 Header, 40-pin, male, right angle Samtec TSW-120-08-T-D-RA 2 2 (J3)2, J4, J5 Connector, gold, female, coax., SMA,

vertical Johnson Components 142-0701-201

1 1 L1 Inductor, SMT, 1008-ct package, 4.7 nH Coilcraft 1008CT-040X-J 0 0 (R1)2, 3

Resistor, thick film, SMT 0402, 100 Ω, 1/16 W, 1%

Panasonic ERJ-2RKF1000

0 0 (R2)2 Resistor, thick film, SMT 1206, 60.4 Ω,

1/4 W, 1% Panasonic ERJ-8ENF60R4V

2 2 (R3 to R5)1, 2, (R8)1, 2, R9, R10

Resistor, thick film, SMT 0805, 500 Ω, 1/8 W, 1%

Panasonic ERJ-6ENF4990V

2 2 R6, R7 Resistor, thick film, SMT 0805, 25.5 Ω, 1/8 W, 1%

Panasonic ERJ-6ENF25R5V

0 0 (R11)2, 3, (R13)2, 3 Resistor, thick film, SMT 0805, 66.5 Ω,

1/8 W, 1% Panasonic ERJ-6ENF66R5V

0 0 (R12)2, 3, (R14)2, 3 Resistor, thick film, SMT 0805, 100 Ω,

1/8W, 1% Panasonic ERJ-6ENF1000V

1 1 R151 Resistor, thick film, SMT 0402, 178 Ω,

1/16 W, 1% Panasonic ERJ-2RKF1780X

1 1 R35 Resistor, thick film, SMT 0805, 49.9 Ω, 1/8 W, 1%

Panasonic ERJ-6ENF49R9V

4 4 RN1 to RN4 Resistor array, SMT 0402; 100 Ω; 8 ISO RES.,1/4 W; 5%

Panasonic EXB2HV101JV

2 2 T23, T31 Transformer, ADT4-1WT, CD542,

2 MHz to 775 MHz Mini-Circuits ADT4-1WT

1 0 U1 IC, 14-bit, 80 MSPS ADC Analog Devices AD6645ASQ/ASV-80 0 1 U1 IC, 14-bit, 105 MSPS ADC Analog Devices AD6645ASQ/ASV-105 2 2 U2, U7 IC, SOIC-20, Octal D-type flip-flop Fairchild 74LCX574WM 0 0 (U3)1, 2 IC, SOIC-8, low distortion differential

ADC driver Analog Devices AD8138AR

2 2 U4, U6 IC, SOT-23, tiny logic UHS 2 input OR gate

Fairchild NC7SZ32

Page 22

AD6645

Rev. D | Page 21 of 24

Quantity 80 MSPS

Quantity 105 MSPS Reference ID Description Manufacturer Supplier Part No.

0 0 (U8)2, 3 IC, SOIC-8, differential receiver Motorola MC100LVEL16

1 0 Y1 Clock oscillator, 80 MHz CTS Reeves MXO45-80 4 4 Y1 Pin sockets, closed end AMP/Tyco Electronics 5-330808-3 4 4 Circuit board support Richco, Inc. CBSB-14-01 1 AC-coupled AIN is standard: R3, R4, R5, R8, and U3 are not installed. If dc-coupled AIN is required, C30, R15, and T3 are not installed. 2 Reference designators in parentheses are not installed on standard units. 3 AC-coupled encode is standard: C5, C6, C33, C34, R1, R11 to R14, and U8 are not installed. If PECL encode is required, CR1 and T2 are not installed.

Page 23

AD6645

Rev. D | Page 22 of 24

0.0

74LC

X574

CP

D0 D1 D2 D3 D4 D6 D7 GND

O0 O1 O2 O3 O4 O5 O6 O7

VCC

OE D5

VEEQQ

VCC

DDNC VBB

0.0

VCC

GND

OUT

OE OE'

GND'

VCC'

OUT'

AIN

C1

C2

D0D1

D10

D11

D12

D13

D2D3D4

D5

D6

D7

D8

D9

DRY

ENC

VREF

AIN

ENC

GND

GND

GND

DVCC

AVCC

AVCC

GND

GND

AVCC

DVCCGN

D

AVCC

GND

AVCC

GND

AVCC

GND

GND

AVCC

GND

GND

AVCC

DVCC

GND

GND

GND

AVCCDN

C

OVR

DMID

GND

+V

GND

+V

HEAD

ER40

74LC

X574

CP

D0 D1 D2 D3 D4 D6 D7 GND

O0 O1 O2 O3 O4 O5 O6 O7

VCC

OE D5

DO N

OT IN

STAL

L

INST

ALL J

UMPE

R

OPTI

ONAL

(SEE

NOT

E 1)

1. R2

IS IN

STAL

LED

FOR

INPU

T M

ATCH

ING

ON T

HE P

RIMA

RY O

F T3

. R1

5 IS

NOT

INST

ALLE

D.R1

5 IS

INST

ALLE

D FO

R IN

PUT

MATC

HING

ON

THE

SECO

NDAR

Y OF

T3,

R2

IS N

OT IN

STAL

LED.

3. AC

-COU

PLED

ENC

ODE

IS S

TAND

ARD.

C5,

C6, C

33, C

34, R

1, R

11−R

14 A

ND U

8 AR

E NO

T IN

STAL

LED.

NOTE

S:

2. AC

-COU

PLED

AIN

IS S

TAND

ARD,

R3,

R4, R

5, R8

AND

U3 A

RE N

OT IN

STAL

LED.

ENC

IF D

C-CO

UPLE

D AI

N IS

REQ

UIRE

D, C

30, R

15 A

ND T

3 ARE

NOT

INST

ALLE

D.

AIN

IF P

ECL E

NCOD

E IS

REQ

UIRE

D, C

R1 A

ND T

2 ARE

NOT

INST

ALLE

D.

(SEE

NOT

E 1)

(SEE

NOT

E 2)

DC-C

OUPL

ED A

IN O

PTIO

N

80MH

z (AD

6645

)66

.66MH

z (AD

6644

)

AD66

44/A

D664

5

4:1IM

PEDA

NCE

RATI

O

4:1IM

PEDA

NCE

RATI

O

DO N

OT IN

STAL

LDC

-COU

PLED

ENC

ODE

OPTI

ON (S

EE N

OTE

3)

OPT_

CLK DO

NOT

INST

ALL

DO N

OT IN

STAL

L

J5

J3

J4

R2 60.4

7

021

1213141516171819

109865432

11

U2

1

10

1112

1314

1516

1718

19

220

2122

2324

2526

2728

29 3

30

3132

3334

3536

3738

39

440

56

78

9

J2

L1

4.7NH

1

10111213141516

2 3 4 5 6 7 89

RN4 100

1

10111213141516

2 3 4 5 6 7 89

RN3

100

1

10111213141516

2 3 4 5 6 7 89

RN2 100

1

10111213141516

2 3 4 5 6 7 89

RN1

100

1 2 3 4 5 6

J1

F1

3 1654

T2

ADT4

-1WT

+3P3

VIN

10U

C31

-5V

+3P3

V_XT

L

10U

C2

E1

E2

OVR

E6

215 3

4 NC7S

Z32

U6

4

351 2

U4

NC7S

Z32

R10

500

R9 500

C7 0.1U

C8 0.1U

2 3 4 5 6 7 8 9 10 11 12 13

4041

4244

4546

4748

4950

52

39 38 37 36 35 34 33 32 31 30 29 28 27

2625

2423

2221

2019

1817

1615

14

1

5143

U1

0.1U

C32

0.01UC5R1 100

0.01UC6

ENC

ENC

0.1U

C15

0.1U

C22

+5VA

12

F3

+3P3

V_XT

L

12

F5

14

78

1

3 5

12 10

Y1

+3P3

VD+3

P3V

PREF

C1 10U

C38

10U

0.1U

C33

0.1U

C34

F2

R13

66.5

R14

100

+5VA

R12

100

R11

66.5

0.01U

C40

C39

0.1U

3

21

CR1

0.1U

C30

C27

0.1U

C29

C4

0.1U

C3 0.1U

R8

500

R5

500

500

R3

C26

0.1U

C25

0.1U

0.1U

C24

0.1U

C23

0.01U

C14

0.01U

C13

0.01U

C12

0.01U

C11

0.1U

C10

0.1U

C9 C16

0.1U

C17

0.01U

C18

U10.0U10.0

C21

C20

0.01U

0.01U

C19

+5VA

+5V

+3P3

V

12

F4+3

P3VD

+3P3

VIN

AIN

R6 25.5

R7 25.5

+5VA

+5VA

+3P3

V

+3P3

VD

BUFL

AT

BUFL

AT

3

U3

R4

5678

321 4

U8

MC10

0LVE

L16

R15

178

+5VA

+3P3

VD

7

021

1213141516171819

109865432

11

U7

49.9

R35

OPT_

LAT

+3P3V

+3P3

V

+5VA

+5VA

+5VA

+5VA

+5VA

+5VA

+5VA

DR_OUT

GND

VREF

-5V

AIN

C28

+5VA

VREF

+3P3

V D

BUFL

AT

BUFL

AT

DR_O

UT

316 5 4

T3

ADT4

-1WT

B00

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

AD81

38AR

M

+5VA

4 5

500

62 7

VAL

V+V−

NC

VOCM

81

02647-043

Figure 43. Evaluation Board Schematic

Page 24

AD6645

Rev. D | Page 23 of 24

0264

7-04

4Figure 44. Top Signal Level

0264

7-04

5

Figure 45. 5.0 V Plane Layer 3 and 3.3 V Plane Layer 4

0264

7-04

6

Figure 46. Ground Plane Layer 2 and Ground Plane Layer 5

0264

7-04

7

Figure 47. Bottom Signal Layer

Page 25

AD6645

Rev. D | Page 24 of 24

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-026-BCC-HD

0.65BSC

LEAD PITCH

0.380.320.22

EXPOSEDHEAT SINK(CENTERED)

BOTTOM VIEW(PINS UP)

1.60MAX

VIEW A

PIN 1

0.750.600.45 4052 40 52

1413

26 142627

39

27

39

TOP VIEW(PINS DOWN)

1

13

1

0.20 0.08

1.451.401.35

0.10 MAXCOPLANARITY

VIEW AROTATED 90° CCW

SEATINGPLANE

7°0°0.15

0.05

12.2012.00 SQ11.80

10.2010.00 SQ 9.80

2.652.50 (4 PLCS)2.35

2.352.20 (4 PLCS)2.05

6.055.90 SQ5.75

0821

08-A

FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

Figure 48. 52-Lead Low Profile Quad Flat Package, PowerQuad [LQFP_PQ4]

(SQ-52-1) Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MS-026-ACC

40521

14

13

2627

39

12.00 BSCSQ

10.00BSC SQ

1.20MAX

0.750.600.45

VIEW A

TOP VIEW(PINS DOWN)

PIN 1

40 52

14

1

13

2627

39

0.65BSC

LEAD PITCH

0.380.320.22

BOTTOM VIEW(PINS UP)

6.50 BSCSQEXPOSED

PAD

0724

08-A

FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

SEATINGPLANE

1.051.000.95

0.200.09

0.08 MAXCOPLANARITY

VIEW AROTATED 90° CCW

0° MIN

7°3.5°0°0.15

0.05

Figure 49. 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-52-1) Dimensions shown in millimeters

ORDERING GUIDE Model Temperature Range Package Description Package Option AD6645ASQ-80 −40°C to +85°C 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) SQ-52-1 AD6645ASQZ-801 −40°C to +85°C 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) SQ-52-1 AD6645ASVZ-801

−40°C to +85°C 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-52-1 AD6645ASQ-105 −10°C to +85°C 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) SQ-52-1 AD6645ASQZ-1051

−10°C to +85°C 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) SQ-52-1 AD6645ASVZ-1051

−10°C to +85°C 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-52-1 AD6645-80/PCBZ1

Evaluation Board AD6645-105/PCBZ1

Evaluation Board 1 Z = RoHS Compliant Part. ©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02647-0-10/08(D)