ACOE161 - Digital Logic for Computers - Frederick University1 MSI Devices M. Mano & C. Kime: Logic and Computer Design Fundamentals (Chapter 5) Dr. Costas.

ACOE161 - Digital Logic for Computers - Frederick University

1

MSI Devices

M. Mano & C. Kime: Logic and Computer Design Fundamentals (Chapter 5)

Dr. Costas Kyriacou and Dr. Konstantinos Tatas


2

MSI Devices

• Medium Scale Integration (MSI) devices are digital devices that are build using

a few tens to hundreds of logic gates.

• MSI devices are used as discrete devices packed in a single Integrated Circuit

(IC), or as building blocks for other, more complex devices such as memory

devices or microprocessors.

• Some typical MSI devices are the following:

– Encoders and Decoders

– Multiplexers and Demultiplexers

– Full Adders

– Latches and flip flops

– Registers and Counters


3

Examples of MSI Devices

1 2 3

4 5 6

7 8 9

0

Y2

Y0

Y1

Y3

DEC/BCD

D2

D0

D1

D3

D6

D4

D5

D7

D8

D9

Decimal to BCD Encoder

0

1

0

1 0 1 2 3 4 5 6 7

0 1 0 10 1BCD/DEC

8 9

0

1

0 1

0

1

A2

Y2A0

Y0

Y1

Y3

Y6

Y4

Y5

Y7

A1

A3

Y8

Y9

BCD to Decimal Decoder

4-to-1 Multiplexer

I0

I1

I2

I31

0

1

1

1

321

0

4/1 Mux


4

Decoders

• A decoder is a combinational digital circuit with a number of inputs ‘n’ and a number of outputs ‘m’, where m= 2n

• Only one of the outputs is enabled at a time. The output enabled is the one specified by the binary number formed at the inputs of the decoder.

• On the circuit below, the inputs of the decoder are connected on three switches, forming the number 5 [(101)2], thus only LED #5 will be ON

0

1

0

1

0

1 0 1 2 3 4 5 6 7

0 1 0 10 1

A2

Y2A0

Y0

Y1

Y3

3/8 DEC.

Y6

Y4

Y5

Y7

A1


5

2 to 4 Line Decoder:

A1

A0

Y0

Y1

Y2

Y3

Y = E A A0 1 0

Y = E A A1 1 0

Y = E A A2 1 0

Y = E A A3 1 0

2-to-4 Line Decoder with Enable Input

Logic Symbol Truth Table

LogicExpressions Logic Circuit

A1

Y2

A0

Y0

Y1

Y3

2/4 DEC

E

A1 Y0 Y1 Y2 Y3

0

0

0

0 0 0

0

000

0 0 0

001

1

1 1 1

1

1

1

A0E

0

1

1

1

1 0

X X 0 0 0 0

E

A1

Y2A0

Y0

Y1

Y3

2/4 DEC A1 Y0 Y1 Y2 Y3

0 0

0

0

0 0 0

0

000

0 0 0

001

1

1 1 1

1

1

1

A0

A1

A0

Y0

Y1

Y2

Y3

Y = A A0 1 0

Y = A A1 1 0

Y = A A2 1 0

Y = A A3 1 0

2-to-4 Line Decoder

Logic Symbol Truth Table

LogicExpressions

Logic Circuit


6

3 to 8 Line Decoder:

A2

A0

Y0

Y1

Y2

Y3

3-to-8 Line Decoder with Enable Input

Logic Symbol Truth Table Logic Circuit

A1 Y0 Y1 Y2 Y3

0

0

0

0 0 0

0

000

0 0 0

001

1

1 1 1

1

1

1

A0E

0

1

1

1

1 0

X X 0 0 0 0

0

0

0

0 0 0

0

000

0 0 0

001

1

1 1 0

0

0

0

1

1

1

1 0

Y4 Y5 Y6 Y7

0 0 0

0

000

0 0 0

00

0

0

0

0

0 0 0 0

0 0 0

0

000

0 0 0

00

1

1

1

1

A1

0

0

0

0

X

1

1

1

1

A1

Y4

Y5

Y6

Y7

E

A2 Y2

A0

Y0

Y1

Y3

3/8 DEC

E

Y6

Y4

Y5

Y7

A1


7

3 to 8 Line Decoder: (Implementation using two 2-to-4 decoders)

A2 A0

Y0

Y1

Y2

Y3

2-to-4 with E = A2 Logic Circuit

A1 Y0 Y1 Y2 Y3

0

0

0

0 0 0

0

000

0 0 0

001

1

1 1 1

1

1

1

A0E

0

1

1

1

1 0

X X 0 0 0 0

0

0

0

0 0 0

0

000

0 0 0

001

1

1 1 0

0

0

0

1

1

1

1 0

Y4 Y5 Y6 Y7

0 0 0

0

000

0 0 0

00

0

0

0

0

0 0 0 0

0 0 0

0

000

0 0 0

00

1

1

1

1

A1

0

0

0

0

X

1

1

1

1

A1

Y4

Y5

Y6

Y7

2-to-4 with E = A2

A1

Y2

A0

Y0

Y1

Y3

2/4 DEC

E

A1

Y2

A0

Y0

Y1

Y3

2/4 DEC

E


8

3 to 8 Line Decoder: (Implementation using two 2-to-4 decoders)

A2 A0

Y0

Y1

Y2

Y3

A1

Y4

Y5

Y6

Y7

A1

Y2

A0

Y0

Y1

Y3

2/4 DEC

E

A1

Y2

A0

Y0

Y1

Y3

2/4 DEC

E

A2A1A0 A2A1A0 A2A1A0 A2A1A0 A2A1A0A2A1A0 A2A1A0 A2A1A0

1 1 11 1 01 0 11 0 00 1 10 1 00 0 10 0 0


9

4 to 16 Line Decoder: (Implementation using four 2-to-4 decoders)

A1

Y2

A0

Y0

Y1

Y3

2/4

DE

C

E A1

Y2

A0

Y0

Y1

Y3

2/4

DE

C

E A1

Y2

A0

Y0

Y1

Y3

2/4

DE

C

E A1

Y2

A0

Y0

Y1

Y3

2/4

DE

C

E

A1

Y2

A0

Y0

Y1

Y3

2/4

DE

C

E

A2A3 E A1 A0

Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15Y7Y6Y5Y4Y3Y2Y1Y0


10

ENCODERS

• A decoder in general is a combinational digital circuit with with a number of inputs ‘m’ and a number of outputs ‘n’, where n = log2m

• A binary encoder has precisely the opposite functionality of the binary decoder.

• A priority encoder is a special case of encoder used in computer interrupt mechanisms to specify which device requests service and prioritize interrupts that occur at the same time

I3 I2 I1 I0 O1 O0 V

0 0 0 0 X X 0

0 0 0 1 0 0 1

0 0 1 X 0 1 1

0 1 X X 1 0 1

1 X X X 1 1 1


11

Multiplexers

• A multiplexer is a device that has a number of data inputs “m”, and number of control inputs “n” and one output, such that m=2n. The output has always the same value as the data input specified by the binary number at the control inputs.

• The rotary switch (selector) shown in figure (a) below, is equivalent to a 4-to-1 multiplexer.

• The sliding switch shown in figure (b) below, is equivalent to an 8-to-1 multiplexer.

(a) 4-to-1 Multiplexer

1 1 0 1 0 0 1 1

0

I0 I1 I2 I3 I4 I5 I6 I7

Y 8/1 MuxI0

I1

I2

I31

0

1

1

1

321

0

4/1 Mux

(b) 8-to-1 Multiplexer


12

Internal structure of a 2-to-1 multiplexer.

• The design of a 2-to-1 multiplexer is shown below.• If S=0 then the output “Y” has the same value as the input “I0”

• If S=1 then the output “Y” has the same value as the input “I1”

I1

I0Y

2/1 MUX

Y = S I + S I0 1

Logic Symbol

Truth TableLogic Expression

I1 Y

0

0

0 0

1

11

1

1 1

0

I0

0

0

0

0 1

1

01

1

1 1

00

S

0

0

0

0

1

1

1

1

I1I000

0

01

1

11 10S0 1 1 0

0 0 1 1S

I1

Y

I0

S

1

0

Logic Function

S

I1

I0

Y

Logic Circuit

1/2 Dec.

2-to-1 Multiplexer


13

4-to-1 Multiplexer (MUX)

4-to-1 MUX

O

I0

I1

I2

I3

S1 S0

S1 S0 O

0 0 I0

0 1 I1

1 0 I2

1 1 I3

2-to-1 MUX

O

I0

I1

I2

I3

S1

S0

2-to-1 MUX

2-to-1 MUX


14

1-bit Full Adder

A B Cin Cout Sum

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Y0A

B

C

3/8 Dec.

En

Y1

Y2

Y3

Y4

Y5

Y6

Y7

I08/1 Mux

Y

I1

I2

I3

S2 S1 S0

I4

I5

I6

I7

I0

8/1 Mux

Y

I1

I2

I3

S2 S1 S0

I4

I5

I6

I7

1-Bit F.A.

Cout Sum

A B Cin

Logic Symbol

Truth Table

1-Bit Full Adder using gates

1-Bit Full Adder using a decoder 1-Bit Full Adder using 8/1 multiplexers

I04/1 Mux

Y

S0S1

I1

I2

I3

Cout Sum

Cin

A

B

A

B

Cin

Sum

Cout

A

B

Cin

0

0

0

1

0

1

1

1

0

1

1

0

0

0

1

1

Sum

Cout

I0

4/1 Mux

Y

S0S1

I1

I2

I3

A

B

Cin

0

1

A

A

A'

A

A'Sum

Cout

1-Bit Full Adder using 4/1 multiplexers


15

4-bit Full Adder (Ripple-Carry Adder)

• To obtain a 4-bit full adder we cascade four 1-bit full adders, by connecting the Carry Out bit of bit column M to the Carry In of the bit column M+1, as shown below. The Carry In of the Least Significant column is set to zero.

1-Bit F.A.

Cout Sum

A B C in

1-Bit F.A.

Cout Sum

A B C in

1-Bit F.A.

Cout Sum

A B C in

1-Bit F.A.

Cout Sum

A B C in

A3 B3 A0 B0A2 B2 A1 B1

0

S3 S2 S1 S0

Cout

• Example: Find the bit values of the outputs {Cout,S3..S0} of the full adder shown below, if {A3..A0 = 1011} and {B3..B0 = 0111}.


16

Example

• Design a 4-bit adder/subtracter using Full-adders and gates.


17

Magnitude Comparator

X3

X1

X0

X2

Y0

Y1

Y2

Y3

X=Y

X0

Y0

X1

Y1

X2

Y2

X3

Y3


18

Review questions

• How many input/output signals are present in a– 5-to-32 decoder?– 32-to-1 MUX?– 32-bit Ripple-Carry Adder (RCA)?

• How many 2-to-1 MUXs are required to build a 32-to-1 MUX?

• Design a logic unit with 2 data inputs (A, B), three select inputs (S2, S1, S0) and the following specifications:

S2 S1 S0 O

0 0 0 A AND B

0 0 1 A OR B

0 1 0 A XOR B

0 1 1 A NAND B

1 0 0 A NOR B

1 0 1 A XNOR B

1 1 0 A΄

1 1 1 B΄


19

Review questions 2

• Use two 4-to-1 MUXs to build a full adder• Implement the following Boolean algebra equation using only a single 8-to-1

MUX: F(A,B,C,D) = Σ(0,3,5,6,8,9,14,15)

ACOE161 - Digital Logic for Computers - Frederick University1 MSI Devices M. Mano & C. Kime: Logic and Computer Design Fundamentals (Chapter 5) Dr. Costas.

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