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fpga03-cover+spine.qxdFPGA 2003 Eleventh ACM International
Symposium on Field-Programmable Gate Arrays
February 23-25, 2003 Monterey Beach Hotel Monterey, California
Copyright © 2003 by the Association for Computing Machinery, Inc (ACM). Permission to make digital or hard copies of portions of this work for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permission to republish from: Publications Dept. ACM, Inc., FAX +1-212-869-0481 or E-mail <[email protected]>. For other copying of articles that carry a code at the bottom of the first or last page, copying is permitted provided that the per-copy fee indicated in the code is paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923.
Cover Page Table of Contents Author Index
FPG A
FPGA 2003
Gate Arrays
February 23-25, 2003
Actel, Altera, Xilinx
FPGA 2003
Gate Arrays
February 23-25, 2003
Actel, Altera, Xilinx
New York, New York 10036
Copyright © 2003 by the Association for Computing Machinery, Inc. (ACM). Permission to make digital or hard copies of portions of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyright for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permission to republish from: Publications Dept., ACM, Inc. Fax +1 (212) 869-0481 or <[email protected]>. For other copying of articles that carry a code at the bottom of the first or last page, copying is permitted provided that the per-copy fee indicated in the code is paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923.
Notice to Past Authors of ACM-Published Articles
ACM intends to create a complete electronic archive of all articles and/or other material previously published by ACM. If you have written a work that has been previously published by ACM in any journal or conference proceedings prior to 1978, or any SIG Newsletter at any time, and you do NOT want this work to appear in the ACM Digital Library, please inform [email protected], stating the title of the work, the author(s), and where and when published.
ACM ISBN: 1-58113-651-X Additional copies may be ordered prepaid from: ACM Order Department PO Box 11405 New York, NY 10286-1405 Phone: 1-800-342-6626 (US and Canada) +1-212-626-0500 (all other countries) Fax: +1-212-944-1318 E-mail: [email protected]
ACM Order Number 480030 Printed in the USA
iii
Monterey Beach Resort, Monterey, California
February 23-25, 2003
Sponsored by ACM/SIGDA
with support from Altera, Xilinx, and Actel
On behalf of the organizing and program committees, welcome to FPGA 2003, the eleventh ACM/SIGDA International Symposium on Field Programmable Gate Arrays. This year’s symposium features twenty-four papers and thirty-two poster presentations describing the latest FPGA research. Authors from universities and commercial vendors present new work on topics ranging from cryptography and reconfigurable computing to FPGA architecture and design tools. The selection process was very difficult, and we wound up accepting only 24 of the 82 submitted papers for presentations. Many additional papers are included as posters.
The panel this year examines the possible impact of low cost ASICs on the FPGA market. The ever-growing capacity and speed of FPGAs have brought them into the heart of the silicon mainstream. Major ASIC vendors have responded by reviving masterslice gate arrays, standard prefab die with design- specific metal layers. Are low cost gate arrays a threat to the FPGA market? Or will the FPGA’s high volume, superior flexibility and time-to-market prevail?
FPGA 2003 provides a relaxed atmosphere for informal information exchange, networking and stimulating discussions with the leaders in FPGA research and development from industry and academia as well as the next generation of FPGA researchers. Paper sessions are separated by ample time to peruse the poster presentations and discuss the latest FPGA news.
We take this opportunity to thank everyone whose contributions have once again provided us with a high quality program, including the program committee, the organizing committee, SIGDA and especially the authors, speakers and session chairs.
Steve Trimberger Russ Tessier General Chair Program Chair
iv
Session 1: Novel Architectures Chair: Michael Butts (Cadence)
• Architectures and Algorithms for Synthesizable Embedded Programmable Logic Cores ............... 3 N. Kafafi, K. Bozman, S. J. E. Wilton (University of British Columbia)
• The Stratix™ Routing and Logic Architecture............................................................................................... 12 D. Lewis, V. Betz, P. Laventis, S. Marquardt, J. Rose (Altera Toronto Technology Centre), D. Jefferson, A. Lee, C. Lane, C. McClintock, B. Pedersen, G. Powell, S. Reddy, C. Wysocki, R. Cliff (Altera Corporation)
• A Pipelined Configurable Gate Array for Embedded Processors ........................................................... 21 A. Lodi, M. Toma, F. Campi, A. Cappelli, R. Guerrieri (University of Bologna) R. Canegallo (STMicroelectronics CR&D)
Session 2: Placement Chair: Vaughn Betz (Altera Corporation)
• Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement..................... 33 M. G. Wrighton, A. M. DeHon (California Institute of Technology)
• Parallel Placement for Field-Programmable Gate Arrays .......................................................................... 43 P. K. Chan, M. D. F. Schlag (University of California at Santa Cruz)
• I/O Placement for FPGAs with Multiple I/O Standards ................................................................................ 51 W.-K. Mak (University of South Florida)
Session 3: Routing Chair: Jason Cong, (UCLA)
• Wire Type Assignment for FPGA Routing ...................................................................................................... 61 S. Lee (University of Texas at Austin), H. Xiang, D. F. Wong (University of Illinois at Urbana-Champaign), R. Y. Sun (Xilinx Inc.)
• PipeRoute: A Pipelining-Aware Router for FPGAs ...................................................................................... 68 A. Sharma, C. Ebeling, S. Hauck (University of Washington)
• Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes ......................................................... 78 R. Huang, J. Wawrzynek (University of California at Berkeley), DeHon (California Institute of Technology)
Session 4: Prototyping, Verification, and Test Chair: Majid Sarrafzadeh, (UCLA)
• Implementation of BEE: a Real-Time Large-scale Hardware Emulation Engine................................. 91 C. Chang, B. Richards, R. W. Brodersen (University of California at Berkeley), K. Kuusilinna (University of California at Berkeley and Tampere University of Technology)
• High-Level Modeling and FPGA Prototyping of Microprocessors ........................................................ 100 J. Ray (Advanced Micro Devices, Inc.), J. C. Hoe (Carnegie Mellon University)
• Reducing Pin and Area Overhead in Fault-Tolerant FPGA-based Designs ....................................... 108 F. Lima, L. Carro, R. Reis (Universidade Federal do Rio Grande do Sul)
v
Session 5: Logic Synthesis and Mapping Chair: Steve Wilton, (University of British Columbia)
• Placement-Driven Technology Mapping for LUT-Based FPGAs ........................................................... 121 J. Y. Lin (Aplus Design Technologies, Inc.), A. Jagannathan, J. Cong (University of California at Los Angeles)
• Verifying the Correctness of FPGA Logic Synthesis Algorithms.......................................................... 127 B. Ratchev, M. Hutton, G. Baeckler, B. van Antwerpen (Altera Corporation)
• Using Logic Duplication to Improve Performance in FPGAs.................................................................. 136 K. Schabas, S. D. Brown (University of Toronto)
Session 6: Device-Level Design Chair: Guy Lemieux, (University of British Columbia)
• A Scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS Technology.................................................. 145 J. R. Guo, C. You, K. Zhou, R. P. Kraft, J. F. McDonald (Rensselaer Polytechnic Institute), B. S. Goda (United States Military Academy)
• Design of FPGA Interconnect for Multilevel Metalization......................................................................... 154 R. Rubin, A. DeHon (California Institute of Technology)
• Automatic Transistor and Physical Design of FPGA Tiles from an Architectural Specification . 164 K. Padalia, R. Fung, M. Bourgeault, A. Egier, J. Rose (University of Toronto)
Session 7: Architecture Analysis and Automation Chair: Sinan Kaptanoglu, (Altera Corporation)
• Architecture Evaluation for Power-Efficient FPGAs .................................................................................. 175 F. Li, D. Chen, L. He, J. Cong (University of California at Los Angeles)
• Post-Placement C-slow Retiming for the Xilinx Virtex FPGA ................................................................. 185 N. Weaver, Y. Markovskiy, Y. Patel, J. Wawrzynek (University of California at Berkeley)
• An FPGA Architecture with Enhanced Datapath Functionality.............................................................. 195 K. Leijten-Nowak (Eindhoven University of Technology), J. L. van Meerbergen (Philips Research Labs)
Session 8: Applications Chair: Ray Andraka, (Andraka Consulting Group)
• A Fully Pipelined Memoryless 17.8 Gbps AES-128 Encryptor................................................................ 207 K. U. Järvinen, M. T. Tommiska, J. O. Skyttä (Helsinki University of Technology)
• A Methodology to Implement Block Ciphers in Reconfigurable Hardware and its Application to Fast and Compact AES RIJNDAEL....................................................................... 216 F.-X. Standaert, G. Rouvroy, J.-J. Quisquater, J.-D. Legat (Université Catholique de Louvain)
• Energy-Efficient Signal Processing Using FPGAs ..................................................................................... 225 S. Choi, R. Scrofano, V. K. Prasanna (University of Southern California), J.-W. Jang (Sogang University)
Posters
• FPGA-based Design of an Evolutionary Controller for Collision-free Robot Navigation............... 237 M. A. H. B. Azhar, K. R. Dimond (University of Kent)
• FPGA Implementation of a Fast Hadamard Transformer for WCDMA ................................................. 237 S. K. Bahl, J. Plusquellic (University of Maryland)
vi
• Making Area-Performance Tradeoffs at the High Level Using the AccelFPGA Compiler for FPGAs .............................................................................................................. 237 P. Banerjee, V. Saxena, J. Uribe, M. Haldar, A. Nayak, V. Kim, D. Bagchi, S. Pal, N. Tripathi, R. Anderson (School AccelChip, Inc.)
• Design Framework for the Implementation of the 2-D Orthogonal Discrete Wavelet Transform on FPGA ............................................................................................................................................. 238 A. Benkrid, D. Crookes, K. Benkrid (The Queen's University of Belfast)
• A Logic Based Approach to Hardware Abstraction ................................................................................... 238 K. Benkrid, S. Belkacemi, D. Crookes (The Queen's University of Belfast)
• A Single-FPGA Implementation of Image Connected Component Labelling .................................... 238 K. Benkrid, S. Sukhsawas, D. Crookes, S. Belkacemi (The Queen's University of Belfast)
• An Estimation and Exploration Methodology from System-Level Specifications: Application to FPGAs .......................................................................................................................................... 239 S. Bilavarn (Swiss Federal Institute of Technology), G. Gogniat, J. L. Philippe (South Britany University)
• A Granularity-based Classification Model for Systems-on-a-Chip ....................................................... 239 S. Bingemer, P. Zipf, M. Glesner (Darmstadt University of Technology)
• Design of a Fingerprint System Using a Hardware/Software Environment........................................ 240 L. V. Bonato, R. F. Molz, J. C. Furtado, M. F. Ferrão (UNISC—-Dept. de Informática), F. G. Moraes (PUCRS—Faculdade de Informática)
• Customized Regular Channel Design in FPGAs ......................................................................................... 240 E. Bozorgzadeh, M. Sarrafzadeh (University of California at Los Angeles)
• A High-speed Successive Erasure BCH Decoder Architecture ............................................................. 241 T. Buerner (Friedrich-Alexander University of Erlangen-Nuremberg)
• Implementation of Digital Fixed-Point Approximations to Continuous-Time IIR Filters ................ 241 J. E. Carletta, R. J. Veillette, F. W. Krach, Z. Fang (The University of Akron)
• Track Placement: Orchestrating Routing Structures to Maximize Routabilit .................................... 241 K. Compton (Northwestern University), S. Hauck (University of Washington)
• Recursive Circuit Clustering for Minimum Delay and Area ..................................................................... 242 M. E. Dehkordi, S. D. Brown (University of Toronto)
• Using FPGAs for Data and Reorganization Engines: Preliminary Results for Spatial Pointer-based Data Structures .................................................................................................... 242 P. C. Diniz, J. Park (University of Southern California)
• On Hiding Latency in Reconfigurable Systems: The Case of Merge-Sort for an FPGA-Based System............................................................................................................................... 242 H. ElGindy, G. Ferizis
• Testing for Bit Error Rate in FPGA Communication Interfaces.............................................................. 243 Y. Fan, Z. Zilic (McGill University)
• On Computation and Resource Management in an FPGA-based Computation Environment..... 243 S. Ghiasi, K. Nguyen, E. Bozorgzadeh, M. Sarrafzadeh (University of California at Los Angeles)
• A SC-based Novel Configurable Analog Cell ............................................................................................... 243 B. Guo, J. Tong (Fudan University)
• FPGAs in Critical Hardware/Software Systems........................................................................................... 244 A. J. Hilton, G. Townson, J. G. Hall
• Power-aware Architectures and Circuits for FPGA-based Signal Processing .................................. 244 F. Honoré, B. Calhoun, A. Chandrakasan (Massachusetts Institute of Technology)
vii
• Reconfigurable Randomized K-way Graph Partitioning........................................................................... 245 F. Kocan (Southern Methodist University)
• Synthetic Circuit Generation Using Clustering and Iteration.................................................................. 245 P. D. Kundarewich, J. Rose (University of Toronto)
• An FPGA Architecture with Built-in Error Correction Capability ........................................................... 245 P. K. Lala, B. K. Kumar (University of Arkansas)
• Lattice Adaptive Filter Implementation for FPGA ....................................................................................... 246 Z. Pohl, R. Matoušek, J. Kadlec, M. Tichý (Institute of Information Theory and Automation,CAS) M. Líko, (Center for Applied Cybernetics)
• Wireless Sensor Networks: a Power-Scalable Motion Estimation IP for Hybrid Video Coding ... 246 F. Quaglio, M. Martina, F. Vacca, G. Masera, A. Molino, G. Piccinini, M. Zamboni (Politecnico di Torino)
• Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES................................... 247 G. Rouvroy, F.-X. Standaert, J.-J. Quisquater, J.-D. Legat (Université catholique de Louvain)
• A Physical Retiming Algorithm for Field Programmable Gate Arrays ................................................. 247 P. Suaris, D. Wang, P.-N. Guo, N.-C. Chou (Mentor Graphics Corporation)
• Application-Dependent Testing of FPGAs for Bridging Faults .............................................................. 248 M. B. Tahoori (Stanford University)
• A High Resolution Diagnosis Technique for Open and Short Defects in FPGA Interconnects ... 248 M. B. Tahooori (Stanford University)
• A Four-bit Full Adder Implemented on Fast SiGe FPGAs with Novel Power Control Scheme..... 248 K. Zhou, M. Chu, C. You, J.-R. Guo, Channakeshav, J. Mayega, B. S. Goda, R. P. Kraft, J. F. McDonald (Rensselaer Polytechnic Institute)
Author Index ............................................................................................................................................................. 249
Program Chair: Russ Tessier, University of Massachusetts - Amherst
Publicity Chair: Steve Wilton, University of British Columbia
Finance Chair: Martine Schlag, University of California, Santa Cruz
Program Committee Members: Ray Andraka, Andraka Consulting
Vaughn Betz, Altera
Michael Butts, Cadence
Andre’ DeHon, Caltech
Rajeev Jayaraman, Xilinx
Herman Schmit, Carnegie Mellon University
Russ Tessier, University of Massachusetts, Amherst
Steve Trimberger, Xilinx
Qiang Wang, Xilinx
Zeljko Zilic, McGill University
February 23-25, 2003 Monterey Beach Hotel Monterey, California
Copyright © 2003 by the Association for Computing Machinery, Inc (ACM). Permission to make digital or hard copies of portions of this work for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permission to republish from: Publications Dept. ACM, Inc., FAX +1-212-869-0481 or E-mail <[email protected]>. For other copying of articles that carry a code at the bottom of the first or last page, copying is permitted provided that the per-copy fee indicated in the code is paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923.
Cover Page Table of Contents Author Index
FPG A
FPGA 2003
Gate Arrays
February 23-25, 2003
Actel, Altera, Xilinx
FPGA 2003
Gate Arrays
February 23-25, 2003
Actel, Altera, Xilinx
New York, New York 10036
Copyright © 2003 by the Association for Computing Machinery, Inc. (ACM). Permission to make digital or hard copies of portions of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyright for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permission to republish from: Publications Dept., ACM, Inc. Fax +1 (212) 869-0481 or <[email protected]>. For other copying of articles that carry a code at the bottom of the first or last page, copying is permitted provided that the per-copy fee indicated in the code is paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923.
Notice to Past Authors of ACM-Published Articles
ACM intends to create a complete electronic archive of all articles and/or other material previously published by ACM. If you have written a work that has been previously published by ACM in any journal or conference proceedings prior to 1978, or any SIG Newsletter at any time, and you do NOT want this work to appear in the ACM Digital Library, please inform [email protected], stating the title of the work, the author(s), and where and when published.
ACM ISBN: 1-58113-651-X Additional copies may be ordered prepaid from: ACM Order Department PO Box 11405 New York, NY 10286-1405 Phone: 1-800-342-6626 (US and Canada) +1-212-626-0500 (all other countries) Fax: +1-212-944-1318 E-mail: [email protected]
ACM Order Number 480030 Printed in the USA
iii
Monterey Beach Resort, Monterey, California
February 23-25, 2003
Sponsored by ACM/SIGDA
with support from Altera, Xilinx, and Actel
On behalf of the organizing and program committees, welcome to FPGA 2003, the eleventh ACM/SIGDA International Symposium on Field Programmable Gate Arrays. This year’s symposium features twenty-four papers and thirty-two poster presentations describing the latest FPGA research. Authors from universities and commercial vendors present new work on topics ranging from cryptography and reconfigurable computing to FPGA architecture and design tools. The selection process was very difficult, and we wound up accepting only 24 of the 82 submitted papers for presentations. Many additional papers are included as posters.
The panel this year examines the possible impact of low cost ASICs on the FPGA market. The ever-growing capacity and speed of FPGAs have brought them into the heart of the silicon mainstream. Major ASIC vendors have responded by reviving masterslice gate arrays, standard prefab die with design- specific metal layers. Are low cost gate arrays a threat to the FPGA market? Or will the FPGA’s high volume, superior flexibility and time-to-market prevail?
FPGA 2003 provides a relaxed atmosphere for informal information exchange, networking and stimulating discussions with the leaders in FPGA research and development from industry and academia as well as the next generation of FPGA researchers. Paper sessions are separated by ample time to peruse the poster presentations and discuss the latest FPGA news.
We take this opportunity to thank everyone whose contributions have once again provided us with a high quality program, including the program committee, the organizing committee, SIGDA and especially the authors, speakers and session chairs.
Steve Trimberger Russ Tessier General Chair Program Chair
iv
Session 1: Novel Architectures Chair: Michael Butts (Cadence)
• Architectures and Algorithms for Synthesizable Embedded Programmable Logic Cores ............... 3 N. Kafafi, K. Bozman, S. J. E. Wilton (University of British Columbia)
• The Stratix™ Routing and Logic Architecture............................................................................................... 12 D. Lewis, V. Betz, P. Laventis, S. Marquardt, J. Rose (Altera Toronto Technology Centre), D. Jefferson, A. Lee, C. Lane, C. McClintock, B. Pedersen, G. Powell, S. Reddy, C. Wysocki, R. Cliff (Altera Corporation)
• A Pipelined Configurable Gate Array for Embedded Processors ........................................................... 21 A. Lodi, M. Toma, F. Campi, A. Cappelli, R. Guerrieri (University of Bologna) R. Canegallo (STMicroelectronics CR&D)
Session 2: Placement Chair: Vaughn Betz (Altera Corporation)
• Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement..................... 33 M. G. Wrighton, A. M. DeHon (California Institute of Technology)
• Parallel Placement for Field-Programmable Gate Arrays .......................................................................... 43 P. K. Chan, M. D. F. Schlag (University of California at Santa Cruz)
• I/O Placement for FPGAs with Multiple I/O Standards ................................................................................ 51 W.-K. Mak (University of South Florida)
Session 3: Routing Chair: Jason Cong, (UCLA)
• Wire Type Assignment for FPGA Routing ...................................................................................................... 61 S. Lee (University of Texas at Austin), H. Xiang, D. F. Wong (University of Illinois at Urbana-Champaign), R. Y. Sun (Xilinx Inc.)
• PipeRoute: A Pipelining-Aware Router for FPGAs ...................................................................................... 68 A. Sharma, C. Ebeling, S. Hauck (University of Washington)
• Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes ......................................................... 78 R. Huang, J. Wawrzynek (University of California at Berkeley), DeHon (California Institute of Technology)
Session 4: Prototyping, Verification, and Test Chair: Majid Sarrafzadeh, (UCLA)
• Implementation of BEE: a Real-Time Large-scale Hardware Emulation Engine................................. 91 C. Chang, B. Richards, R. W. Brodersen (University of California at Berkeley), K. Kuusilinna (University of California at Berkeley and Tampere University of Technology)
• High-Level Modeling and FPGA Prototyping of Microprocessors ........................................................ 100 J. Ray (Advanced Micro Devices, Inc.), J. C. Hoe (Carnegie Mellon University)
• Reducing Pin and Area Overhead in Fault-Tolerant FPGA-based Designs ....................................... 108 F. Lima, L. Carro, R. Reis (Universidade Federal do Rio Grande do Sul)
v
Session 5: Logic Synthesis and Mapping Chair: Steve Wilton, (University of British Columbia)
• Placement-Driven Technology Mapping for LUT-Based FPGAs ........................................................... 121 J. Y. Lin (Aplus Design Technologies, Inc.), A. Jagannathan, J. Cong (University of California at Los Angeles)
• Verifying the Correctness of FPGA Logic Synthesis Algorithms.......................................................... 127 B. Ratchev, M. Hutton, G. Baeckler, B. van Antwerpen (Altera Corporation)
• Using Logic Duplication to Improve Performance in FPGAs.................................................................. 136 K. Schabas, S. D. Brown (University of Toronto)
Session 6: Device-Level Design Chair: Guy Lemieux, (University of British Columbia)
• A Scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS Technology.................................................. 145 J. R. Guo, C. You, K. Zhou, R. P. Kraft, J. F. McDonald (Rensselaer Polytechnic Institute), B. S. Goda (United States Military Academy)
• Design of FPGA Interconnect for Multilevel Metalization......................................................................... 154 R. Rubin, A. DeHon (California Institute of Technology)
• Automatic Transistor and Physical Design of FPGA Tiles from an Architectural Specification . 164 K. Padalia, R. Fung, M. Bourgeault, A. Egier, J. Rose (University of Toronto)
Session 7: Architecture Analysis and Automation Chair: Sinan Kaptanoglu, (Altera Corporation)
• Architecture Evaluation for Power-Efficient FPGAs .................................................................................. 175 F. Li, D. Chen, L. He, J. Cong (University of California at Los Angeles)
• Post-Placement C-slow Retiming for the Xilinx Virtex FPGA ................................................................. 185 N. Weaver, Y. Markovskiy, Y. Patel, J. Wawrzynek (University of California at Berkeley)
• An FPGA Architecture with Enhanced Datapath Functionality.............................................................. 195 K. Leijten-Nowak (Eindhoven University of Technology), J. L. van Meerbergen (Philips Research Labs)
Session 8: Applications Chair: Ray Andraka, (Andraka Consulting Group)
• A Fully Pipelined Memoryless 17.8 Gbps AES-128 Encryptor................................................................ 207 K. U. Järvinen, M. T. Tommiska, J. O. Skyttä (Helsinki University of Technology)
• A Methodology to Implement Block Ciphers in Reconfigurable Hardware and its Application to Fast and Compact AES RIJNDAEL....................................................................... 216 F.-X. Standaert, G. Rouvroy, J.-J. Quisquater, J.-D. Legat (Université Catholique de Louvain)
• Energy-Efficient Signal Processing Using FPGAs ..................................................................................... 225 S. Choi, R. Scrofano, V. K. Prasanna (University of Southern California), J.-W. Jang (Sogang University)
Posters
• FPGA-based Design of an Evolutionary Controller for Collision-free Robot Navigation............... 237 M. A. H. B. Azhar, K. R. Dimond (University of Kent)
• FPGA Implementation of a Fast Hadamard Transformer for WCDMA ................................................. 237 S. K. Bahl, J. Plusquellic (University of Maryland)
vi
• Making Area-Performance Tradeoffs at the High Level Using the AccelFPGA Compiler for FPGAs .............................................................................................................. 237 P. Banerjee, V. Saxena, J. Uribe, M. Haldar, A. Nayak, V. Kim, D. Bagchi, S. Pal, N. Tripathi, R. Anderson (School AccelChip, Inc.)
• Design Framework for the Implementation of the 2-D Orthogonal Discrete Wavelet Transform on FPGA ............................................................................................................................................. 238 A. Benkrid, D. Crookes, K. Benkrid (The Queen's University of Belfast)
• A Logic Based Approach to Hardware Abstraction ................................................................................... 238 K. Benkrid, S. Belkacemi, D. Crookes (The Queen's University of Belfast)
• A Single-FPGA Implementation of Image Connected Component Labelling .................................... 238 K. Benkrid, S. Sukhsawas, D. Crookes, S. Belkacemi (The Queen's University of Belfast)
• An Estimation and Exploration Methodology from System-Level Specifications: Application to FPGAs .......................................................................................................................................... 239 S. Bilavarn (Swiss Federal Institute of Technology), G. Gogniat, J. L. Philippe (South Britany University)
• A Granularity-based Classification Model for Systems-on-a-Chip ....................................................... 239 S. Bingemer, P. Zipf, M. Glesner (Darmstadt University of Technology)
• Design of a Fingerprint System Using a Hardware/Software Environment........................................ 240 L. V. Bonato, R. F. Molz, J. C. Furtado, M. F. Ferrão (UNISC—-Dept. de Informática), F. G. Moraes (PUCRS—Faculdade de Informática)
• Customized Regular Channel Design in FPGAs ......................................................................................... 240 E. Bozorgzadeh, M. Sarrafzadeh (University of California at Los Angeles)
• A High-speed Successive Erasure BCH Decoder Architecture ............................................................. 241 T. Buerner (Friedrich-Alexander University of Erlangen-Nuremberg)
• Implementation of Digital Fixed-Point Approximations to Continuous-Time IIR Filters ................ 241 J. E. Carletta, R. J. Veillette, F. W. Krach, Z. Fang (The University of Akron)
• Track Placement: Orchestrating Routing Structures to Maximize Routabilit .................................... 241 K. Compton (Northwestern University), S. Hauck (University of Washington)
• Recursive Circuit Clustering for Minimum Delay and Area ..................................................................... 242 M. E. Dehkordi, S. D. Brown (University of Toronto)
• Using FPGAs for Data and Reorganization Engines: Preliminary Results for Spatial Pointer-based Data Structures .................................................................................................... 242 P. C. Diniz, J. Park (University of Southern California)
• On Hiding Latency in Reconfigurable Systems: The Case of Merge-Sort for an FPGA-Based System............................................................................................................................... 242 H. ElGindy, G. Ferizis
• Testing for Bit Error Rate in FPGA Communication Interfaces.............................................................. 243 Y. Fan, Z. Zilic (McGill University)
• On Computation and Resource Management in an FPGA-based Computation Environment..... 243 S. Ghiasi, K. Nguyen, E. Bozorgzadeh, M. Sarrafzadeh (University of California at Los Angeles)
• A SC-based Novel Configurable Analog Cell ............................................................................................... 243 B. Guo, J. Tong (Fudan University)
• FPGAs in Critical Hardware/Software Systems........................................................................................... 244 A. J. Hilton, G. Townson, J. G. Hall
• Power-aware Architectures and Circuits for FPGA-based Signal Processing .................................. 244 F. Honoré, B. Calhoun, A. Chandrakasan (Massachusetts Institute of Technology)
vii
• Reconfigurable Randomized K-way Graph Partitioning........................................................................... 245 F. Kocan (Southern Methodist University)
• Synthetic Circuit Generation Using Clustering and Iteration.................................................................. 245 P. D. Kundarewich, J. Rose (University of Toronto)
• An FPGA Architecture with Built-in Error Correction Capability ........................................................... 245 P. K. Lala, B. K. Kumar (University of Arkansas)
• Lattice Adaptive Filter Implementation for FPGA ....................................................................................... 246 Z. Pohl, R. Matoušek, J. Kadlec, M. Tichý (Institute of Information Theory and Automation,CAS) M. Líko, (Center for Applied Cybernetics)
• Wireless Sensor Networks: a Power-Scalable Motion Estimation IP for Hybrid Video Coding ... 246 F. Quaglio, M. Martina, F. Vacca, G. Masera, A. Molino, G. Piccinini, M. Zamboni (Politecnico di Torino)
• Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES................................... 247 G. Rouvroy, F.-X. Standaert, J.-J. Quisquater, J.-D. Legat (Université catholique de Louvain)
• A Physical Retiming Algorithm for Field Programmable Gate Arrays ................................................. 247 P. Suaris, D. Wang, P.-N. Guo, N.-C. Chou (Mentor Graphics Corporation)
• Application-Dependent Testing of FPGAs for Bridging Faults .............................................................. 248 M. B. Tahoori (Stanford University)
• A High Resolution Diagnosis Technique for Open and Short Defects in FPGA Interconnects ... 248 M. B. Tahooori (Stanford University)
• A Four-bit Full Adder Implemented on Fast SiGe FPGAs with Novel Power Control Scheme..... 248 K. Zhou, M. Chu, C. You, J.-R. Guo, Channakeshav, J. Mayega, B. S. Goda, R. P. Kraft, J. F. McDonald (Rensselaer Polytechnic Institute)
Author Index ............................................................................................................................................................. 249
Program Chair: Russ Tessier, University of Massachusetts - Amherst
Publicity Chair: Steve Wilton, University of British Columbia
Finance Chair: Martine Schlag, University of California, Santa Cruz
Program Committee Members: Ray Andraka, Andraka Consulting
Vaughn Betz, Altera
Michael Butts, Cadence
Andre’ DeHon, Caltech
Rajeev Jayaraman, Xilinx
Herman Schmit, Carnegie Mellon University
Russ Tessier, University of Massachusetts, Amherst
Steve Trimberger, Xilinx
Qiang Wang, Xilinx
Zeljko Zilic, McGill University
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