ABC: A System for Logic Synthesis and Formal Verification

ABC: A System for Logic Synthesis and Formal Verification

Alan MishchenkoUniversity of California, Berkeley

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Outlinel Basic level

l Boolean calculator and visualizerl Standard commands and scripts

l Advanced levell Key packages and data-structuresl Ways to improve runtime and memory usage

l Hits and missesl Future research directions

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Boolean Calculatorl Read/generate small functions/networks

l Automatically extracted or manually specifiedl Compute basic functional properties

l Symmetries, decomposability, unateness, etcl Transform them in various ways

l Minimize SOP, reorder BDD, extract kernels, etcl Visualization

l Use text output, dot / GSView, etc

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Standard Commands/Scripts

l Technology independent synthesisl Logic synthesis for PLAsl Technology mapping for standard cellsl Technology mapping for LUTsl Sequential synthesisl Verification

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AIG Rewriting

a b a c

Subgraph 1

b ca

Subgraph 2

l Pre-computing AIG subgraphsl Consider function f = abc

a cb

Subgraph 3

Rewriting AIG subgraphsRewriting node A

Rewriting node B

⇒

a b a c

⇒

a b a c

A

Subgraph 1b c

a

A

Subgraph 2

b ca

B

Subgraph 2

a b a c

B

Subgraph 1

In both cases 1 node is saved

l AIG rewriting has the goal of minimizing the number of AIG nodes

P. Bjesse and A. Boralv, "DAG-aware circuit compression for formal verification", Proc. ICCAD ’04.

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Technology Independent Synthesisl AIG rewriting for area

l Scripts drwsat, compress2rsl AIG rewriting for delay

l Scripts dc2, resyn2l Scripts &syn2, &synch2

l High-effort delay optimizationl Perform SOP balancing (st; if –g –K 6)l Follow up with area-recovery (resyn2) and technology

mapping (map, amap, if)l Iterate, if needed

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Logic Synthesis for PLAsl Enter PLA (.type fd) into ABC using readl Perform logic sharing extraction using fx

l If fx is complaining that individual covers are not prime and irredundant, try bdd; sop; fx

l After fx, convert shared logic into AIG and continue AIG-based synthesis and mapping if needed

l Consider using high-effort synthesis with don’t-caresl First map into 6-LUTs (if –K 6; ps), optimize (mfs2), synthesize with

choices (st; dch) and map into 6-LUTs (if –K 6; ps)l Iterate until no improvement, then remap into target technology

l To find description of PLA format, google for “Espresso PLA format”, for example:l http://www.ecs.umass.edu/ece/labs/vlsicad/ece667/links/espresso.

5.html

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LUT MappingInput: A Boolean network (And-Inverter Graph)

Output: A netlist of K-LUTs covering the AIG and optimizing some cost function

The subject graph The mapped netlist

TechnologyMapping

a b c d

f

e a b c d e

f

A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, "Combinational and sequential mapping with priority cuts", Proc. ICCAD '07, https://people.eecs.berkeley.edu/~alanmi/publications/2007/iccad07_map.pdf

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Technology Mapping for SCsl Read library using

l read_genlib (for libraries in GENLIB format)l read_liberty (for libraries in Liberty format)

l For standard-cellsl map: Boolean matching, delay-oriented, cells up to 5 inputsl amap: structural mapping, area-oriented, cells up to 15 inputs

l If Liberty library is used, run topo followed byl stime (accurate timing analysis)l buffer (buffering)l upsize; dnsize (gate sizing)

l Structural choices are an important way of improving mapping (both area and delay)l Run st; dch before calling map or amap

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Technology Mapping for LUTsl It is suggested to use mapper if –K <num>

l For area-oriented mapping, try if -al For delay-oriented mapping, try delay-oriented AIG-

based synthesis with structural choicesl Structural choices are an important way of

improving mapping (both area and delay)l Run st; dch before calling if

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Synthesis With Structural Choicesl Traditional synthesis produces one “optimized” networkl Synthesis with choices produces several networks

l These can be different snapshot of the same synthesis flowl These can be results of synthesizing the design with different options

l For example, area-oriented and delay-oriented scripts

Synthesis

D2D1

Synthesis with structural choices

D3HAIG

D2D1 D3 D4

D4

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Sequential Synthesisl Uses reachable state information to further

improve the quality of resultsl Reachable states are often approximated

l Types of AIG-based sequential synthesisl Retiming (retime, dretime, etc)l Detecting and merging sequential equivalences

(lcorr, scorr, &scorr, etc)l Negative experiences

l Sequential redundancy removal is often hardl Using sequential don’t-cares in combinational

synthesis typically gives a very small improvement

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Formal Verificationl Equivalence checking

l Takes two designs and makes a miter (AIG)

l Model checkingl Takes design and

property and makes a miter (AIG)

The goal is the same:to transform AIG until the output is proved constant 0

D2D1

Equivalence checking

0

D1

Property checking

0p

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Verificationl Combinational verification

l r <file1>; cec <file2> (small/medium circuits)l &r <file1.aig>; &cec <file2.aig> (large circuits)

l Sequential verificationl r <file1>; dsec <file2>

l Running cec or dsec any time in a synthesis flow compares the current network against its specl The spec is the circuit obtained from the original file

l Verification and synthesis are closely related and should be co-developed

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l Future research directions

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Key Packages

l AIG packagel Technology-independent synthesisl Technology mappersl SAT solverl Combinational equivalence checkingl Sequential synthesisl Sequential verification engine IC3/PDR

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Key Packages


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And-Inverter Graph (AIG)

cdab 00 01 11 10

00 0 0 1 0

01 0 0 1 1

11 0 1 1 0

10 0 0 1 0

F(a,b,c,d) = ab + d(a!c+bc)

F(a,b,c,d) = a!c(b+d) + bc(a+d)cd

ab 00 01 11 10

00 0 0 1 0

01 0 0 1 1

11 0 1 1 0

10 0 0 1 0

6 nodes

4 levels

7 nodes

3 levels

b ca c

a b d

a c b d b c a d

AIG is a Boolean network composed of two-input ANDs and inverters

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Components of Efficient AIG Packagel Structural hashing

l Leads to a compact representationl Is applied during AIG construction

l Propagates constantsl Makes each node structurally unique

l Complemented edgesl Represents inverters as attributes on the edges

l Leads to fast, uniform manipulationl Does not use memory for invertersl Increases logic sharing using DeMorgan’s rule

l Memory allocationl Uses fixed amount of memory for each node

l Can be done by a custom memory managerl Even dynamic fanout can be implemented this way

l Allocates memory for nodes in a topological orderl Optimized for traversal using this topological orderl Small static memory footprint for many applications

l Computes fanout information on demand

a b

c d

a b

c d

Without hashing

With hashing

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“Minimalistic” AIG Packagel Designed to minimize memory requirements

l Baseline: 8 bytes/node for AIGs (works up to 2 billion nodes)l Structural hashing: +8 bytes/nodel Logic level information: +4 bytes/nodel Simulation information: +8 bytes/node for 64 patterns

l Each node attribute is stored in a separate arrayl No “Aig_Node” structl Attributes are allocated and deallocated on demandl Helps improve locality of computationl Very useful to large AIG (100M nodes and more)

l Maintaining minimum memory footprint for basic tasks, while allowing the AIG package to have several optional built-in featuresl Structural hashingl Bit-parallel simulationl Circuit-based SAT solving

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Key Packages


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SAT Solverl Modern SAT solvers are practicall A modern solver is a treasure-trove of tricks for

efficient implementation l To mentions just a few

l Representing clauses as arrays of integersl Using signatures to check clause containmentl Using two-literal watching schemel etc

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What is Missing in a SAT Solver? (from the point of view of logic synthesis)

l Modern SAT solvers are geared to solving hard problems from SAT competitions or hard verification instances (1 problem ~ 15 min)l This motivates elaborate data-structures and high memory usage

l 64 bytes/variable; 16 bytes/clause; 4 bytes/literal

l In logic synthesis, runtime of many applications is dominated by SATl SAT sweeping, sequential synthesis, computing structural choices, etc

l The SAT problems solved in these applications arel Incremental (+/- 10 AIG nodes, compared to a previous problem)l Relatively easy (less than 10 conflicts)l Numerous (100K-1M problems in one run)

l For these appliactions, a new circuit-based SAT solver can be developed (abc/src/aig/gia/giaCSat.c)

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Experimental Results

abc 01> &r corrsrm06.aig; &sat -v -C 100CO = 98192 AND = 544369 Conf = 100 MinVar = 2000 MinCalls = 200Unsat calls 32294 ( 32.89 %) Ave conf = 4.6 Time = 2.12 sec ( 15.35 %)Sat calls 65540 ( 66.75 %) Ave conf = 0.6 Time = 9.38 sec ( 67.82 %)Undef calls 358 ( 0.36 %) Ave conf = 101.6 Time = 0.98 sec ( 7.08 %)Total time = 13.83 sec

abc 01> &r corrsrm06.aig; &sat -vc -C 100CO = 98192 AND = 544369 Conf = 100 JustMax = 100Unsat calls 31952 ( 32.54 %) Ave conf = 3.3 Time = 0.12 sec ( 14.51 %)Sat calls 65501 ( 66.71 %) Ave conf = 0.3 Time = 0.42 sec ( 52.77 %)Undef calls 739 ( 0.75 %) Ave conf = 102.3 Time = 0.20 sec ( 24.48 %)Total time = 0.80 sec

l Well-tuned version based on MiniSAT

l Version based on circuit-based solver

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Why MiniSAT Is Slower?l Requires multiple intermediate steps

l Window → AIG → CNF → Solvingl Instead of Window → Solving

l Generates counter examples in the form ofl Complete assignment of primary inputsl Instead of Partial assignment of primary inputs

l Uses too much memoryl Solver + CNF = 140 bytes / AIG nodel Instead of 8-16 bytes / AIG node

l Decision heuristicsl Is not aware of the circuit structurel Instead of Using circuit information

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General Guidelines for Improving Speed and Memory Usage of Software

l Minimize memory usagel Use integers instead of pointersl Recycle memory whenever possible

l especially if memory is split into chunks of the same size

l Use book-keeping to avoid useless computationl Windowing, local fanout, event-driven simulation

l If application is important, design custom specialized data-structuresl Typically the overhead to covert to the custom data-

structure is negligible, compared to the runtime saved by using it

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ABC Hitsl It is based on what we believe to be

cutting-edge research ideasl It offers a low-cost and often competitive

implementation of fundamental algorithmsl AIG rewriting, tech-mapping, SAT sweeping,

retiming, equivalence checking, etcl It is often fast and low-memoryl It is reliable (if we use it in a known way)l It is actively developed and supported

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ABC Misses

l Inadequate Verilog parserl Does not natively support much of the

“industrial stuff” (complex flops, multiple clocks, memories, design constraints, etc)l requires elaborate workarounds to be useful

l Poor documentationl A lot of redundant source code

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Lessons: Front-End and Back-End

l Having a variety of formats is useful, but…l Reading and writing Verilog is a must!

l If a general-enough Verilog parser cannot be developed, integrate with Yosys

l Absolutely need well-documented APIs for integrating with external tools!l This has been addressed to some extent

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Lessons: Optimization Flow

l AIG is a good unifying data-structure l Do not hesitate to base computations on AIGs

l Need parametrizable optimizersl Rather than having optimizations geared to a

specific representation (AIG/MIG/XMIG/etc)l Need one generic cut-based tech-mapper

for all technologies (gates, LUTs, etc) l Need to support the “industrial stuff”!

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Lessons: Data Structures

l Develop a clean minimalistic data-structure for each package (conversions between data-structures are easy and fast)

l Reduce memory for large data-structures and runtime will be reducedl true about AIG, logic network, hierarchical netlist

l Whenever possible, use 32-bit integers l a MiniSAT-like SAT solver is a good example

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Lessons: Programming

l Strive for maintainabilityl Minimize dependency between packages

l Strive for reproducibilityl Implement your own floating point number

l Strive for thread-safetyl Have no global and static variables

l Spend time to build a set of handy toolsl Go beyond C (mix C and C++)

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Research Directionsl Ongoing

l Deep integration of simulation and SATl Word-level optimizations (e.g. memory abstraction)l Logic synthesis for machine learning

l As opposed to machine learning for logic synthesis!

l Hopefully, some dayl Improved Verilog interface and RTL elaboration

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Industrial Supporters (since 2005)

l CAD tool companiesl Synopsys, Mentor (Siemens), Cadence, Verific, Magma

(Synopsys), Atrenta (Synopsys), Jasper (Cadence), Oasys (Mentor)

l FPGA companiesl Xilinx (AMD), Altera (Intel), Synplicity (Synopsys), Actel

(Microsemi), Abound Logic (Lattice), Tabula (?)l System design companies

l IBM, Intel

l Plus grants from federal and industrial funding agenciesl NFS, NSA, SRC

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Contributors to ABCl Fabio Somenzi (U Colorado, Boulder) - BDD package CUDDl Niklas Sorensson, Niklas Een (Chalmers U, Sweden) - MiniSAT v. 1.4 (2005)l Gilles Audemard, Laurent Simon (U Artois, U Paris Sud, France) - Glucose 3.0

l Hadi Katebi, Igor Markov (U Michigan) - Boolean matching for CECl Jake Nasikovsky - Fast truth table manipulationl Wenlong Yang (Fudan U, China) - Lazy man’s synthesisl Zyad Hassan (U Colorado, Boulder) - Improved generalization in IC3/PDRl Augusto Neutzling, Jody Matos, Andre Reis (UFRGS, Brazil) - Technology mapping into

threshold functionsl Mayler Martins. Vinicius Callegaro, Andre Reis (UFRGS, Brazil) – Boolean

decomposition using read-polarity-once (RPO) functionl Mathias Soeken, EPFL - Exact logic synthesisl Ana Petkovska, EPFL – Hierarchical NPN matchingl Bruno Schmitt (UFRGS / EPFL) - Fast-extract with cube hashingl Xuegong Zhou, Lingli Wang (Fudan U, China) - NPN classificationl Yukio Miyasaka, Masahiro Fujita (U Tokyo, Japan) - Custom BDD package for multiplier

verificationl Siang-Yun Lee, Roland Jiang (NTU, Taiwan) - Dumping libraries of minimum circuits for

functions up to five input variablesl He-Teng Zhang (NTU, Taiwan) – Circuit-based SAT solver, enhanced SAT sweeper

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ABC Resources l Source code

l https://github.com/berkeley-abc/abcl “Getting started with ABC”, a tutorial by Ana Petkovska

l https://www.dropbox.com/s/qrl9svlf0ylxy8p/ ABC_GettingStarted.pdf

l An overview paper: R. Brayton and A. Mishchenko, "ABC: An academic industrial-strength verification tool", Proc. CAV'10.l http://www.eecs.berkeley.edu/~alanmi/publications/

2010/cav10_abc.pdfl Windows binary

l http://www.eecs.berkeley.edu/~alanmi/abc/abc.exel http://www.eecs.berkeley.edu/~alanmi/abc/abc.rc

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Conclusionsl If you have patience and time to figure it out,

ABC can be very useful

l Do not hesitate to contact me if you have any questions or ideas

l Consider contributing something that could be helpful for others, for examplel the code used in your paperl your course project

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Abstractl The talk presents ABC on three levels. l On the basic level, ABC is discussed in general,

what it has to offer for different users, and what are the most important computations and commands.

l On the advanced level, there is an overview of different ABC packages and the lessons learned while developing them, as well as an in-depth look into the important data-structures and coding patterns that make ABC fast and efficient.

l Finally, there is an overview of research efforts and an invitation for contributions.

ABC: A System for Logic Synthesis and Formal Verification

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