A Zero-IF 60GHz Transceiver A Zero-IF 60GHz Transceiver in 65nm CMOS with > 3.5Gb/s in 65nm CMOS with > 3.5Gb/s Links Links Alexander Tomkins, Ricardo A. Aroca, Takuji Yamamoto*, Sean Alexander Tomkins, Ricardo A. Aroca, Takuji Yamamoto*, Sean T. Nicolson, Yoshiyasu Doi* and Sorin P. Voinigescu, University T. Nicolson, Yoshiyasu Doi* and Sorin P. Voinigescu, University of Toronto, Toronto, Canada, *Fujitsu Laboratories, Kawasaki, of Toronto, Toronto, Canada, *Fujitsu Laboratories, Kawasaki, Japan Japan 1 University of Toronto 2008
25
Embed
A Zero-IF 60GHz Transceiver in 65nm CMOS with > 3.5Gb/s Links Alexander Tomkins, Ricardo A. Aroca, Takuji Yamamoto*, Sean T. Nicolson, Yoshiyasu Doi* and.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
A Zero-IF 60GHz Transceiver in 65nm A Zero-IF 60GHz Transceiver in 65nm CMOS with > 3.5Gb/s LinksCMOS with > 3.5Gb/s Links
Alexander Tomkins, Ricardo A. Aroca, Takuji Yamamoto*, Sean T. Alexander Tomkins, Ricardo A. Aroca, Takuji Yamamoto*, Sean T. Nicolson, Yoshiyasu Doi* and Sorin P. Voinigescu, University of Nicolson, Yoshiyasu Doi* and Sorin P. Voinigescu, University of
Simple architecture appropriate for rapid Simple architecture appropriate for rapid file-transfer -> “Kiosk” applicationsfile-transfer -> “Kiosk” applications
Fundamental frequency, zero-IF Fundamental frequency, zero-IF architecturearchitecture
Direct BPSK modulation/demodulationDirect BPSK modulation/demodulation
Baseband NRZ data recovered with no Baseband NRZ data recovered with no ADCADC
Single-chip with TX and RX integrationSingle-chip with TX and RX integration
Design completed in 3-4 weeks (4 designers), with an immature design-kitDesign completed in 3-4 weeks (4 designers), with an immature design-kit
Performed hand design with only DC sims and no layout parasitic extraction tool.Performed hand design with only DC sims and no layout parasitic extraction tool.
Designed for 60GHz + 10%Designed for 60GHz + 10%
VDDIF+
IF-LNA
DataBuffers
RFin
Datain
LOin
Bias
÷ 2TX-
TX+
Div
Bias
LOTree
BPSK Modulator
Mixer
Divider
12mA
18mA
18mA
18mA
VDD
LO Buffer
Alexander Tomkins – University of Toronto 2008 3
Circuit Design Philosophy in CMOSCircuit Design Philosophy in CMOS
VVDSDS will vary as a result of V will vary as a result of VTT variation variation
Different topologies are required in order to:Different topologies are required in order to:
Work with VWork with VDDDD < 0.9V < 0.9V
VVTT insensitive insensitive
VDD
VVDDDD ≥≥ 1.0V 1.0V
∆∆VVDSDS due to ∆ V due to ∆ VTT
*A 65nm CMOS wafer costs more than a 300GHz SiGe BiCMOS wafer**A 65nm CMOS wafer costs more than a 300GHz SiGe BiCMOS wafer*
CMOS does not make economic sense unless you integrate the DSP CMOS does not make economic sense unless you integrate the DSP
You must ensure that all topologies can scale to 45nm, 32nm ...You must ensure that all topologies can scale to 45nm, 32nm ...
∆ ∆ VVTT
Alexander Tomkins – University of Toronto 2008 4
VG
VDD
VDD
LO+LO- LO-
VDD
Ibias
Vout+ Vout
-
VDD
Ibias
VIN+
XFMR
AC-folded AC-folded CascodeCascode
XFMR-folded XFMR-folded CascodeCascode
Folded-cascode topologies with constant current biasingFolded-cascode topologies with constant current biasing
Only one high-speed transistor is placed between VOnly one high-speed transistor is placed between VDDDD and ground, and ground, maximizing the transistor Vmaximizing the transistor VDSDS..
All mm-wave blocks can be implemented with these topologies: All mm-wave blocks can be implemented with these topologies:
But there is a price: 2x the currentBut there is a price: 2x the current
Circuit Design Philosophy in CMOSCircuit Design Philosophy in CMOS
Input is noise and impedance matched to 50Input is noise and impedance matched to 50ΩΩ, with large output transistors for IIP3 and OP, with large output transistors for IIP3 and OP1dB1dB
80mA (60mA) from 1.2V (1.0V)80mA (60mA) from 1.2V (1.0V)
High gain to reduce receiver NF variation with temperature/processHigh gain to reduce receiver NF variation with temperature/process
Direct BPSK Modulator and MixerDirect BPSK Modulator and Mixer
6Alexander Tomkins – University of Toronto 2008
Data signal directly drives quad transistors of modulator [in SiGe: C. Lee Data signal directly drives quad transistors of modulator [in SiGe: C. Lee et al, CSICS 2004]et al, CSICS 2004]
Equivalent to a digitally modulated PA; operates in saturationEquivalent to a digitally modulated PA; operates in saturation
Both circuits drive off-chip directly in 50Both circuits drive off-chip directly in 50ΩΩ (mixer has no IF amplifier) (mixer has no IF amplifier)
DATA+
DATA- DATA-
90pH 90pH
VDD=1.2V
18mA
Vout+ Vout
-
40um 40um
VDD=1.2V59.2um 59.2um
20mA
VLO+VLO
-
2-coilXFMR0.77mA
VDD=1.2V
81.6um
800Ω
2.4um
83.2um
LO+LO-LO+
50Ω 50Ω
VDD=1.2V
12mA
Vout+ Vout
-
40um 40um
VDD=1.2V
From LNA
59.2um
VDD=1.2V
R=300Ω
R
R
4kΩ
20mA
VDD=1.2V
2-coilXFMR
41.6um
800Ω
0.77mA
2.4um
VDD=1.2V
81.6um
c
R
59.2um
New Frequency Divider TopologyNew Frequency Divider Topology
7Alexander Tomkins – University of Toronto 2008
Single differential pair drives Single differential pair drives both latches:both latches:
Transmit-Receive Test Results – 6Gb/sTransmit-Receive Test Results – 6Gb/s
60.8GHz Carrier60.8GHz Carrier
6.0Gbps 26.0Gbps 277-1 PRBS Signal-1 PRBS Signal
Testing limited by bandwidth of IF amplifier (4GHz)Testing limited by bandwidth of IF amplifier (4GHz)
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0 5 10 15 20 25time (ns)
-0.3
-0.2
-0.1
0
0.1
RX
TX
SummarySummary
19Alexander Tomkins – University of Toronto 2008
1.2V 60GHz zero-IF single-chip transceiver in 65nm CMOS1.2V 60GHz zero-IF single-chip transceiver in 65nm CMOS
Occupies only 1.28x0.81mmOccupies only 1.28x0.81mm22 (1.0mm (1.0mm22), consumes 374mW), consumes 374mW
Simple high-bandwidth, high data-rate architectureSimple high-bandwidth, high data-rate architecture
Proof-of-concept demonstration: wireless link over 2mProof-of-concept demonstration: wireless link over 2m
Data-rates up to 6.0Gb/s demonstrated (IF bandwidth limited above 4GHz)Data-rates up to 6.0Gb/s demonstrated (IF bandwidth limited above 4GHz)
First demonstration of a 60GHz wireless link at 50First demonstration of a 60GHz wireless link at 50ooC C
60GHz transceiver block characterization over process corners, 60GHz transceiver block characterization over process corners, temperature, and power supply.temperature, and power supply.
AcknowledgementsAcknowledgements
20Alexander Tomkins – University of Toronto 2008
This work was funded by Fujitsu Limited. This work was funded by Fujitsu Limited.
Many thanks to Katya Laskin and Ioannis Sarkas for testing, Many thanks to Katya Laskin and Ioannis Sarkas for testing, measurement, and lab support.measurement, and lab support.
The authors would like to thank Jaro Pristupa and CMC for CAD support, The authors would like to thank Jaro Pristupa and CMC for CAD support, CFI, OIT, and ECTI for test equipment. CFI, OIT, and ECTI for test equipment.
We would also like to thank Dr. W. Walker of Fujitsu Laboratories of We would also like to thank Dr. W. Walker of Fujitsu Laboratories of America Inc. for his support.America Inc. for his support.
Tuned SPST switch for 60GHz operationTuned SPST switch for 60GHz operation
High-isolation from series-shunt transistor and 250pH inductorHigh-isolation from series-shunt transistor and 250pH inductor
Lower-insertion loss from 45pH shunt inductorLower-insertion loss from 45pH shunt inductor
Transmit-Receive Link ExperimentTransmit-Receive Link Experiment
23Alexander Tomkins – University of Toronto 2008
Goal: Demonstrate successful data transmissionGoal: Demonstrate successful data transmission
““Bits in, bits out”Bits in, bits out”
Single-ended input data stream (PRBS sequence) fed directly on-chipSingle-ended input data stream (PRBS sequence) fed directly on-chip
Data stream reclaimed directly from the receiver IF output with no ADCData stream reclaimed directly from the receiver IF output with no ADC
One probe-station will act as a transmitter, one as receiverOne probe-station will act as a transmitter, one as receiver
Transmit channel formed by: Transmit channel formed by:
2m wireless link with transmitter/receiver 25dBi horn antenna2m wireless link with transmitter/receiver 25dBi horn antenna
Total channel loss (including input/output losses): 35dBTotal channel loss (including input/output losses): 35dB
Lack of on-chip IF-amp requires an additional external amplifier (limited to Lack of on-chip IF-amp requires an additional external amplifier (limited to 4GHz BW)4GHz BW)
Alexander Tomkins – University of Toronto 2008 24
Data Transmission at 2 Gb/s (50°C)
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0 10 20 30 40 50 60 70time (ns)
-0.3
-0.2
-0.1
0
0.1
Transmit-Receive Test ResultsTransmit-Receive Test Results