A Useful Skew Tree Framework for Inserting Large Safety Margins Rickard Ewetz and Cheng-Kok Koh School of Electrical and Computer Engineering, Purdue University.

A Useful Skew Tree Framework for Inserting Large Safety Margins

Rickard Ewetz and Cheng-Kok KohSchool of Electrical and Computer Engineering, Purdue University

ISPD 2015

Lowering the Point of Divergenceand

Safety Margins

A B A BC D

Skew Constraints

JHj

ijiCQi

jjS

ijiCQi

ttttt

Tttttt

min

max

Combinational Logic

ijiCQ

jHij

jS

ijiCQij

jiij

tttl

tttTu

ttskew

min

max

it iCQt

FFiFFj

jtijtmaxijtmin

jSt

jHt

ijijij uskewl

Safety Margins

ijijij uskewl

ijijijijij muskewml

A B C D

SCG

ab

c

d30

20

D Q

D QD Q

D Qa

b

c

d

4030 ababab uskewl2010 acacac uskewl

4010

bdbdbd uskewl

cdcdcd uskewl bcbcbc uskewl

Insert Safety Margin Muser = 20

ab

c

d10

0

20-10

Negative cycle => no Feasible Arrival times!

Cycles of Skew Constraints

ijjiji mwtt

Cji Cji ijjiji mwtt),( ),(

)(

=0

CCji jiCjiij Wwm

),(

),(

[9] J. Fishburn. Clock skew optimization. IEEETransactions on Computers, pages 945–951, 1990.

10

20

SCG with = 0m

|| min

min

C

WM CMaximum Uniform safety margin

Greedy-UST/DME

D Q D Q D Q D Q

a b c d

Sourcea b c d

FSRab = [-dab, dba]

[17] C.-W. A. Tsao and C.-K. Koh. UST/DME: a clock tree router for general skew constraints. ACM TODAES, pages 359–379, 2002.

ab

d

c

Insertion of Safety Margins in [17]

• Uniform Safety Margins MuserMM user 0

[17] C.-W. A. Tsao and C.-K. Koh. UST/DME: a clock tree router for general skew constraints. ACM TODAES, pages 359–379, 2002.

Yield (%)

Muser (ps)0 15

46.8

100

M = 15 ps

Insertion of Safety Margins in [11]

D Q D Q D Q D Q

a b c d

Sourcea b c d

FSRab = [-dab, dba]

[11] W.-C. D. Lam and C.-K. Koh. Process variation robust clock tree routing. ASP-DAC ’05, pages 606–611, 2005.

M = 15 ps

b c20

10

=ф20 20

Proposal

• Safety margin Muser > Max uniform M • Lower point of divergenceFew constraints that limit the magnitude of M!

Flow UST-LSM FrameworkDecrease SCG edge weights with Muser

Detection of negative cycles

Pre-

synt

hesi

sSy

nthe

sis

Create clusters from negative cycles

Construct trees from cluster 2 to K

Construct clock tree from cluster 1 and the trees from cluster 2 to K

Output

Input

No cycles in SCG Found one cycle in SCG

Reduction of safety margin from edges of negative cycles

Cycle is non-negative

1 2

3 4

8

57312-2

10

3 2 6

1 2

3 4

6

35210

8

-41 0 4

1 2

3 4-41 0

1 2

3 4-32 1

2 3 41

C1 C2

2 3 4 2 3 41

Evaluation of the UST-LSM Framework

Name Clock period

(ns)

Number of nets

Number of cells

Number of sequential elements

Number of skew

constraintsscaled_s1423scaled_s5378scaled_s15850

0.320.320.32

---

---

74179597

78175318

mspfpuecg

12.3040.00

1.00

52394210462164

47874156561491

683715

7674

449901626363440

[8] R. Ewetz and C.-K. Koh. Benchmark circuits for clock scheduling and synthesis. https://purr.purdue.edu/publications/1759, 2015.

Monte Carlo Framework

• Adopted from the ISPD2010 contest [15]• Variations– Supply voltage (15%)– Wire widths (10%)– Temperature (30%)– Channel length (10%)

• Spatial correlations– Quad tree model [1]

• Stage-by-stage with slew propagation [19]

11v

23v 24v

22v21v

[15] C. Sze. ISPD 2010 high performance clock network synthesis contest: Benchmark suite and results. ISPD’10, pages 143–143, 2010.[1] A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. ICCAD’03, pages 900–907, 2003.[19] M. Zhao, K. Gala, V. Zolotov, Y. Fu, R. Panda, R. Ramkumar, and B. Agrawal. Worst case clock skew under power supply variations. TAU ’02, pages 22–28, 2002.

Evaluation metrics

• Metrics:– Yield (skew + transition time)– 95%-slack– Capacitive cost– Run-time

• Designs with loose and tight skew constraints– Loose if no negative cycles with Muser = 100 ps

Designs with loose skew constraints

Safety margin

Muser (ps)

Yield 95%-slack Cap(fF)

Run-time

msp ZSTNo margin

50100

100100100100

80.0080.0080.00

100.00

2473187218721977

209193200184

fpu ZSTNo margin

50100

100100100100

49.1150.0050.0087.63

3185226422644499

78494671

Similar results for scaled_s1423 and scaled_s5378

Designs with Tight Skew Constraints

Safety margin Muser (ps)

ClusteringC2

(num)

Max stagesC3

(num)C4

(num)scaled_s15850scaled_s15850

M+20=47M+20=47

yesno

37

--

--

scaled_s15850scaled_s15850

M+50=77M+50=77

yesno

39

--

--

ecgecg

M+15=30M+15=30

yesno

36

18

--

ecgecg

M+25=40M+25=40

yesno

33

16

11

Tight Skew Constraints

Yield (%)

Muser (ps)0 15 20 25 30 35 40

46.8

100

82.6

98.895.496.293.0

Tight Skew ConstraintsBM Safety

Margin Muser (ps)

Yield (%) 95%-slack Cap (fF) Run-time

scaled_s15850

ZST0

M=27M+10=37M+20=47M+30=57

0.026.496.699.699.8100

-12.98-14.54

3.2311.2517.4024.30

178301452020197259163005034890

136181292678

10921484

ecg ZST0

M=15M+5=20

M+10=25M+15=30M+20=35M+25=40

0.00.0

46.882.693.098.895.496.2

-30.53-19.55

-9.04-5.34-1.134.640.155.17

2587822256448534712956974668298922396845

17711118182717612127236040116388

Illustration on scaled_s15850

Muser = M+ 0 = 27

Muser = M+10 =37

Summary

• Combine the lowering of the point of divergence with insertion of large safety margins!

• Questions