ISOCC 2016 “This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government(MSIP) (No. 2015R1A2A1A13001751).” A Test Methodology to Screen Scan-Path Failures Junghwan Kim, Young-woo Lee, Minho Cheong, Sungyoul Seo and Sungho Kang Department of Electrical & Electronic Engineering Yonsei University Seoul, Korea {kjhcz, roberto, cmh9292, sungyoul}@soc.yonsei.ac.kr and [email protected] Abstract— It is important to screen scan-path failures because scan-path failures affect product yield even though these are not related to the device functional operations. However, the additional efforts such as diagnosis are required to screen scan- path failures. In this paper, we propose a new test methodology to screen scan-path failures under the Automatic-Test-Pattern- Generation (ATPG) constraints and the multi-capture-clock condition without diagnosis. Experimental results show that the proposed methodology efficiently screens scan-path failures with high test coverage. Keywords; scan-path failure; diagnosis I. INTRODUCTION Nowadays, a scan-based testing is a widely used methodology for the higher test coverage and the faster test time. The number of scan chains in Very-Large-Scale- Integrated (VLSI) circuits increases proportionally to gate counts and it is reported that 10% to 30% of all defects cause the scan chains to fail, the scan chain failures account for almost 50% of chip failures [1]. However, if there are scan chain failures, these are not always related to the device functional operations. It depends on the fault location such as the internal of flip-flop or the scan-path; scan-path failures are defined as the scan chain failures but not the functional failures, as shown in Figure 1. In order to screen scan-path failures, the detection of the fault location is required. Many diagnosis techniques have been researched to find the fault locations efficiently. Commonly, the diagnosis techniques are classified into the hardware-assisted, the software-based and the signal profiling [2]. However, these have the following drawbacks. The hardware-assisted diagnosis requires the additional hardware overhead, and the software-based diagnosis needs the additional simulation time. Lastly, the signal profiling diagnosis can find the most accurate the fault location, but it requires the high cost equipment and the long analysis time. Therefore, the objective of this paper is to screen scan-path failures without diagnosis. II. PROPOSED METHODOLOGY Normally, a scan-capture vector is not executed, if the scan chain has a failure, because a capture operation is affected by the shift operations in any scan chains. In the proposal, in order to screen scan-path failures, a specific capture vector is executed even though the scan chain has a failure. Furthermore, a test flow with the specific capture vector is proposed. A. Concept of the proposed vector For the proposed vector, the first step is to find the failed scan chain. It is reasonable to assume that there is only a failed scan chain at a time. There is a simple way to find it with the chain-check vector. Most of ATPG tools support to generate the chain-check vector without the scan-capture operation. Each scan chain has its own scan-in/out pins, respectively. So it is possible to detect which scan chain is failed by analyzing the test result from the scan-out pin using the Automatic-Test- Equipment (ATE). After finding the failed scan chain, it is stored in the ATE memory. Next, it is necessary to generate the specific capture vector called the screening vector using the ATPG tool in order to distinguish scan-path failures from the scan chain failures; the state of flip-flops of the failed scan chain can be observed even though the scan-path is not tested by the screening vector. The scan-in data cannot be loaded into all the flip-flops of the failed scan chain under the SI-Mask constraints. The definition of SI-Mask constraints is that all values of the Q-to-SI path replace with the “X” value. D-ports and Q-ports should not have any constraints to make capture operation free. Normally, a capture vector is generated by the ATPG tool under the single-capture-clock condition. However, the state of flip-flops of the failed scan chain cannot be observed because of the SI-Mask constraints under the single- capture-clock condition. In contrast, the multi-capture-clock vector can solve this problem. Figure 2 represents the comparison of the data route between two vectors when the chain-2 is failed, as an example. The value of the 2-C (flip- flop) is captured from the 1-B at a capture-clock. After the capture operation, the value of the 2-C is shifted to the 2-D and it is changed to the “X” value because of the SI-Mask constraints. So it is not possible to observe the state of 2-C under the single-capture-clock condition. Under the multi- capture-clock condition, the value of 2-B which is captured from the 1-A sequentially transfers to the 3-C at the second- capture-clock. Therefore, it is possible to observe the state of 2- B through the chain-3 although the chain-2 has the SI-Mask constraints. Figure 1. Scan failure according to the fault location 978-1-5090-3219-8/16/$31.00 ©2016 IEEE 150 ISOCC 2016