© 2012 Atrenta Inc. A Systematic Approach to Soft IP Quality Anuj Kumar October 2012
© 2012 Atrenta Inc.
A Systematic Approach to Soft IP Quality
Anuj Kumar October 2012
2 © 2012 Atrenta Inc.
IP Use Is On The Rise
Source: IBS Inc., August 2012
3 © 2012 Atrenta Inc.
And So Is Cost
Much of this IP is soft, or synthesizable
Source: IBS Inc., August 2012
4 © 2012 Atrenta Inc.
Taming Cost Means Reducing Risk
Can’t reach test goals
Routing congestion
Can’t close timing
Too much power
Design bugs
Incomplete deliverables
5 © 2012 Atrenta Inc.
Atrenta’s Approach – IP Kit
Atrenta IP Kit
IP
SpyGlass Clean IP
IP reports
Atrenta DataSheet
Atrenta DashBoard
IP design intent
….
RTL
wai
vers
Standard methodology Setup & run automation
Quickstart Guide
Training module Li
nt +
+
CD
C
DFT
Pow
er
Con
str
SDC
SG
DC
UPF
/CPF
FS
DB
,…
Scripts, setup
Deliverables
Phys
ical
6 © 2012 Atrenta Inc.
Key Component – SpyGlass
Complete platform to optimize RTL - Lint, CDC, DFT, Constraints, Power and Routing Congestion
GuideWare provides best practices for high impact, low noise analysis
RTL problems easily identified
Richest set of engines that identify real implementation issues
7 © 2012 Atrenta Inc.
Design readSetup
Results database
OptimizeDebug
GuideWare Methodology
ConstraintsCDC
Lint
PowerDFT
Automatically generates HTML DashBoard and DataSheet reports
to track design quality & design specs
And Data Management Addition
Configuration Management
System (CVS, Clearcase, RCS, …)
Check-in updates
Automated nightly runs
Met
hodo
logy
SpyGlass RTL Platform
8 © 2012 Atrenta Inc.
And Some Help From Our Friends
TSMC and Atrenta announced the Soft IP Qualification Flow in May 2011 Focus – qualify the robustness and completeness of synthesizable IP that is part of the TSMC 9000 library for TSMC’s customers
9 © 2012 Atrenta Inc.
Overview of TSMC Program
IP1
IP 2
IP 3
IP n
IP ecosystem partners
Handoff
Atrenta DashBoard
Atrenta DataSheet
Atrenta summary reports
● ● ●
Atrenta IP Kit
Chip project 1
Chip project 2
Chip project 3
Chip project n
End customers
Atrenta IP Kit
Inspection/ Acceptance
● ●
●
TSMC Online
10 © 2012 Atrenta Inc.
WHAT DOES THE IP KIT CHECK AND WHAT HAVE WE FOUND?
11 © 2012 Atrenta Inc.
Sample Tests – IP Handoff Kit V 1.0 What will the average power dissipation be?
Are my power domains correctly defined?
Are clock and reset constraints set properly?
Are clock definitions consistent, correct and complete?
Are clock domain crossing synchronizers bug-free?
Are timing constraints consistent across block boundaries?
Are false path and multi-cycle paths correctly identified?
Is the design ready for simulation and synthesis?
What will the stuck-at and at-speed test coverage be?
Can all sequential elements be scanned?
Lint
Test
Power
Clocks &
Timing
12 © 2012 Atrenta Inc.
What Did We Find?
Many items that would impact integration/debug time and chip function were found & fixed
Some examples:
Missing synchronizers on CDC paths causing possible chip function issues
Data loss on a fast-slow CDC paths
Uncontrolled data path impacting transition fault coverage
Index out of range which causes synthesizability issues
Unconstrained I/O ports leading to poor SDC coverage
13 © 2012 Atrenta Inc.
IP Kit 2.0 – Need & Motivation
Improve soft IP handoff quality checks Align TSMC IP Kit methodology with Atrenta’s latest GuideWare 2.0
methodology providing high coverage and low noise IP handoff checks Introduce additional design checks
• Advanced formal lint (e.g., X-assignment, dead code detection, etc.) • Physical implementation data (e.g., area, timing & congestion)
Improve the IP Kit setup & flow execution Automatic generation of setup files Flexibility in goal running (single/multiple/goal group) Incremental analysis
Easier integration of SpyGlass in customer’s existing design flow
Improved IP packaging
14 © 2012 Atrenta Inc.
IP Kit 2.0 Execution Flow
IP Packaging >% aipk_pack –top foo –save_all
Advanced Design Checks >% aipk_run –top foo –goals adv_check
Basic Design Checks >% aipk_run –top foo –goals basic_check
Design Setup Checks >% aipk_read –top foo
Design Read >% aipk_read -top foo –srcfile foo.f –libfile lib.f –sdcfile foo.sdc -activity_file foo.vcd
Auto-generation of SpyGlass setup files (.prj, .sgdc, .swl, .dat etc) Generation of Design Read DashBoard report Ensures that RTL is read successfully in SpyGlass
Identifies unconstrained clock/resets in the design
Ensures that design setup is complete & correct
Runs basic IP Handoff checks (Lint, CDC-structural, DFT, SDC, Power)
Generates quality report for basic design checks/goals
Runs Advanced IP Handoff checks (CDC-functional, Lint-functional and Physical)
Generates overall quality report combining results for basic & advanced checks
Packages an IP with design intent, setup & analysis reports
15 © 2012 Atrenta Inc.
Design Read DashBoard Report
16 © 2012 Atrenta Inc.
TSMC IP Kit 2.0 – Mandatory Goals
Domain Goal Name Purpose Handoff Check Type
Lint
lint_rtl Checks the design for simulation/synthesis readiness, connectivity & structural issues Basic
clock_reset_integrity Checks the integrity of clock and reset propagation and architecture Basic
Advanced Lint
adv_lint_struct Checks for X-assignment, FSM transition, deadlock issues based design topology analysis Advanced
adv_lint_verify Checks the functional issues in FSM transition, static code, bus overflow & X-assignments based on formal verification analysis Advanced
CDC
cdc_setup_check Checks the completeness of clock & reset constraints Basic
cdc_structural_check Exhaustive verification all synchronization checking for CDCs and asynchronous reset signals based on design topology checking Basic
cdc_functional_check Exhaustive verification of functional aspects of the CDC path and synchronizers using formal analysis techniques Advanced
DFT
dft_best_practices Checks the design for best practices to increase ATPG effectiveness and efficiency Basic
dft_scan_ready Checks if all sequential elements are scannable or not. Also generates the coverage audit report Basic
dft_test_points Helps in improving the test coverage by identifying the uncontrollable and unobservable nodes in the design Basic
dft_dsm_clocks Helps in defining the clocks used for at-speed testing and any associated PLL ,etc. Basic
dft_dsm_best_practices Addresses special needs of cases such as d-pin controllability, test clock domains and path issues. Also generates the transition coverage audit report Basic
Goal Enhanced Legend: New Goal Added
17 © 2012 Atrenta Inc.
Domain Goal Name Purpose Handoff Check Type
Power power_est_average Estimates the average power of the design Basic
Power Verification
power_verif_instr_rtl Verifies the desired power intent in the RTL design as per given power constraints Basic
Constraints
sdc_setup_check Performs sanity checking on SDC file Basic
sdc_audit Computes constraints coverage for design objects like as IOs, flops, etc. Basic
sdc_check Ensures that clock & IO delay definitions defined in the SDC file are consistent, correct & complete Basic
sdc_exception_struct Ensures that given timing exceptions constraints exist in the design Basic
sdc_redundancy_check Help in removing the redundancy in constraints definition Basic
TXV fp_verification Helps in the verification of false path constraints Advanced
mcp_verification Helps in the verification of multi-cycle path constraints Advanced
Physical physical_analysis_signoff Performs physical analysis using vendor library, used for signoff on area, congestion and timing (based on pre-floorplan checks) Advanced
TSMC IP Kit 2.0 – Mandatory Goals
Goal Enhanced Legend: New Goal Added
18 © 2012 Atrenta Inc.
TSMC IP Kit 2.0 – Optional Goals Domain Goal Name Purpose Handoff
Check Type
Lint design_audit Provides basic design profile data and generates the IO data for the population of DataSheet reports. This goal is automatically run during IP Kit Design Read stage, hence kept as an optional goal and user does not need to run it explicitly
Basic
Power
power_audit
Reports all given key design data, inputs and parameters, which will be used for power estimation analysis. This report indicates the completeness of design setup for power estimation analysis. . This goal is automatically run during the IP Kit Design Read stage, hence kept as an optional goal and user does not need to run it explicitly
Basic
power_est_cycle Calculate power for each cycle of the simulation profile file. As this goal computes power for each cycle of simulation waveform, it may take huge run time if given simulation file(VCD/FSDB) is quite big, hence kept as an optional goal
Basic
Power Verification power_verif_audit
Does the audit/completeness check on given UPF/CPF file. This goal is automatically run during the IP Kit Design Read stage if the user has provided any power intent file like UPF or CPF. Hence kept as an optional goal
Basic
Constraints
sdc_hierarchical_check Ensures that constraints are consistent across the block boundaries. This goal would become applicable for running if SDC files exist both for the top design and underlying sub-blocks
Basic
sdc_equiv Ensures that different versions of the SDC files are equivalent for the same design. This goal can only be run if there exist two sets of the SDC file(s) for an IP
Advanced
Physical physical_library_preparation Prepare the technology library in the requisite OA format, which is a must for running other SpyGlass Physical goal runs. . This goal is automatically run during the IP Kit Design Read stage, hence kept as an optional goal and user does not need to run it again explicitly
Advanced
Goal Enhanced Legend: New Goal Added
19 © 2012 Atrenta Inc.
IP Kit 2.0 vs. 1.0 Benchmark Data
Design Quality Objective
IP#1 IP#2 IP#3 Comments
IPK 2.0 IPK 1.0 IPK 2.0 IPK 1.0 IPK 2.0 IPK 1.0
Unsynchronized CDC paths 236 240 0 0 102 106 CDC goal optimized to avoid false unsynchronized violations
Stuck-at fault coverage 82.7 82.7 100 100 99.8 99.8
Stuck-at test coverage 83.7 83.7 100 100 99.8 99.8
% of scannable flops 89 89 100 100 99 99
Transition fault coverage 51.3 51.3 95.5 95.5 73.3 73.3
Transition test coverage 77.7 77.7 95.8 95.8 95.2 95.2
% of IO ports constrained in SDC file 93.9 93.9 100 100 100 100
% of registers constraints in SDC file 100 100 100 100 100 100
Switching power(in mW) 0.32 0.32 5.98 5.98 2.24 2.24
Internal power(in mW) 1.05 1.05 44.2 44.2 11.5 11.5
Leakage power(in mW) 0.005 0.005 0.13 0.13 0.02 0.02
Total power(in mW) 1.37 1.37 50.3 50.3 13.8 13.8
Improved QA Legend: Additional QA
20 © 2012 Atrenta Inc.
Benchmark Data (cont’d)
Design Quality Objective
IP#1 IP#2 IP#3 Comments
IPK 2.0 IPK 1.0 IPK 2.0 IPK 1.0 IPK 2.0 IPK 1.0
Gate count (NAND equivalent) 9.2K 9.9K 1.72M 2.2M 48K 70.5K Gate count calculation is more accurate in IP Kit K2.0 – based on SpyGlass Physical analysis
Flop count 741 745 50422 53581 4490 4546
Latch count 5 5 1175 1179 0 0
No. of timing paths failing 0 NA 0 NA 0 NA
No. of congested module instances 0 NA 10 NA 0 NA
Floating inputs 0 0 0 0 0 0
Multiply driven nets 0 0 0 0 0 0
Cyclomatic complexity 63 NA 1559 NA 257 NA
Run time for common (existing) goals 824 1109 8197 9520 9550 9616 Run time reduced an average by 10-15% for
common goals
Total number of errors 619 386 1147 125 122 115 New & improved error rules catching additional critical design issues
Total number of warnings 796 1369 1911 7614 214 918 Goal enhancement/optimization helped to control the violation reported for less severe rules (warnings)
Improved QA Legend: Additional QA
21 © 2012 Atrenta Inc.
IP Specification Report SpyGlass DataSheet report capturing key design specifications and profile
statistics, once all goals run are finished
Design Read
Design Setup Check
Design Analysis
IP Packaging
22 © 2012 Atrenta Inc.
Design Quality & Status Summary Report
SpyGlass DashBoard report capturing the high-level design quality metrics and goal run summary report, once all goals run are finished
23 © 2012 Atrenta Inc.
Conclusion
Soft IP qualification can be automated Results in higher quality deliverables, reduced cost and better schedules All soft IP can be improved System is currently deployed at several large customers and through TSMC’s soft IP qualification program TSMC program participation growing and on-track
© 2012 Atrenta Inc.
Thank you!