21.01.2008 13th Asia and South Pacific Design Automation Conference ASP-DAC 2008,Seoul, Korea January 21-24, 2008 A Symbolic Approach for A Symbolic Approach for Mixed Mixed - - Signal Model Checking Signal Model Checking Alexander Jesser, Alexander Jesser, Lars Lars Hedrich Hedrich
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A Symbolic Approach for Mixed-Signal Model Checking
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21.01.2008
13th Asia and South Pacific Design Automation Conference ASP-DAC 2008,Seoul, Korea January 21-24, 2008
A Symbolic Approach for A Symbolic Approach for MixedMixed--Signal Model CheckingSignal Model Checking
Alexander Jesser, Alexander Jesser, Lars Lars HedrichHedrich
2Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
Outline
Mixed-Signal System DecompositionReal-Time Transition Structure (RTTS)Computational Data structure (MTBDDs)CTL-AT as the Specification languageMS Verification FlowCTL-AT Evaluation AlgorithmsVerification Results (PLL)Summary
3Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
Mixed-Signal Decomposition (Interfaces)
( ) ( )max 1( ) ( )min 1
: ( ) 1, 1 ,( ) ( ( ))
: ( ) 0, 1 ,
i id k k
a d k i id k k
u u t i n t t tu t inj u t
u u t i n t t t+
+
⎧ = ∀ ≤ ≤ ≤ <= = ⎨
= ∀ ≤ ≤ ≤ <⎩
( ) ( ) ( )
( ) ( ) ( )
1: ( ) , 1( ) ( ( ))
0 : ( ) , 1
i i id a k thresh
d k a i i id a k thresh
y y t y i my t quant y t
y y t y i m⎧ = ≥ ∀ ≤ ≤
= = ⎨= < ∀ ≤ ≤⎩
A/D-Interface: 1-bit quantizer:
D/A-Interconnection: ramp function:
4Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
Real Timed Transition Structure
t0
t1t2
t3
L(s1)
L(s3)
L(s2)
L(s4)
g0
g1
g3
g2
• Real Timed Transition Structures (RTTS) • Time extension of Kripke structures
• Time delay represents the dynamic behavior ofthe system
• Inputs are necessary because of theintercommunication of both subsystems
• Basic structure for the analog specificationlanguage CTL-AT
• L … labeling function• ti … delay time• gi …inputs
5Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
Characteristic Transition Function (CTF)
: ( , , )( , , )
: ( , , )s s g
s s gs s gδ
τ δχ
δ
++
+
⎧ ∈=⎨
∞ ∉⎩
Transition MTBDD:
Characteristic transition function (CTF)
,,
( ( ))( ( ))( ( , ))i j
i j i j i js s
z z s z z s g g s sδχ τ += ⋅ ≡ ≡ ≡∨
1 2 1 2
1 2 1 2
1 2 1 2
1 2 2 2 2 1 2 1
0.3 ( )
0.4 ( )
0.6 ( )
( )
z z z z g
z z z z g
z z z z g
z z z z g z z z z
δχ+ +
+ +
+ +
+ + + +
= ⋅ ∨
⋅ ∨
⋅ ∨
∞ ⋅ ∨ ∨ ∨ ∨
RTTS:
g
g
g0.3
00
0.4
0.6
01
10
11
6Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
CTL-AT syntax
{ , }A E∈
| | | | | |a z v U RΦ = ∗ Φ Φ ¬Φ ◊ Φ Φ Φ Φ Φ
[ , ] , ,l h l h l ht t t t t t= ∈ ≤
{ , , , , }
• CTL-AT is CTL extended by:• Analog (state) variables (e.g. voltages, currents)
• e.g.: (V2 > 1.456)• Inequalities for describing analog state regions• Time Intervals [tl … th] for describing real-time behavior• Inverse time path operators
• Y=X-1, P=F-1, H=G1, S=U-1
• Syntax:
X F G U R◊∈{ , , , }∗∈ ≤ ≥ < >
{ , }∈ ∨ ∧
v∈
a AP∈
z… atomic proposition
… analog state variable… state boundaries
7Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
CTL-AT semantics
• Equivalencessimilar to CTL
• Formal semantic
8Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
MS - model checking flow
MS -netlist
Analog:DAEs/Netlist
Digital:Bools./Gate
Analog state space
discretization
Construction of
MTBDDs
Frontend
FSM
9Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
Discrete modelling of analog circuits
uein
R 1 L1
D 1 C 1
Circuit
DAE system
Infinity state spaceDiscrete transitionsystem
MNA
Solution
Discretizationt1
t2
t3
Symbolic transformation
Transition MTBDDt1
t2
t3
10Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
11Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
Mixed CTL-AT properties
• Mixed CTL-AT formula consists of analog and digital initialstates
D Aϕ ϕ ϕ= ∧
• Evaluation of MS CTL-AT formulas can not be doneindependent to the appropriate other subsystem
[ , ]( ) [ , ]( ) [ , ]( )A DD AMS D Al h l h l hEF t t EF t t EF t tϕ ϕ ϕ= ∧
• Pre-image computation by variable quantification
+ +δ ϕ
+ +δ ϕ
ϕ =∃ ∃ ∃ χ ∧ χ
ϕ =∃ ∃ ∀ χ ∧ χ
EX( ) z e w : (z,e,w) (z )
AX( ) z e w : (z,e,w) (z )∈∈ d a d a
w {u,v,u,y}e {u ,u ,y ,y }
12Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
MS CTL-AT Algorithms
Problems:• Different time characteristics
• Digital: synchronous• Analog: continuous
• Interaction between both sub-circuits
13Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
MS CTL-AT Algorithms (ex.: EF operation)
• Assumption: Global digital clock clkτ
• Taking care about time constraints• Simple EX operation (Quantification)• Returns results and front state forfurther processing
14Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
MS CTL-AT Algorithms (ex.: EF operation)
• Different transition delay times
• Taking care about time constraints• Simple EX operation (Quantification)• Recursive traversaling through theanalog state space
• Returns results and front state forfurther processing
15Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
MS CTL-AT Algorithms (CheckImpact)
• Analysis of dependentintercommunication signals
• Modifies the accordingtransition MTBDD
16Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
MScheck Demonstration
1 4[ , ]( )l hEF t t D A∧
: A Di clki t t∀ ≤
Assumption (w.l.o.g.):
CTL-AT formula:
17Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
Example: Phase Locked Loop (PLL)
A/D
LPF VCO
Phasedetector
Ref.clock
D/A
CP
Legend:CP: charge pumpLPF: Low Pass FilterVCO: Voltage Control
Oscillator
Schematic
18Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
Verification Results
| [0.0 , 20.0 ]( )lock D AEP ms msφ φ φ= ∧
| [0.0 ,30.0 ]( )locktrue AF ms ms φ=
ReachabilityReachability
Locking behaviorLocking behavior
Verification Results:
v
0.08
-0.08
2C
-3.1 3.1v1C
VCO state space Analog sub-state space
19Alexander JesserA Symbolic Approach for Mixed-Signal Model Checking
Conclusion
• A symbolic approach for Mixed-Signal model checkingis given based on
• Real-Time transition structures (RTTS) • MTBDDs representing transition relations• CTL-AT as the specification language• based on modified fixpoint algorithms for evaluatingCTL-AT formulas
• The approach is demonstrated on a PLL• analyzing reachability and• locking behavior